1.. SPDX-License-Identifier: BSD-3-Clause 2 Copyright(c) 2024 Marvell. 3 4Odyssey ODM DMA Device Driver 5============================= 6 7The ``odm`` DMA device driver provides a poll-mode driver (PMD) 8for Marvell Odyssey DMA Hardware Accelerator block found in Odyssey SoC. 9The block supports only mem to mem DMA transfers. 10 11ODM DMA device can support up to 32 queues and 16 VFs. 12 13Device Setup 14------------ 15 16ODM DMA device is initialized by kernel PF driver. 17The PF kernel driver is part of Marvell software packages for Odyssey. 18 19Kernel module can be inserted as in below example:: 20 21 sudo insmod odyssey_odm.ko 22 23ODM DMA device can support up to 16 VFs:: 24 25 sudo echo 16 > /sys/bus/pci/devices/0000\:08\:00.0/sriov_numvfs 26 27Above command creates 16 VFs with 2 queues each. 28 29The ``dpdk-devbind.py`` script, included with DPDK, 30can be used to show the presence of supported hardware. 31Running ``dpdk-devbind.py --status-dev dma`` 32will show all the Odyssey ODM DMA devices. 33 34Devices using VFIO drivers 35~~~~~~~~~~~~~~~~~~~~~~~~~~ 36 37The HW devices to be used will need to be bound to a user-space IO driver. 38The ``dpdk-devbind.py`` script can be used to view the state of the devices 39and to bind them to a suitable DPDK-supported driver, such as ``vfio-pci``. 40For example:: 41 42 dpdk-devbind.py -b vfio-pci 0000:08:00.1 43 44Device Probing and Initialization 45~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 46 47To use the devices from an application, the dmadev API can be used. 48 49Once configured, the device can then be made ready for use 50by calling the ``rte_dma_start()`` API. 51 52Performing Data Copies 53~~~~~~~~~~~~~~~~~~~~~~ 54 55Refer to the :ref:`Enqueue / Dequeue API <dmadev_enqueue_dequeue>` 56section of the dmadev library documentation 57for details on operation enqueue and submission API usage. 58 59Performance Tuning Parameters 60~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 61 62To achieve higher performance, DMA device needs to be tuned 63using PF kernel driver module parameters. 64 65Following options are exposed by kernel PF driver via devlink interface 66for tuning performance. 67 68``eng_sel`` 69 70 ODM DMA device has 2 engines internally. Engine to queue mapping is decided 71 by a hardware register which can be configured as below:: 72 73 /sbin/devlink dev param set pci/0000:08:00.0 name eng_sel value 3435973836 cmode runtime 74 75 Each bit in the register corresponds to one queue. 76 Each queue would be associated with one engine. 77 If the value of the bit corresponding to the queue is 0, then engine 0 would be picked. 78 If it is 1, then engine 1 would be picked. 79 80 In the above command, the register value is set as 81 ``1100 1100 1100 1100 1100 1100 1100 1100`` 82 which allows for alternate engines to be used with alternate VFs 83 (assuming the system has 16 VFs with 2 queues each). 84 85``max_load_request`` 86 87 Specifies maximum outstanding load requests on internal bus. 88 Values can range from 1 to 512. 89 Set to 512 for maximum requests in flight.:: 90 91 /sbin/devlink dev param set pci/0000:08:00.0 name max_load_request value 512 cmode runtime 92