1c6fe65f0SNicolas Chautru.. SPDX-License-Identifier: BSD-3-Clause 2c6fe65f0SNicolas Chautru Copyright(c) 2023 Intel Corporation 3c6fe65f0SNicolas Chautru 4c6fe65f0SNicolas Chautru.. include:: <isonum.txt> 5c6fe65f0SNicolas Chautru 6c6fe65f0SNicolas ChautruIntel\ |reg| vRAN Boost v2 Poll Mode Driver (PMD) 7c6fe65f0SNicolas Chautru================================================= 8c6fe65f0SNicolas Chautru 9c6fe65f0SNicolas ChautruThe Intel\ |reg| vRAN Boost integrated accelerator enables 10c6fe65f0SNicolas Chautrucost-effective 4G and 5G next-generation virtualized Radio Access Network (vRAN) 11c6fe65f0SNicolas Chautrusolutions. 12c6fe65f0SNicolas ChautruThe Intel vRAN Boost v2.0 (VRB2 in the code) is specifically integrated on the 13c6fe65f0SNicolas ChautruIntel\ |reg| Xeon\ |reg| Granite Rapids-D Process (GNR-D). 14c6fe65f0SNicolas Chautru 15c6fe65f0SNicolas ChautruFeatures 16c6fe65f0SNicolas Chautru-------- 17c6fe65f0SNicolas Chautru 18c6fe65f0SNicolas ChautruIntel vRAN Boost v2.0 includes a 5G Low Density Parity Check (LDPC) encoder/decoder, 19c6fe65f0SNicolas Chautrurate match/dematch, Hybrid Automatic Repeat Request (HARQ) with access to DDR 20c6fe65f0SNicolas Chautrumemory for buffer management, a 4G Turbo encoder/decoder, 21c6fe65f0SNicolas Chautrua Fast Fourier Transform (FFT) block providing DFT/iDFT processing offload 22c6fe65f0SNicolas Chautrufor the 5G Sounding Reference Signal (SRS), a MLD-TS accelerator, a Queue Manager (QMGR), 23c6fe65f0SNicolas Chautruand a DMA subsystem. 24c6fe65f0SNicolas ChautruThere is no dedicated on-card memory for HARQ, the coherent memory on the CPU side is being used. 25c6fe65f0SNicolas Chautru 26c6fe65f0SNicolas ChautruThese hardware blocks provide the following features exposed by the PMD: 27c6fe65f0SNicolas Chautru 28c6fe65f0SNicolas Chautru- LDPC Encode in the Downlink (5GNR) 29c6fe65f0SNicolas Chautru- LDPC Decode in the Uplink (5GNR) 30c6fe65f0SNicolas Chautru- Turbo Encode in the Downlink (4G) 31c6fe65f0SNicolas Chautru- Turbo Decode in the Uplink (4G) 32c6fe65f0SNicolas Chautru- FFT processing 33c6fe65f0SNicolas Chautru- MLD-TS processing 34c6fe65f0SNicolas Chautru- Single Root I/O Virtualization (SR-IOV) with 16 Virtual Functions (VFs) per Physical Function (PF) 35c6fe65f0SNicolas Chautru- Maximum of 2048 queues per VF 36c6fe65f0SNicolas Chautru- Message Signaled Interrupts (MSIs) 37c6fe65f0SNicolas Chautru 38c6fe65f0SNicolas ChautruThe Intel vRAN Boost v2.0 PMD supports the following bbdev capabilities: 39c6fe65f0SNicolas Chautru 40c6fe65f0SNicolas Chautru* For the LDPC encode operation: 41c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_CRC_24B_ATTACH``: set to attach CRC24B to CB(s). 42c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_RATE_MATCH``: if set then do not do Rate Match bypass. 43c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_INTERLEAVER_BYPASS``: if set then bypass interleaver. 44c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_ENC_SCATTER_GATHER``: supports scatter-gather for input/output data. 45c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_ENC_CONCATENATION``: concatenate code blocks with bit granularity. 46c6fe65f0SNicolas Chautru 47c6fe65f0SNicolas Chautru* For the LDPC decode operation: 48c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK``: check CRC24B from CB(s). 49c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP``: drops CRC24B bits appended while decoding. 50c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK``: check CRC24A from CB(s). 51c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_CRC_TYPE_16_CHECK``: check CRC16 from CB(s). 52c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE``: provides an input for HARQ combining. 53c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE``: provides an input for HARQ combining. 54c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE``: disable early termination. 55c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_DEC_SCATTER_GATHER``: supports scatter-gather for input/output data. 56c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION``: supports compression of the HARQ input/output. 57c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_LLR_COMPRESSION``: supports LLR input compression. 58c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_HARQ_4BIT_COMPRESSION``: supports compression of the HARQ input/output. 59c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_SOFT_OUT_ENABLE``: set the APP LLR soft output. 60c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_SOFT_OUT_RM_BYPASS``: set the APP LLR soft output after rate-matching. 61c6fe65f0SNicolas Chautru - ``RTE_BBDEV_LDPC_SOFT_OUT_DEINTERLEAVER_BYPASS``: disables the de-interleaver. 62c6fe65f0SNicolas Chautru 63c6fe65f0SNicolas Chautru* For the turbo encode operation: 64c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_CRC_24B_ATTACH``: set to attach CRC24B to CB(s). 65c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_RATE_MATCH``: if set then do not do Rate Match bypass. 66c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_ENC_INTERRUPTS``: set for encoder dequeue interrupts. 67c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_RV_INDEX_BYPASS``: set to bypass RV index. 68c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER``: supports scatter-gather for input/output data. 69c6fe65f0SNicolas Chautru 70c6fe65f0SNicolas Chautru* For the turbo decode operation: 71c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_CRC_TYPE_24B``: check CRC24B from CB(s). 72c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE``: perform subblock de-interleave. 73c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_DEC_INTERRUPTS``: set for decoder dequeue interrupts. 74c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN``: set if negative LLR input is supported. 75c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP``: keep CRC24B bits appended while decoding. 76c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_DEC_CRC_24B_DROP``: option to drop the code block CRC after decoding. 77c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_EARLY_TERMINATION``: set early termination feature. 78c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_DEC_SCATTER_GATHER``: supports scatter-gather for input/output data. 79c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_HALF_ITERATION_EVEN``: set half iteration granularity. 80c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_SOFT_OUTPUT``: set the APP LLR soft output. 81c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_EQUALIZER``: set the turbo equalizer feature. 82c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_SOFT_OUT_SATURATE``: set the soft output saturation. 83c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_CONTINUE_CRC_MATCH``: set to run an extra odd iteration after CRC match. 84c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT``: set if negative APP LLR output supported. 85c6fe65f0SNicolas Chautru - ``RTE_BBDEV_TURBO_MAP_DEC``: supports flexible parallel MAP engine decoding. 86c6fe65f0SNicolas Chautru 87c6fe65f0SNicolas Chautru* For the FFT operation: 88c6fe65f0SNicolas Chautru - ``RTE_BBDEV_FFT_WINDOWING``: flexible windowing capability. 89c6fe65f0SNicolas Chautru - ``RTE_BBDEV_FFT_CS_ADJUSTMENT``: flexible adjustment of Cyclic Shift time offset. 90c6fe65f0SNicolas Chautru - ``RTE_BBDEV_FFT_DFT_BYPASS``: set for bypass the DFT and get directly into iDFT input. 91c6fe65f0SNicolas Chautru - ``RTE_BBDEV_FFT_IDFT_BYPASS``: set for bypass the IDFT and get directly the DFT output. 92c6fe65f0SNicolas Chautru - ``RTE_BBDEV_FFT_WINDOWING_BYPASS``: set for bypass time domain windowing. 93c6fe65f0SNicolas Chautru 94c6fe65f0SNicolas Chautru* For the MLD-TS operation: 95c6fe65f0SNicolas Chautru - ``RTE_BBDEV_MLDTS_REP``: set to repeat and reuse channel across operations. 96c6fe65f0SNicolas Chautru 97c6fe65f0SNicolas ChautruInstallation 98c6fe65f0SNicolas Chautru------------ 99c6fe65f0SNicolas Chautru 100c6fe65f0SNicolas ChautruSection 3 of the DPDK manual provides instructions on installing and compiling DPDK. 101c6fe65f0SNicolas Chautru 102c6fe65f0SNicolas ChautruDPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual. 103c6fe65f0SNicolas ChautruThe bbdev test application has been tested with a configuration 40 x 1GB hugepages. 104c6fe65f0SNicolas ChautruThe hugepage configuration of a server may be examined using: 105c6fe65f0SNicolas Chautru 106c6fe65f0SNicolas Chautru.. code-block:: console 107c6fe65f0SNicolas Chautru 108c6fe65f0SNicolas Chautru grep Huge* /proc/meminfo 109c6fe65f0SNicolas Chautru 110c6fe65f0SNicolas Chautru 111c6fe65f0SNicolas ChautruInitialization 112c6fe65f0SNicolas Chautru-------------- 113c6fe65f0SNicolas Chautru 114c6fe65f0SNicolas ChautruWhen the device first powers up, its PCI Physical Functions (PF) 115c6fe65f0SNicolas Chautrucan be listed through these commands for Intel vRAN Boost v2: 116c6fe65f0SNicolas Chautru 117c6fe65f0SNicolas Chautru.. code-block:: console 118c6fe65f0SNicolas Chautru 119c6fe65f0SNicolas Chautru sudo lspci -vd8086:57c2 120c6fe65f0SNicolas Chautru 121c6fe65f0SNicolas ChautruThe physical and virtual functions are compatible with Linux UIO drivers: 122c6fe65f0SNicolas Chautru``vfio`` (preferred) and ``igb_uio`` (legacy). 123c6fe65f0SNicolas ChautruHowever, in order to work the 5G/4G FEC device first needs to be bound 124c6fe65f0SNicolas Chautruto one of these Linux drivers through DPDK. 125c6fe65f0SNicolas Chautru 126c6fe65f0SNicolas Chautru 127c6fe65f0SNicolas ChautruConfigure the VFs through PF 128c6fe65f0SNicolas Chautru~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 129c6fe65f0SNicolas Chautru 130c6fe65f0SNicolas ChautruThe PCI virtual functions must be configured before working or getting assigned 131c6fe65f0SNicolas Chautruto VMs/Containers. 132c6fe65f0SNicolas ChautruThe configuration involves allocating the number of hardware queues, priorities, 133c6fe65f0SNicolas Chautruload balance, bandwidth and other settings necessary for the device 134c6fe65f0SNicolas Chautruto perform FEC functions. 135c6fe65f0SNicolas Chautru 136c6fe65f0SNicolas ChautruThis configuration needs to be executed at least once after reboot or PCI FLR 137c6fe65f0SNicolas Chautruand can be achieved by using the functions ``rte_acc_configure()``, 138c6fe65f0SNicolas Chautruwhich sets up the parameters defined in the compatible ``rte_acc_conf`` structure. 139c6fe65f0SNicolas Chautru 140c6fe65f0SNicolas Chautru 141c6fe65f0SNicolas ChautruTest Application 142c6fe65f0SNicolas Chautru---------------- 143c6fe65f0SNicolas Chautru 144*22900d7fSNicolas ChautruBBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing 145*22900d7fSNicolas Chautruthe functionality of the device, depending on the device's capabilities. 146c6fe65f0SNicolas Chautru 147*22900d7fSNicolas ChautruFor more details on how to use the test application, 148*22900d7fSNicolas Chautrusee :ref:`test_bbdev_application`. 149c6fe65f0SNicolas Chautru 150c6fe65f0SNicolas Chautru 151c6fe65f0SNicolas ChautruTest Vectors 152c6fe65f0SNicolas Chautru~~~~~~~~~~~~ 153c6fe65f0SNicolas Chautru 154c6fe65f0SNicolas ChautruIn addition to the simple LDPC decoder and LDPC encoder tests, 155c6fe65f0SNicolas Chautrubbdev also provides a range of additional tests under the test_vectors folder, 156c6fe65f0SNicolas Chautruwhich may be useful. 157c6fe65f0SNicolas ChautruThe results of these tests will depend on the device capabilities which may 158c6fe65f0SNicolas Chautrucause some test cases to be skipped, but no failure should be reported. 159c6fe65f0SNicolas Chautru 160c6fe65f0SNicolas Chautru 161c6fe65f0SNicolas ChautruAlternate Baseband Device configuration tool 162c6fe65f0SNicolas Chautru~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 163c6fe65f0SNicolas Chautru 164c6fe65f0SNicolas ChautruOn top of the embedded configuration feature supported in test-bbdev using 165c6fe65f0SNicolas Chautru"- -init-device" option mentioned above, there is also a tool available 166c6fe65f0SNicolas Chautruto perform that device configuration using a companion application. 167c6fe65f0SNicolas ChautruThe ``pf_bb_config`` application notably enables then to run bbdev-test 168c6fe65f0SNicolas Chautrufrom the VF and not only limited to the PF as captured above. 169c6fe65f0SNicolas Chautru 170c6fe65f0SNicolas ChautruSee for more details: https://github.com/intel/pf-bb-config 171c6fe65f0SNicolas Chautru 172c6fe65f0SNicolas ChautruSpecifically for the bbdev Intel vRAN Boost v2 PMD, the command below can be used 173c6fe65f0SNicolas Chautru(note that ACC200 was used previously to refer to VRB2): 174c6fe65f0SNicolas Chautru 175c6fe65f0SNicolas Chautru.. code-block:: console 176c6fe65f0SNicolas Chautru 177c6fe65f0SNicolas Chautru pf_bb_config VRB2 -c ./vrb2/vrb2_config_vf_5g.cfg 178c6fe65f0SNicolas Chautru test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -b 64 -l 1 -v ./ldpc_dec_default.data 179