regex/mlx5: utilize all available queue pairs

Fix overflow of free QP mask.
Regex used 64 QPs and used a bitmask to select a free QP for use.
The bitmask in use was only 32 bits so did not allow hal

regex/mlx5: utilize all available queue pairs

Fix overflow of free QP mask.
Regex used 64 QPs and used a bitmask to select a free QP for use.
The bitmask in use was only 32 bits so did not allow half of the QPs
to be utilised.
Upgraded to 64 bit mask and using ffsll now instead of ffs.

Fixes: 270032608503 ("regex/mlx5: refactor HW queue objects")
Cc: stable@dpdk.org

Signed-off-by: Gerry Gribbon <ggribbon@nvidia.com>

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regex/mlx5: support combined ROF file

Added support to allow parsing of a combined ROF file to
locate compatible binary ROF data for the Bluefield hardware
being run on.

Signed-off-by: Gerry Gribbo

regex/mlx5: support combined ROF file

Added support to allow parsing of a combined ROF file to
locate compatible binary ROF data for the Bluefield hardware
being run on.

Signed-off-by: Gerry Gribbon <ggribbon@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>

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regexdev: add maximum number of mbuf segments

Allows application to query maximum number of mbuf segments that can
be chained together.

Signed-off-by: Gerry Gribbon <ggribbon@nvidia.com>
Acked-by:

regexdev: add maximum number of mbuf segments

Allows application to query maximum number of mbuf segments that can
be chained together.

Signed-off-by: Gerry Gribbon <ggribbon@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>

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common/mlx5: fix post doorbell barrier

The rdma-core library can map doorbell register in two ways, depending
on the environment variable "MLX5_SHUT_UP_BF":

- as regular cached memory, the variab

common/mlx5: fix post doorbell barrier

The rdma-core library can map doorbell register in two ways, depending
on the environment variable "MLX5_SHUT_UP_BF":

- as regular cached memory, the variable is either missing or set to
zero. This type of mapping may cause the significant doorbell
register writing latency and requires an explicit memory write
barrier to mitigate this issue and prevent write combining.

- as non-cached memory, the variable is present and set to not "0"
value. This type of mapping may cause performance impact under
heavy loading conditions but the explicit write memory barrier is
not required and it may improve core performance.

The UAR creation function maps a doorbell in one of the above ways
according to the system. In run time, it always adds an explicit memory
barrier after writing to.
In cases where the doorbell was mapped as non-cached memory, the
explicit memory barrier is unnecessary and may impair performance.

The commit [1] solved this problem for a Tx queue. In run time, it
checks the mapping type and provides the memory barrier after writing to
a Tx doorbell register if it is needed. The mapping type is extracted
directly from the uar_mmap_offset field in the queue properties.

This patch shares this code between the drivers and extends the above
solution for each of them.

[1] commit 8409a28573d3
("net/mlx5: control transmit doorbell register mapping")

Fixes: f8c97babc9f4 ("compress/mlx5: add data-path functions")
Fixes: 8e196c08ab53 ("crypto/mlx5: support enqueue/dequeue operations")
Fixes: 4d4e245ad637 ("regex/mlx5: support enqueue")
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Reviewed-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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regex/mlx5: remove engine start/stop commands

Remove the engine start/stop DevX commands,
as they have been deprecated and moved to FW.

Signed-off-by: Ady Agbarih <adypodoman@gmail.com>

regex/mlx5: move RXP to CrSpace

Add patch for programming the regex database through ROF file,
using the firmware instead of manually through the software.
No need to setup the DB anymore, the regex

regex/mlx5: move RXP to CrSpace

Add patch for programming the regex database through ROF file,
using the firmware instead of manually through the software.
No need to setup the DB anymore, the regex-daemon is responsible
for that always.
In the new flow the regex driver only has to program ROF rules
by using set params DevX cmd, requires ROF mkey creation.
The rules file has to be read into 4KB aligned memory.

Signed-off-by: Ady Agbarih <adypodoman@gmail.com>
Acked-by: Ori Kam <orika@nvidia.com>

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regex/mlx5: remove register read/write

Remove the set/query regexp register commands from DevX.
Remove functions that used these commands.
Remove manual rules programming.

Signed-off-by: Ady Agbari

regex/mlx5: remove register read/write

Remove the set/query regexp register commands from DevX.
Remove functions that used these commands.
Remove manual rules programming.

Signed-off-by: Ady Agbarih <adypodoman@gmail.com>
Acked-by: Ori Kam <orika@nvidia.com>

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common/mlx5: update regex DevX commands

This patch modifies the SET_REGEXP_PARAMS DevX command as follows:

Remove DB setup DevX command. The command is no longer needed
in DPDK, it will always be i

common/mlx5: update regex DevX commands

This patch modifies the SET_REGEXP_PARAMS DevX command as follows:

Remove DB setup DevX command. The command is no longer needed
in DPDK, it will always be invoked by the regex-daemon.

Add new DevX command, for programming ROF rules for a specific engine.
The command takes as an input an mkey of the ROF.
It also introduces a new field_select bit.

Signed-off-by: Ady Agbarih <adypodoman@gmail.com>
Acked-by: Ori Kam <orika@nvidia.com>

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regex/mlx5: add cleanup on stop

When stopping the device we should release all
data allocated.

After rte_regexdev_configure(), the QPs are pre-allocated,
and will be configured only in rte_regexdev

regex/mlx5: add cleanup on stop

When stopping the device we should release all
data allocated.

After rte_regexdev_configure(), the QPs are pre-allocated,
and will be configured only in rte_regexdev_queue_pair_setup().
That's why the QP jobs array initialization is checked
before attempting to destroy the QP.

Signed-off-by: Ori Kam <orika@nvidia.com>
Signed-off-by: Ady Agbarih <adypodoman@gmail.com>

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common/mlx5: share MR management

Add global shared MR cache as a field of common device structure.
Move MR management to use this global cache for all drivers.

Signed-off-by: Michael Baum <michaelb

common/mlx5: share MR management

Add global shared MR cache as a field of common device structure.
Move MR management to use this global cache for all drivers.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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common/mlx5: share HCA capabilities handle

Add HCA attributes structure as a field of device config structure.
It query in common probing, and updates the timestamp format fields.

Each driver use H

common/mlx5: share HCA capabilities handle

Add HCA attributes structure as a field of device config structure.
It query in common probing, and updates the timestamp format fields.

Each driver use HCA attributes from common device config structure,
instead of query it for itself.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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common/mlx5: share protection domain object

Create shared Protection Domain in common area and add it and its PDN as
fields of common device structure.

Use this Protection Domain in all drivers and

common/mlx5: share protection domain object

Create shared Protection Domain in common area and add it and its PDN as
fields of common device structure.

Use this Protection Domain in all drivers and remove the PD and PDN
fields from their private structure.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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common/mlx5: share device context object

Create shared context device in common area and add it as a field of
common device.
Use this context device in all drivers and remove the ctx field from
thei

common/mlx5: share device context object

Create shared context device in common area and add it as a field of
common device.
Use this context device in all drivers and remove the ctx field from
their private structure.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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regex/mlx5: refactor HW queue objects

The mlx5 PMD for regex class uses an MMO WQE operated by the GGA engine
in BF devices.
Currently, all the MMO WQEs are managed by the SQ object.
Starting from B

regex/mlx5: refactor HW queue objects

The mlx5 PMD for regex class uses an MMO WQE operated by the GGA engine
in BF devices.
Currently, all the MMO WQEs are managed by the SQ object.
Starting from BF3, the queue of the MMO WQEs should be connected to the
GGA engine using a new configuration, MMO, that will be supported only
in the QP object.
The FW introduced new capabilities to define whether the MMO
configuration should be configured for the GGA queue.
Replace all the GGA queue objects to QP, set MMO configuration according
to the new FW capabilities.

Signed-off-by: Raja Zidane <rzidane@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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regex/mlx5: fix memory region unregistration

The issue can cause illegal physical address access while a huge-page A
is released and huge-page B is allocated on the same virtual address.
The old MR

regex/mlx5: fix memory region unregistration

The issue can cause illegal physical address access while a huge-page A
is released and huge-page B is allocated on the same virtual address.
The old MR can be matched using the virtual address of huge-page B but
the HW will access the physical address of huge-page A which is no more
part of the DPDK process.

Register a driver callback for memory event in order to free out all the
MRs of memory that is going to be freed from the DPDK process.

Fixes: cda883bbb655 ("regex/mlx5: add dynamic memory registration to datapath")
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>

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regex/mlx5: migrate to bus-agnostic common interface

To support auxiliary bus, upgrades driver to use mlx5 common driver
structure.

Signed-off-by: Xueming Li <xuemingl@nvidia.com>
Acked-by: Viaches

regex/mlx5: migrate to bus-agnostic common interface

To support auxiliary bus, upgrades driver to use mlx5 common driver
structure.

Signed-off-by: Xueming Li <xuemingl@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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regex/mlx5: add data path scattered mbuf process

UMR (User-Mode Memory Registration) WQE can present data buffers
scattered within multiple mbufs with single indirect mkey. Take
advantage of the UMR

regex/mlx5: add data path scattered mbuf process

UMR (User-Mode Memory Registration) WQE can present data buffers
scattered within multiple mbufs with single indirect mkey. Take
advantage of the UMR WQE, scattered mbuf in one operation can be
presented to an indirect mkey. The RegEx which only accepts one
mkey can now process the whole scattered mbuf in one operation.

The maximum scattered mbuf can be supported in one UMR WQE is now
defined as 64. The mbufs from multiple operations can be combined
into one UMR WQE as well if there is enough space in the KLM array,
since the operations can address their own mbuf's content by the
mkey's address and length. However, one operation's scattered mbuf's
can't be placed in two different UMR WQE's KLM array, if the UMR
WQE's KLM does not has enough free space for one operation, the
extra UMR WQE will be engaged.

In case the UMR WQE's indirect mkey will be over wrapped by the SQ's
WQE move, the mkey's index used by the UMR WQE should be the index
of last the RegEX WQE in the operations. As one operation consumes
one WQE set, build the RegEx WQE by reverse helps address the mkey
more efficiently. Once the operations in one burst consumes multiple
mkeys, when the mkey KLM array is full, the reverse WQE set index
will always be the last of the new mkey's for the new UMR WQE.

In GGA mode, the SQ WQE's memory layout becomes UMR/NOP and RegEx
WQE by interleave. The UMR and RegEx WQE can be called as WQE set.
The SQ's pi and ci will also be increased as WQE set not as WQE.

For operations don't have scattered mbuf, uses the mbuf's mkey directly,
the WQE set combination is NOP + RegEx.
For operations have scattered mbuf but share the UMR WQE with others,
the WQE set combination is NOP + RegEx.
For operations complete the UMR WQE, the WQE set combination is UMR +
RegEx.

Signed-off-by: John Hurley <jhurley@nvidia.com>
Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>

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regex/mlx5: support timestamp format

This patch adds support for the timestamp format settings for
the receive and send queues. If the firmware version x.30.1000
or above is installed and the NIC ti

regex/mlx5: support timestamp format

This patch adds support for the timestamp format settings for
the receive and send queues. If the firmware version x.30.1000
or above is installed and the NIC timestamps are configured
with the real-time format, the default zero values for newly
added fields cause the queue creation to fail.

The patch queries the timestamp formats supported by the hardware
and sets the configuration values in queue context accordingly.

Fixes: 92f2c6a30fe0 ("regex/mlx5: add send queue")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>

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regex/mlx5: support combined rule file

The rof file holds programming instructions for
a given HW version.
In order to support future generation of HW it
was decided that the rof file will hold numb

regex/mlx5: support combined rule file

The rof file holds programming instructions for
a given HW version.
In order to support future generation of HW it
was decided that the rof file will hold number
of rule configurations, and the driver will use
the one that matches the HW version.

In current code we force sync after each write block.
This has impact on performance.

The solution is to move the sync to the end of the
entire programming sequence.

Signed-off-by: Ori Kam <orika@nvidia.com>

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regex/mlx5: move DevX SQ creation to common

Using common function for DevX SQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

regex/mlx5: move DevX CQ creation to common

Using common function for DevX CQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

regex/mlx5: add dynamic memory registration to datapath

Currently job data is being copied to pre-registered buffer.
To avoid memcpy on the datapath, use dynamic memory registration.

This change wi

regex/mlx5: add dynamic memory registration to datapath

Currently job data is being copied to pre-registered buffer.
To avoid memcpy on the datapath, use dynamic memory registration.

This change will reduce latency when sending regex jobs. The first few
jobs may have high latency due to registration, but assuming all
following mbufs will arrive from the same mempool/hugepage, there will
be no further memory registration.

Signed-off-by: Yuval Avnery <yuvalav@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>

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regex/mlx5: add teardown for fastpath buffers

Added missing code to free Input/Output buffers and memory
registration.
Also added calls to this code in case of error in the qp setup
procedure.
The r

regex/mlx5: add teardown for fastpath buffers

Added missing code to free Input/Output buffers and memory
registration.
Also added calls to this code in case of error in the qp setup
procedure.
The rollback code itself did not handle rollback properly
and did not check return value from the fastpath setup.

Signed-off-by: Yuval Avnery <yuvalav@mellanox.com>
Acked-by: Ori Kam <orika@mellanox.com>

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regex/mlx5: add empty start/stop/close

Add the start, stop and close functions.
In current implementation they are empty functions
and are only exists in order that when called
from rte level, the f

regex/mlx5: add empty start/stop/close

Add the start, stop and close functions.
In current implementation they are empty functions
and are only exists in order that when called
from rte level, the function will return with success code.

Signed-off-by: Ori Kam <orika@mellanox.com>

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regex/mlx5: support dequeue

Implement dequeue function for the regex API.

Signed-off-by: Yuval Avnery <yuvalav@mellanox.com>
Acked-by: Ori Kam <orika@mellanox.com>