1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2020 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef MLX5_REGEX_H 6 #define MLX5_REGEX_H 7 8 #include <rte_regexdev.h> 9 10 #include <infiniband/verbs.h> 11 #include <infiniband/mlx5dv.h> 12 13 #include <mlx5_common.h> 14 #include <mlx5_common_mr.h> 15 #include <mlx5_common_devx.h> 16 17 #include "mlx5_rxp.h" 18 19 struct mlx5_regex_sq { 20 uint16_t log_nb_desc; /* Log 2 number of desc for this object. */ 21 struct mlx5_devx_sq sq_obj; /* The SQ DevX object. */ 22 size_t pi, db_pi; 23 size_t ci; 24 uint32_t sqn; 25 }; 26 27 struct mlx5_regex_cq { 28 uint32_t log_nb_desc; /* Log 2 number of desc for this object. */ 29 struct mlx5_devx_cq cq_obj; /* The CQ DevX object. */ 30 size_t ci; 31 }; 32 33 struct mlx5_regex_qp { 34 uint32_t flags; /* QP user flags. */ 35 uint32_t nb_desc; /* Total number of desc for this qp. */ 36 struct mlx5_regex_sq *sqs; /* Pointer to sq array. */ 37 uint16_t nb_obj; /* Number of sq objects. */ 38 struct mlx5_regex_cq cq; /* CQ struct. */ 39 uint32_t free_sqs; 40 struct mlx5_regex_job *jobs; 41 struct ibv_mr *metadata; 42 struct ibv_mr *outputs; 43 size_t ci, pi; 44 struct mlx5_mr_ctrl mr_ctrl; 45 }; 46 47 struct mlx5_regex_db { 48 void *ptr; /* Pointer to the db memory. */ 49 uint32_t len; /* The memory len. */ 50 bool active; /* Active flag. */ 51 uint8_t db_assigned_to_eng_num; 52 /**< To which engine the db is connected. */ 53 struct mlx5_regex_umem umem; 54 /**< The umem struct. */ 55 }; 56 57 struct mlx5_regex_priv { 58 TAILQ_ENTRY(mlx5_regex_priv) next; 59 struct ibv_context *ctx; /* Device context. */ 60 struct rte_pci_device *pci_dev; 61 struct rte_regexdev *regexdev; /* Pointer to the RegEx dev. */ 62 uint16_t nb_queues; /* Number of queues. */ 63 struct mlx5_regex_qp *qps; /* Pointer to the qp array. */ 64 uint16_t nb_max_matches; /* Max number of matches. */ 65 enum mlx5_rxp_program_mode prog_mode; 66 struct mlx5_regex_db db[MLX5_RXP_MAX_ENGINES + 67 MLX5_RXP_EM_COUNT]; 68 uint32_t nb_engines; /* Number of RegEx engines. */ 69 struct mlx5dv_devx_uar *uar; /* UAR object. */ 70 struct ibv_pd *pd; 71 struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ 72 }; 73 74 /* mlx5_regex.c */ 75 int mlx5_regex_start(struct rte_regexdev *dev); 76 int mlx5_regex_stop(struct rte_regexdev *dev); 77 int mlx5_regex_close(struct rte_regexdev *dev); 78 79 /* mlx5_rxp.c */ 80 int mlx5_regex_info_get(struct rte_regexdev *dev, 81 struct rte_regexdev_info *info); 82 int mlx5_regex_configure(struct rte_regexdev *dev, 83 const struct rte_regexdev_config *cfg); 84 int mlx5_regex_rules_db_import(struct rte_regexdev *dev, 85 const char *rule_db, uint32_t rule_db_len); 86 87 /* mlx5_regex_devx.c */ 88 int mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id, 89 uint32_t addr, uint32_t data); 90 int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id, 91 uint32_t addr, uint32_t *data); 92 int mlx5_devx_regex_database_stop(void *ctx, uint8_t engine); 93 int mlx5_devx_regex_database_resume(void *ctx, uint8_t engine); 94 int mlx5_devx_regex_database_program(void *ctx, uint8_t engine, 95 uint32_t umem_id, uint64_t umem_offset); 96 97 /* mlx5_regex_control.c */ 98 int mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind, 99 const struct rte_regexdev_qp_conf *cfg); 100 101 /* mlx5_regex_fastpath.c */ 102 int mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id); 103 void mlx5_regexdev_teardown_fastpath(struct mlx5_regex_priv *priv, 104 uint32_t qp_id); 105 uint16_t mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id, 106 struct rte_regex_ops **ops, uint16_t nb_ops); 107 uint16_t mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id, 108 struct rte_regex_ops **ops, uint16_t nb_ops); 109 110 #endif /* MLX5_REGEX_H */ 111