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/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dllvm.get.fpmode.ll15 ; GFX678-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 0, 19)
16 ; GFX678-NEXT: s_and_b32 s4, 0x7f3ff, s4
17 ; GFX678-NEXT: v_mov_b32_e32 v0, s4
23 ; GFX9-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 0, 24)
24 ; GFX9-NEXT: s_and_b32 s4, 0x87f3ff, s4
25 ; GFX9-NEXT: v_mov_b32_e32 v0, s4
31 ; GFX10-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 0, 24)
32 ; GFX10-NEXT: s_and_b32 s4,
[all...]
H A Dllvm.get.rounding.ll15 ; GFX678-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 0, 4)
16 ; GFX678-NEXT: s_lshl_b32 s6, s4, 2
17 ; GFX678-NEXT: s_mov_b32 s4, 0xeb24da71
20 ; GFX678-NEXT: s_and_b32 s4, s4, 15
21 ; GFX678-NEXT: s_add_i32 s5, s4, 4
22 ; GFX678-NEXT: s_cmp_lt_u32 s4, 4
23 ; GFX678-NEXT: s_cselect_b32 s4, s4, s5
24 ; GFX678-NEXT: v_mov_b32_e32 v0, s4
[all...]
H A Dllvm.amdgcn.readlane.ptr.ll8 ; CHECK-SDAG-NEXT: v_readfirstlane_b32 s4, v4
10 ; CHECK-SDAG-NEXT: v_readlane_b32 s5, v3, s4
11 ; CHECK-SDAG-NEXT: v_readlane_b32 s4, v2, s4
25 ; CHECK-SDAG-NEXT: v_readfirstlane_b32 s4, v8
27 ; CHECK-SDAG-NEXT: v_readlane_b32 s9, v7, s4
28 ; CHECK-SDAG-NEXT: v_readlane_b32 s8, v6, s4
29 ; CHECK-SDAG-NEXT: v_readlane_b32 s7, v5, s4
30 ; CHECK-SDAG-NEXT: v_readlane_b32 s6, v4, s4
31 ; CHECK-SDAG-NEXT: v_readlane_b32 s5, v3, s4
32 ; CHECK-SDAG-NEXT: v_readlane_b32 s4, v2, s4
[all …]
H A Dllvm.is.fpclass.bf16.ll22 ; GFX7CHECK-NEXT: s_and_b32 s4, s6, 0x7fff
23 ; GFX7CHECK-NEXT: s_cmpk_gt_i32 s4, 0x7f80
164 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7fc0
165 ; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
166 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
167 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e64 s[4:5], s4, v0
176 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7fc0
177 ; GFX8CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
178 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
179 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e64 s[4:5], s4, v
[all...]
H A Dfpenv.ll21 ; GFX6-SDAG-NEXT: s_getreg_b32 s4, hwreg(HW_REG_TRAPSTS, 0, 5)
24 ; GFX6-SDAG-NEXT: v_mov_b32_e32 v1, s4
30 ; GFX6-ISEL-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 0, 23)
32 ; GFX6-ISEL-NEXT: v_mov_b32_e32 v0, s4
39 ; GFX8-SDAG-NEXT: s_getreg_b32 s4, hwreg(HW_REG_TRAPSTS, 0, 5)
42 ; GFX8-SDAG-NEXT: v_mov_b32_e32 v1, s4
48 ; GFX8-ISEL-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 0, 23)
50 ; GFX8-ISEL-NEXT: v_mov_b32_e32 v0, s4
57 ; GFX9-SDAG-NEXT: s_getreg_b32 s4, hwreg(HW_REG_TRAPSTS, 0, 5)
60 ; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s4
[all …]
H A Dfp_trunc_store_fp32_to_bf16.ll11 ; CHECK-NEXT: s_movk_i32 s4, 0x7fff
12 ; CHECK-NEXT: v_add3_u32 v1, v1, v0, s4
30 ; CHECK-NEXT: s_movk_i32 s4, 0x7fff
31 ; CHECK-NEXT: v_add3_u32 v4, v4, v0, s4
36 ; CHECK-NEXT: v_add3_u32 v4, v4, v1, s4
40 ; CHECK-NEXT: s_mov_b32 s4, 0x7060302
41 ; CHECK-NEXT: v_perm_b32 v0, v1, v0, s4
58 ; CHECK-NEXT: s_movk_i32 s4, 0x7fff
59 ; CHECK-NEXT: v_add3_u32 v3, v3, v0, s4
64 ; CHECK-NEXT: v_add3_u32 v3, v3, v1, s4
[all …]
H A Datomic_optimizations_raw_buffer.ll41 ; GFX6-NEXT: v_readfirstlane_b32 s4, v1
42 ; GFX6-NEXT: v_mad_u32_u24 v0, v0, 5, s4
309 ; GFX6-NEXT: v_readfirstlane_b32 s4, v1
312 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v0
426 ; GFX10W32-NEXT: v_readfirstlane_b32 s4, v1
486 ; GFX11W32-NEXT: v_readfirstlane_b32 s4, v1
551 ; GFX12W32-NEXT: v_readfirstlane_b32 s4, v1
601 ; GFX6-NEXT: v_readfirstlane_b32 s4, v0
603 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v1
1088 ; GFX6-NEXT: v_readfirstlane_b32 s4, v
[all...]
H A Datomic_optimizations_buffer.ll42 ; GFX6-NEXT: v_readfirstlane_b32 s4, v1
43 ; GFX6-NEXT: v_mad_u32_u24 v0, v0, 5, s4
310 ; GFX6-NEXT: v_readfirstlane_b32 s4, v1
313 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v0
427 ; GFX10W32-NEXT: v_readfirstlane_b32 s4, v1
487 ; GFX11W32-NEXT: v_readfirstlane_b32 s4, v1
552 ; GFX12W32-NEXT: v_readfirstlane_b32 s4, v1
602 ; GFX6-NEXT: v_readfirstlane_b32 s4, v0
604 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v1
994 ; GFX6-NEXT: v_readfirstlane_b32 s4, v
[all...]
/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Ddynamic-alloca-uniform.ll15 ; GFX9-NEXT: s_mov_b32 s4, s32
20 ; GFX9-NEXT: v_mov_b32_e32 v1, s4
23 ; GFX9-NEXT: s_add_u32 s32, s4, s5
32 ; GFX10-NEXT: s_mov_b32 s4, s32
35 ; GFX10-NEXT: v_mov_b32_e32 v1, s4
42 ; GFX10-NEXT: s_add_u32 s32, s4, s5
74 ; GFX9-NEXT: s_add_u32 s4, s4, gv@gotpcrel32@lo+4
82 ; GFX9-NEXT: s_load_dword s4, s[4:5], 0x0
84 ; GFX9-NEXT: s_lshl2_add_u32 s4, s
[all...]
H A Dllvm.amdgcn.image.atomic.dim.ll15 ; GFX6-NEXT: s_mov_b32 s2, s4
17 ; GFX6-NEXT: s_mov_b32 s4, s6
29 ; GFX8-NEXT: s_mov_b32 s2, s4
31 ; GFX8-NEXT: s_mov_b32 s4, s6
43 ; GFX900-NEXT: s_mov_b32 s2, s4
45 ; GFX900-NEXT: s_mov_b32 s4, s6
57 ; GFX90A-NEXT: s_mov_b32 s2, s4
59 ; GFX90A-NEXT: s_mov_b32 s4, s6
72 ; GFX10PLUS-NEXT: s_mov_b32 s2, s4
74 ; GFX10PLUS-NEXT: s_mov_b32 s4, s6
[all …]
H A Dllvm.amdgcn.image.store.2d.ll13 ; GFX6-NEXT: s_mov_b32 s2, s4
15 ; GFX6-NEXT: s_mov_b32 s4, s6
26 ; GFX8-NEXT: s_mov_b32 s2, s4
28 ; GFX8-NEXT: s_mov_b32 s4, s6
39 ; GFX10-NEXT: s_mov_b32 s2, s4
41 ; GFX10-NEXT: s_mov_b32 s4, s6
52 ; GFX11-NEXT: s_mov_b32 s2, s4
54 ; GFX11-NEXT: s_mov_b32 s4, s6
65 ; GFX12-NEXT: s_mov_b32 s2, s4
67 ; GFX12-NEXT: s_mov_b32 s4, s
[all...]
H A Dllvm.amdgcn.image.load.1d.ll14 ; GFX68-NEXT: s_mov_b32 s2, s4
16 ; GFX68-NEXT: s_mov_b32 s4, s6
28 ; GFX10-NEXT: s_mov_b32 s2, s4
30 ; GFX10-NEXT: s_mov_b32 s4, s6
42 ; NOPRT-NEXT: s_mov_b32 s2, s4
44 ; NOPRT-NEXT: s_mov_b32 s4, s6
56 ; GFX12-NEXT: s_mov_b32 s2, s4
58 ; GFX12-NEXT: s_mov_b32 s4, s6
74 ; GFX68-NEXT: s_mov_b32 s2, s4
76 ; GFX68-NEXT: s_mov_b32 s4, s6
[all …]
H A Dllvm.amdgcn.image.load.1d.d16.ll14 ; GFX8-UNPACKED-NEXT: s_mov_b32 s2, s4
16 ; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s6
28 ; GFX8-PACKED-NEXT: s_mov_b32 s2, s4
30 ; GFX8-PACKED-NEXT: s_mov_b32 s4, s6
42 ; GFX9-NEXT: s_mov_b32 s2, s4
44 ; GFX9-NEXT: s_mov_b32 s4, s6
56 ; GFX10PLUS-NEXT: s_mov_b32 s2, s4
58 ; GFX10PLUS-NEXT: s_mov_b32 s4, s6
70 ; GFX12-NEXT: s_mov_b32 s2, s4
72 ; GFX12-NEXT: s_mov_b32 s4, s6
[all …]
H A Dllvm.amdgcn.image.getresinfo.ll13 ; GFX6-NEXT: s_mov_b32 s2, s4
15 ; GFX6-NEXT: s_mov_b32 s4, s6
27 ; GFX8-NEXT: s_mov_b32 s2, s4
29 ; GFX8-NEXT: s_mov_b32 s4, s6
41 ; GFX10-NEXT: s_mov_b32 s2, s4
43 ; GFX10-NEXT: s_mov_b32 s4, s6
55 ; GFX12-NEXT: s_mov_b32 s2, s4
57 ; GFX12-NEXT: s_mov_b32 s4, s6
74 ; GFX6-NEXT: s_mov_b32 s2, s4
76 ; GFX6-NEXT: s_mov_b32 s4, s6
[all …]
/llvm-project/llvm/test/CodeGen/Thumb2/
H A Dmve-frint.ll26 ; CHECK-MVE-NEXT: vmovx.f16 s4, s0
28 ; CHECK-MVE-NEXT: vrintp.f16 s4, s4
29 ; CHECK-MVE-NEXT: vins.f16 s0, s4
30 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
31 ; CHECK-MVE-NEXT: vrintp.f16 s4, s4
33 ; CHECK-MVE-NEXT: vins.f16 s1, s4
34 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
35 ; CHECK-MVE-NEXT: vrintp.f16 s4, s4
37 ; CHECK-MVE-NEXT: vins.f16 s2, s4
38 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
[all …]
H A Dmve-vcmpfz.ll27 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
67 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
104 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
140 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
176 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
212 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
252 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
281 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
317 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
353 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
[all...]
H A Dmve-vcmpf.ll8 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
44 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
85 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
121 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
157 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
193 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
229 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
278 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
298 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
334 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
[all...]
H A Dmve-fp-negabs.ll8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s0
10 ; CHECK-MVE-NEXT: vneg.f16 s4, s4
11 ; CHECK-MVE-NEXT: vins.f16 s0, s4
12 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
13 ; CHECK-MVE-NEXT: vneg.f16 s4, s4
15 ; CHECK-MVE-NEXT: vins.f16 s1, s4
16 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
17 ; CHECK-MVE-NEXT: vneg.f16 s4, s4
19 ; CHECK-MVE-NEXT: vins.f16 s2, s4
20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
[all …]
H A Dmve-vecreduce-fminmax.ll47 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s4
63 ; CHECK-FP-NEXT: vmovx.f16 s4, s0
65 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s4
94 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s0
95 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
96 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s1
98 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
125 ; CHECK-NOFP-NEXT: vmovx.f16 s8, s4
126 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
129 ; CHECK-NOFP-NEXT: vminnm.f16 s4, s
[all...]
/llvm-project/llvm/test/CodeGen/ARM/
H A Dfp16-fusedMAC.ll12 ; CHECK-NEXT: vldr.16 s4, [r2]
13 ; CHECK-NEXT: vfma.f16 s4, s2, s0
14 ; CHECK-NEXT: vstr.16 s4, [r0]
41 ; CHECK-NEXT: vldr.16 s4, [r0]
42 ; CHECK-NEXT: vfms.f16 s4, s2, s0
43 ; CHECK-NEXT: vstr.16 s4, [r0]
70 ; CHECK-NEXT: vldr.16 s4, [r2]
71 ; CHECK-NEXT: vfnma.f16 s4, s2, s0
72 ; CHECK-NEXT: vstr.16 s4, [r0]
100 ; CHECK-NEXT: vldr.16 s4, [r2]
[all …]
/llvm-project/mlir/include/mlir/Dialect/Linalg/IR/
H A DLinalgNamedStructuredOps.yaml1339 shape_map: affine_map<()[s0, s1, s2, s3, s4, s5] -> (s0, s1, s2, s3)>
1344 shape_map: affine_map<()[s0, s1, s2, s3, s4, s5] -> (s4, s1, s5, s3)>
1349 shape_map: affine_map<()[s0, s1, s2, s3, s4, s5] -> (s0, s4, s2, s5)>
1352 - affine_map<(d0, d1, d2, d3, d4, d5)[s0, s1, s2, s3, s4, s5] -> (d0, d2, d3,
1354 - affine_map<(d0, d1, d2, d3, d4, d5)[s0, s1, s2, s3, s4, s5] -> (d1, d2, d4,
1356 - affine_map<(d0, d1, d2, d3, d4, d5)[s0, s1, s2, s3, s4, s5] -> (d0, d1, d3,
1416 shape_map: affine_map<()[s0, s1, s2, s3, s4, s5, s6] -> (s0, s1, s2, s3, s4)>
[all...]
/llvm-project/llvm/test/MC/AMDGPU/
H A Dsmrd.s54 s_load_dword s1, s[2:3], s4
55 // GCN: s_load_dword s1, s[2:3], s4 ; encoding: [0x04,0x82,0x00,0xc0]
56 // VI: s_load_dword s1, s[2:3], s4 ; encoding: [0x41,0x00,0x00,0xc0,0x04,0x00,0x00,0x00]
58 s_load_dword tba_lo, s[2:3], s4
59 // GCN: s_load_dword tba_lo, s[2:3], s4 ; encoding: [0x04,0x02,0x36,0xc0]
60 // VI: s_load_dword tba_lo, s[2:3], s4 ; encoding: [0x01,0x1b,0x00,0xc0,0x04,0x00,0x00,0x00]
62 s_load_dword tba_hi, s[2:3], s4
63 // GCN: s_load_dword tba_hi, s[2:3], s4 ; encoding: [0x04,0x82,0x36,0xc0]
64 // VI: s_load_dword tba_hi, s[2:3], s4 ; encoding: [0x41,0x1b,0x00,0xc0,0x04,0x00,0x00,0x00]
66 s_load_dword tma_lo, s[2:3], s4
[all...]
/llvm-project/clang/test/SemaCXX/
H A Delaborated-type-specifier.cpp22 void test_elab2(struct S4 *s4); // expected-note{{'NS::S4' declared here}}
25 void X::test_elab2(S4 *s4) { } // expected-note{{passing argument to parameter 's4' here}} in test_elab2() argument
29 …struct S4 *s4 = 0; // expected-note{{'S4' is not defined, but forward declared here; conversion wo… in test_X_elab() local
30 …x.test_elab2(s4); // expected-error{{cannot initialize a parameter of type 'S4 *' (aka 'NS::S4 *')… in test_X_elab()
34 S4 *get_S4();
38 S4 *s4; // expected-error{{unknown type name 'S4'; did you mean 'NS::S4'?}} in test_S5_scope() local
/llvm-project/llvm/test/CodeGen/AArch64/
H A Dstorepairsuppress.ll40 ; SUPPRESS-NEXT: ldp s4, s5, [x8, #8]
42 ; SUPPRESS-NEXT: fmul s1, s4, s1
43 ; SUPPRESS-NEXT: fnmsub s4, s4, s0, s6
45 ; SUPPRESS-NEXT: fadd s1, s4, s2
48 ; SUPPRESS-NEXT: fsub s2, s2, s4
52 ; SUPPRESS-NEXT: ldp s3, s4, [x9]
55 ; SUPPRESS-NEXT: fmul s18, s17, s4
56 ; SUPPRESS-NEXT: fmul s4, s16, s4
58 ; SUPPRESS-NEXT: fmadd s3, s17, s3, s4
59 ; SUPPRESS-NEXT: fadd s4, s16, s6
[all …]
/llvm-project/llvm/test/CodeGen/VE/Scalar/
H A Datomicrmw-uinc-udec-wrap.ll13 ; CHECK-NEXT: ldl.sx %s4, (, %s1)
19 ; CHECK-NEXT: or %s5, 0, %s4
20 ; CHECK-NEXT: and %s4, %s5, (32)0
21 ; CHECK-NEXT: srl %s4, %s4, %s0
22 ; CHECK-NEXT: and %s6, %s4, (56)0
23 ; CHECK-NEXT: adds.w.sx %s4, 1, %s4
25 ; CHECK-NEXT: cmov.w.ge %s4, (0)1, %s6
26 ; CHECK-NEXT: and %s4, %s4, (56)0
27 ; CHECK-NEXT: sla.w.sx %s4, %s4, %s0
29 ; CHECK-NEXT: or %s4, %s6, %s4
[all …]

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