xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-frint.ll (revision 52e0cf9d61618353d2745a51a16ae408edf0f49b) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
4
5define arm_aapcs_vfpcc <4 x float> @fceil_float32_t(<4 x float> %src) {
6; CHECK-MVE-LABEL: fceil_float32_t:
7; CHECK-MVE:       @ %bb.0: @ %entry
8; CHECK-MVE-NEXT:    vrintp.f32 s3, s3
9; CHECK-MVE-NEXT:    vrintp.f32 s2, s2
10; CHECK-MVE-NEXT:    vrintp.f32 s1, s1
11; CHECK-MVE-NEXT:    vrintp.f32 s0, s0
12; CHECK-MVE-NEXT:    bx lr
13;
14; CHECK-MVEFP-LABEL: fceil_float32_t:
15; CHECK-MVEFP:       @ %bb.0: @ %entry
16; CHECK-MVEFP-NEXT:    vrintp.f32 q0, q0
17; CHECK-MVEFP-NEXT:    bx lr
18entry:
19  %0 = call fast <4 x float> @llvm.ceil.v4f32(<4 x float> %src)
20  ret <4 x float> %0
21}
22
23define arm_aapcs_vfpcc <8 x half> @fceil_float16_t(<8 x half> %src) {
24; CHECK-MVE-LABEL: fceil_float16_t:
25; CHECK-MVE:       @ %bb.0: @ %entry
26; CHECK-MVE-NEXT:    vmovx.f16 s4, s0
27; CHECK-MVE-NEXT:    vrintp.f16 s0, s0
28; CHECK-MVE-NEXT:    vrintp.f16 s4, s4
29; CHECK-MVE-NEXT:    vins.f16 s0, s4
30; CHECK-MVE-NEXT:    vmovx.f16 s4, s1
31; CHECK-MVE-NEXT:    vrintp.f16 s4, s4
32; CHECK-MVE-NEXT:    vrintp.f16 s1, s1
33; CHECK-MVE-NEXT:    vins.f16 s1, s4
34; CHECK-MVE-NEXT:    vmovx.f16 s4, s2
35; CHECK-MVE-NEXT:    vrintp.f16 s4, s4
36; CHECK-MVE-NEXT:    vrintp.f16 s2, s2
37; CHECK-MVE-NEXT:    vins.f16 s2, s4
38; CHECK-MVE-NEXT:    vmovx.f16 s4, s3
39; CHECK-MVE-NEXT:    vrintp.f16 s4, s4
40; CHECK-MVE-NEXT:    vrintp.f16 s3, s3
41; CHECK-MVE-NEXT:    vins.f16 s3, s4
42; CHECK-MVE-NEXT:    bx lr
43;
44; CHECK-MVEFP-LABEL: fceil_float16_t:
45; CHECK-MVEFP:       @ %bb.0: @ %entry
46; CHECK-MVEFP-NEXT:    vrintp.f16 q0, q0
47; CHECK-MVEFP-NEXT:    bx lr
48entry:
49  %0 = call fast <8 x half> @llvm.ceil.v8f16(<8 x half> %src)
50  ret <8 x half> %0
51}
52
53define arm_aapcs_vfpcc <2 x double> @fceil_float64_t(<2 x double> %src) {
54; CHECK-LABEL: fceil_float64_t:
55; CHECK:       @ %bb.0: @ %entry
56; CHECK-NEXT:    .save {r7, lr}
57; CHECK-NEXT:    push {r7, lr}
58; CHECK-NEXT:    .vsave {d8, d9}
59; CHECK-NEXT:    vpush {d8, d9}
60; CHECK-NEXT:    vmov q4, q0
61; CHECK-NEXT:    vmov r0, r1, d9
62; CHECK-NEXT:    bl ceil
63; CHECK-NEXT:    vmov r2, r3, d8
64; CHECK-NEXT:    vmov d9, r0, r1
65; CHECK-NEXT:    mov r0, r2
66; CHECK-NEXT:    mov r1, r3
67; CHECK-NEXT:    bl ceil
68; CHECK-NEXT:    vmov d8, r0, r1
69; CHECK-NEXT:    vmov q0, q4
70; CHECK-NEXT:    vpop {d8, d9}
71; CHECK-NEXT:    pop {r7, pc}
72entry:
73  %0 = call fast <2 x double> @llvm.ceil.v2f64(<2 x double> %src)
74  ret <2 x double> %0
75}
76
77define arm_aapcs_vfpcc <4 x float> @ftrunc_float32_t(<4 x float> %src) {
78; CHECK-MVE-LABEL: ftrunc_float32_t:
79; CHECK-MVE:       @ %bb.0: @ %entry
80; CHECK-MVE-NEXT:    vrintz.f32 s3, s3
81; CHECK-MVE-NEXT:    vrintz.f32 s2, s2
82; CHECK-MVE-NEXT:    vrintz.f32 s1, s1
83; CHECK-MVE-NEXT:    vrintz.f32 s0, s0
84; CHECK-MVE-NEXT:    bx lr
85;
86; CHECK-MVEFP-LABEL: ftrunc_float32_t:
87; CHECK-MVEFP:       @ %bb.0: @ %entry
88; CHECK-MVEFP-NEXT:    vrintz.f32 q0, q0
89; CHECK-MVEFP-NEXT:    bx lr
90entry:
91  %0 = call fast <4 x float> @llvm.trunc.v4f32(<4 x float> %src)
92  ret <4 x float> %0
93}
94
95define arm_aapcs_vfpcc <8 x half> @ftrunc_float16_t(<8 x half> %src) {
96; CHECK-MVE-LABEL: ftrunc_float16_t:
97; CHECK-MVE:       @ %bb.0: @ %entry
98; CHECK-MVE-NEXT:    vmovx.f16 s4, s0
99; CHECK-MVE-NEXT:    vrintz.f16 s0, s0
100; CHECK-MVE-NEXT:    vrintz.f16 s4, s4
101; CHECK-MVE-NEXT:    vins.f16 s0, s4
102; CHECK-MVE-NEXT:    vmovx.f16 s4, s1
103; CHECK-MVE-NEXT:    vrintz.f16 s4, s4
104; CHECK-MVE-NEXT:    vrintz.f16 s1, s1
105; CHECK-MVE-NEXT:    vins.f16 s1, s4
106; CHECK-MVE-NEXT:    vmovx.f16 s4, s2
107; CHECK-MVE-NEXT:    vrintz.f16 s4, s4
108; CHECK-MVE-NEXT:    vrintz.f16 s2, s2
109; CHECK-MVE-NEXT:    vins.f16 s2, s4
110; CHECK-MVE-NEXT:    vmovx.f16 s4, s3
111; CHECK-MVE-NEXT:    vrintz.f16 s4, s4
112; CHECK-MVE-NEXT:    vrintz.f16 s3, s3
113; CHECK-MVE-NEXT:    vins.f16 s3, s4
114; CHECK-MVE-NEXT:    bx lr
115;
116; CHECK-MVEFP-LABEL: ftrunc_float16_t:
117; CHECK-MVEFP:       @ %bb.0: @ %entry
118; CHECK-MVEFP-NEXT:    vrintz.f16 q0, q0
119; CHECK-MVEFP-NEXT:    bx lr
120entry:
121  %0 = call fast <8 x half> @llvm.trunc.v8f16(<8 x half> %src)
122  ret <8 x half> %0
123}
124
125define arm_aapcs_vfpcc <2 x double> @ftrunc_float64_t(<2 x double> %src) {
126; CHECK-LABEL: ftrunc_float64_t:
127; CHECK:       @ %bb.0: @ %entry
128; CHECK-NEXT:    .save {r7, lr}
129; CHECK-NEXT:    push {r7, lr}
130; CHECK-NEXT:    .vsave {d8, d9}
131; CHECK-NEXT:    vpush {d8, d9}
132; CHECK-NEXT:    vmov q4, q0
133; CHECK-NEXT:    vmov r0, r1, d9
134; CHECK-NEXT:    bl trunc
135; CHECK-NEXT:    vmov r2, r3, d8
136; CHECK-NEXT:    vmov d9, r0, r1
137; CHECK-NEXT:    mov r0, r2
138; CHECK-NEXT:    mov r1, r3
139; CHECK-NEXT:    bl trunc
140; CHECK-NEXT:    vmov d8, r0, r1
141; CHECK-NEXT:    vmov q0, q4
142; CHECK-NEXT:    vpop {d8, d9}
143; CHECK-NEXT:    pop {r7, pc}
144entry:
145  %0 = call fast <2 x double> @llvm.trunc.v2f64(<2 x double> %src)
146  ret <2 x double> %0
147}
148
149define arm_aapcs_vfpcc <4 x float> @frint_float32_t(<4 x float> %src) {
150; CHECK-MVE-LABEL: frint_float32_t:
151; CHECK-MVE:       @ %bb.0: @ %entry
152; CHECK-MVE-NEXT:    vrintx.f32 s3, s3
153; CHECK-MVE-NEXT:    vrintx.f32 s2, s2
154; CHECK-MVE-NEXT:    vrintx.f32 s1, s1
155; CHECK-MVE-NEXT:    vrintx.f32 s0, s0
156; CHECK-MVE-NEXT:    bx lr
157;
158; CHECK-MVEFP-LABEL: frint_float32_t:
159; CHECK-MVEFP:       @ %bb.0: @ %entry
160; CHECK-MVEFP-NEXT:    vrintx.f32 q0, q0
161; CHECK-MVEFP-NEXT:    bx lr
162entry:
163  %0 = call fast <4 x float> @llvm.rint.v4f32(<4 x float> %src)
164  ret <4 x float> %0
165}
166
167define arm_aapcs_vfpcc <8 x half> @frint_float16_t(<8 x half> %src) {
168; CHECK-MVE-LABEL: frint_float16_t:
169; CHECK-MVE:       @ %bb.0: @ %entry
170; CHECK-MVE-NEXT:    vmovx.f16 s4, s0
171; CHECK-MVE-NEXT:    vrintx.f16 s0, s0
172; CHECK-MVE-NEXT:    vrintx.f16 s4, s4
173; CHECK-MVE-NEXT:    vins.f16 s0, s4
174; CHECK-MVE-NEXT:    vmovx.f16 s4, s1
175; CHECK-MVE-NEXT:    vrintx.f16 s4, s4
176; CHECK-MVE-NEXT:    vrintx.f16 s1, s1
177; CHECK-MVE-NEXT:    vins.f16 s1, s4
178; CHECK-MVE-NEXT:    vmovx.f16 s4, s2
179; CHECK-MVE-NEXT:    vrintx.f16 s4, s4
180; CHECK-MVE-NEXT:    vrintx.f16 s2, s2
181; CHECK-MVE-NEXT:    vins.f16 s2, s4
182; CHECK-MVE-NEXT:    vmovx.f16 s4, s3
183; CHECK-MVE-NEXT:    vrintx.f16 s4, s4
184; CHECK-MVE-NEXT:    vrintx.f16 s3, s3
185; CHECK-MVE-NEXT:    vins.f16 s3, s4
186; CHECK-MVE-NEXT:    bx lr
187;
188; CHECK-MVEFP-LABEL: frint_float16_t:
189; CHECK-MVEFP:       @ %bb.0: @ %entry
190; CHECK-MVEFP-NEXT:    vrintx.f16 q0, q0
191; CHECK-MVEFP-NEXT:    bx lr
192entry:
193  %0 = call fast <8 x half> @llvm.rint.v8f16(<8 x half> %src)
194  ret <8 x half> %0
195}
196
197define arm_aapcs_vfpcc <2 x double> @frint_float64_t(<2 x double> %src) {
198; CHECK-LABEL: frint_float64_t:
199; CHECK:       @ %bb.0: @ %entry
200; CHECK-NEXT:    .save {r7, lr}
201; CHECK-NEXT:    push {r7, lr}
202; CHECK-NEXT:    .vsave {d8, d9}
203; CHECK-NEXT:    vpush {d8, d9}
204; CHECK-NEXT:    vmov q4, q0
205; CHECK-NEXT:    vmov r0, r1, d9
206; CHECK-NEXT:    bl rint
207; CHECK-NEXT:    vmov r2, r3, d8
208; CHECK-NEXT:    vmov d9, r0, r1
209; CHECK-NEXT:    mov r0, r2
210; CHECK-NEXT:    mov r1, r3
211; CHECK-NEXT:    bl rint
212; CHECK-NEXT:    vmov d8, r0, r1
213; CHECK-NEXT:    vmov q0, q4
214; CHECK-NEXT:    vpop {d8, d9}
215; CHECK-NEXT:    pop {r7, pc}
216entry:
217  %0 = call fast <2 x double> @llvm.rint.v2f64(<2 x double> %src)
218  ret <2 x double> %0
219}
220
221define arm_aapcs_vfpcc <4 x float> @fnearbyint_float32_t(<4 x float> %src) {
222; CHECK-LABEL: fnearbyint_float32_t:
223; CHECK:       @ %bb.0: @ %entry
224; CHECK-NEXT:    vrintr.f32 s3, s3
225; CHECK-NEXT:    vrintr.f32 s2, s2
226; CHECK-NEXT:    vrintr.f32 s1, s1
227; CHECK-NEXT:    vrintr.f32 s0, s0
228; CHECK-NEXT:    bx lr
229entry:
230  %0 = call fast <4 x float> @llvm.nearbyint.v4f32(<4 x float> %src)
231  ret <4 x float> %0
232}
233
234define arm_aapcs_vfpcc <8 x half> @fnearbyint_float16_t(<8 x half> %src) {
235; CHECK-LABEL: fnearbyint_float16_t:
236; CHECK:       @ %bb.0: @ %entry
237; CHECK-NEXT:    vmovx.f16 s4, s0
238; CHECK-NEXT:    vrintr.f16 s0, s0
239; CHECK-NEXT:    vrintr.f16 s4, s4
240; CHECK-NEXT:    vins.f16 s0, s4
241; CHECK-NEXT:    vmovx.f16 s4, s1
242; CHECK-NEXT:    vrintr.f16 s4, s4
243; CHECK-NEXT:    vrintr.f16 s1, s1
244; CHECK-NEXT:    vins.f16 s1, s4
245; CHECK-NEXT:    vmovx.f16 s4, s2
246; CHECK-NEXT:    vrintr.f16 s4, s4
247; CHECK-NEXT:    vrintr.f16 s2, s2
248; CHECK-NEXT:    vins.f16 s2, s4
249; CHECK-NEXT:    vmovx.f16 s4, s3
250; CHECK-NEXT:    vrintr.f16 s4, s4
251; CHECK-NEXT:    vrintr.f16 s3, s3
252; CHECK-NEXT:    vins.f16 s3, s4
253; CHECK-NEXT:    bx lr
254entry:
255  %0 = call fast <8 x half> @llvm.nearbyint.v8f16(<8 x half> %src)
256  ret <8 x half> %0
257}
258
259define arm_aapcs_vfpcc <2 x double> @fnearbyint_float64_t(<2 x double> %src) {
260; CHECK-LABEL: fnearbyint_float64_t:
261; CHECK:       @ %bb.0: @ %entry
262; CHECK-NEXT:    .save {r7, lr}
263; CHECK-NEXT:    push {r7, lr}
264; CHECK-NEXT:    .vsave {d8, d9}
265; CHECK-NEXT:    vpush {d8, d9}
266; CHECK-NEXT:    vmov q4, q0
267; CHECK-NEXT:    vmov r0, r1, d9
268; CHECK-NEXT:    bl nearbyint
269; CHECK-NEXT:    vmov r2, r3, d8
270; CHECK-NEXT:    vmov d9, r0, r1
271; CHECK-NEXT:    mov r0, r2
272; CHECK-NEXT:    mov r1, r3
273; CHECK-NEXT:    bl nearbyint
274; CHECK-NEXT:    vmov d8, r0, r1
275; CHECK-NEXT:    vmov q0, q4
276; CHECK-NEXT:    vpop {d8, d9}
277; CHECK-NEXT:    pop {r7, pc}
278entry:
279  %0 = call fast <2 x double> @llvm.nearbyint.v2f64(<2 x double> %src)
280  ret <2 x double> %0
281}
282
283define arm_aapcs_vfpcc <4 x float> @ffloor_float32_t(<4 x float> %src) {
284; CHECK-MVE-LABEL: ffloor_float32_t:
285; CHECK-MVE:       @ %bb.0: @ %entry
286; CHECK-MVE-NEXT:    vrintm.f32 s3, s3
287; CHECK-MVE-NEXT:    vrintm.f32 s2, s2
288; CHECK-MVE-NEXT:    vrintm.f32 s1, s1
289; CHECK-MVE-NEXT:    vrintm.f32 s0, s0
290; CHECK-MVE-NEXT:    bx lr
291;
292; CHECK-MVEFP-LABEL: ffloor_float32_t:
293; CHECK-MVEFP:       @ %bb.0: @ %entry
294; CHECK-MVEFP-NEXT:    vrintm.f32 q0, q0
295; CHECK-MVEFP-NEXT:    bx lr
296entry:
297  %0 = call fast <4 x float> @llvm.floor.v4f32(<4 x float> %src)
298  ret <4 x float> %0
299}
300
301define arm_aapcs_vfpcc <8 x half> @ffloor_float16_t(<8 x half> %src) {
302; CHECK-MVE-LABEL: ffloor_float16_t:
303; CHECK-MVE:       @ %bb.0: @ %entry
304; CHECK-MVE-NEXT:    vmovx.f16 s4, s0
305; CHECK-MVE-NEXT:    vrintm.f16 s0, s0
306; CHECK-MVE-NEXT:    vrintm.f16 s4, s4
307; CHECK-MVE-NEXT:    vins.f16 s0, s4
308; CHECK-MVE-NEXT:    vmovx.f16 s4, s1
309; CHECK-MVE-NEXT:    vrintm.f16 s4, s4
310; CHECK-MVE-NEXT:    vrintm.f16 s1, s1
311; CHECK-MVE-NEXT:    vins.f16 s1, s4
312; CHECK-MVE-NEXT:    vmovx.f16 s4, s2
313; CHECK-MVE-NEXT:    vrintm.f16 s4, s4
314; CHECK-MVE-NEXT:    vrintm.f16 s2, s2
315; CHECK-MVE-NEXT:    vins.f16 s2, s4
316; CHECK-MVE-NEXT:    vmovx.f16 s4, s3
317; CHECK-MVE-NEXT:    vrintm.f16 s4, s4
318; CHECK-MVE-NEXT:    vrintm.f16 s3, s3
319; CHECK-MVE-NEXT:    vins.f16 s3, s4
320; CHECK-MVE-NEXT:    bx lr
321;
322; CHECK-MVEFP-LABEL: ffloor_float16_t:
323; CHECK-MVEFP:       @ %bb.0: @ %entry
324; CHECK-MVEFP-NEXT:    vrintm.f16 q0, q0
325; CHECK-MVEFP-NEXT:    bx lr
326entry:
327  %0 = call fast <8 x half> @llvm.floor.v8f16(<8 x half> %src)
328  ret <8 x half> %0
329}
330
331define arm_aapcs_vfpcc <2 x double> @ffloor_float64_t(<2 x double> %src) {
332; CHECK-LABEL: ffloor_float64_t:
333; CHECK:       @ %bb.0: @ %entry
334; CHECK-NEXT:    .save {r7, lr}
335; CHECK-NEXT:    push {r7, lr}
336; CHECK-NEXT:    .vsave {d8, d9}
337; CHECK-NEXT:    vpush {d8, d9}
338; CHECK-NEXT:    vmov q4, q0
339; CHECK-NEXT:    vmov r0, r1, d9
340; CHECK-NEXT:    bl floor
341; CHECK-NEXT:    vmov r2, r3, d8
342; CHECK-NEXT:    vmov d9, r0, r1
343; CHECK-NEXT:    mov r0, r2
344; CHECK-NEXT:    mov r1, r3
345; CHECK-NEXT:    bl floor
346; CHECK-NEXT:    vmov d8, r0, r1
347; CHECK-NEXT:    vmov q0, q4
348; CHECK-NEXT:    vpop {d8, d9}
349; CHECK-NEXT:    pop {r7, pc}
350entry:
351  %0 = call fast <2 x double> @llvm.floor.v2f64(<2 x double> %src)
352  ret <2 x double> %0
353}
354
355define arm_aapcs_vfpcc <4 x float> @fround_float32_t(<4 x float> %src) {
356; CHECK-MVE-LABEL: fround_float32_t:
357; CHECK-MVE:       @ %bb.0: @ %entry
358; CHECK-MVE-NEXT:    vrinta.f32 s3, s3
359; CHECK-MVE-NEXT:    vrinta.f32 s2, s2
360; CHECK-MVE-NEXT:    vrinta.f32 s1, s1
361; CHECK-MVE-NEXT:    vrinta.f32 s0, s0
362; CHECK-MVE-NEXT:    bx lr
363;
364; CHECK-MVEFP-LABEL: fround_float32_t:
365; CHECK-MVEFP:       @ %bb.0: @ %entry
366; CHECK-MVEFP-NEXT:    vrinta.f32 q0, q0
367; CHECK-MVEFP-NEXT:    bx lr
368entry:
369  %0 = call fast <4 x float> @llvm.round.v4f32(<4 x float> %src)
370  ret <4 x float> %0
371}
372
373define arm_aapcs_vfpcc <8 x half> @fround_float16_t(<8 x half> %src) {
374; CHECK-MVE-LABEL: fround_float16_t:
375; CHECK-MVE:       @ %bb.0: @ %entry
376; CHECK-MVE-NEXT:    vmovx.f16 s4, s0
377; CHECK-MVE-NEXT:    vrinta.f16 s0, s0
378; CHECK-MVE-NEXT:    vrinta.f16 s4, s4
379; CHECK-MVE-NEXT:    vins.f16 s0, s4
380; CHECK-MVE-NEXT:    vmovx.f16 s4, s1
381; CHECK-MVE-NEXT:    vrinta.f16 s4, s4
382; CHECK-MVE-NEXT:    vrinta.f16 s1, s1
383; CHECK-MVE-NEXT:    vins.f16 s1, s4
384; CHECK-MVE-NEXT:    vmovx.f16 s4, s2
385; CHECK-MVE-NEXT:    vrinta.f16 s4, s4
386; CHECK-MVE-NEXT:    vrinta.f16 s2, s2
387; CHECK-MVE-NEXT:    vins.f16 s2, s4
388; CHECK-MVE-NEXT:    vmovx.f16 s4, s3
389; CHECK-MVE-NEXT:    vrinta.f16 s4, s4
390; CHECK-MVE-NEXT:    vrinta.f16 s3, s3
391; CHECK-MVE-NEXT:    vins.f16 s3, s4
392; CHECK-MVE-NEXT:    bx lr
393;
394; CHECK-MVEFP-LABEL: fround_float16_t:
395; CHECK-MVEFP:       @ %bb.0: @ %entry
396; CHECK-MVEFP-NEXT:    vrinta.f16 q0, q0
397; CHECK-MVEFP-NEXT:    bx lr
398entry:
399  %0 = call fast <8 x half> @llvm.round.v8f16(<8 x half> %src)
400  ret <8 x half> %0
401}
402
403define arm_aapcs_vfpcc <2 x double> @fround_float64_t(<2 x double> %src) {
404; CHECK-LABEL: fround_float64_t:
405; CHECK:       @ %bb.0: @ %entry
406; CHECK-NEXT:    .save {r7, lr}
407; CHECK-NEXT:    push {r7, lr}
408; CHECK-NEXT:    .vsave {d8, d9}
409; CHECK-NEXT:    vpush {d8, d9}
410; CHECK-NEXT:    vmov q4, q0
411; CHECK-NEXT:    vmov r0, r1, d9
412; CHECK-NEXT:    bl round
413; CHECK-NEXT:    vmov r2, r3, d8
414; CHECK-NEXT:    vmov d9, r0, r1
415; CHECK-NEXT:    mov r0, r2
416; CHECK-NEXT:    mov r1, r3
417; CHECK-NEXT:    bl round
418; CHECK-NEXT:    vmov d8, r0, r1
419; CHECK-NEXT:    vmov q0, q4
420; CHECK-NEXT:    vpop {d8, d9}
421; CHECK-NEXT:    pop {r7, pc}
422entry:
423  %0 = call fast <2 x double> @llvm.round.v2f64(<2 x double> %src)
424  ret <2 x double> %0
425}
426
427declare <4 x float> @llvm.ceil.v4f32(<4 x float>)
428declare <4 x float> @llvm.trunc.v4f32(<4 x float>)
429declare <4 x float> @llvm.rint.v4f32(<4 x float>)
430declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>)
431declare <4 x float> @llvm.floor.v4f32(<4 x float>)
432declare <4 x float> @llvm.round.v4f32(<4 x float>)
433declare <8 x half> @llvm.ceil.v8f16(<8 x half>)
434declare <8 x half> @llvm.trunc.v8f16(<8 x half>)
435declare <8 x half> @llvm.rint.v8f16(<8 x half>)
436declare <8 x half> @llvm.nearbyint.v8f16(<8 x half>)
437declare <8 x half> @llvm.floor.v8f16(<8 x half>)
438declare <8 x half> @llvm.round.v8f16(<8 x half>)
439declare <2 x double> @llvm.ceil.v2f64(<2 x double>)
440declare <2 x double> @llvm.trunc.v2f64(<2 x double>)
441declare <2 x double> @llvm.rint.v2f64(<2 x double>)
442declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>)
443declare <2 x double> @llvm.floor.v2f64(<2 x double>)
444declare <2 x double> @llvm.round.v2f64(<2 x double>)
445