xref: /llvm-project/llvm/test/CodeGen/VE/Scalar/atomicrmw-uinc-udec-wrap.ll (revision 778cf5431cafc243f81dd5c8cbd27701ff7f9120) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=ve-unknown-unknown < %s | FileCheck %s
3
4define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
5; CHECK-LABEL: atomicrmw_uinc_wrap_i8:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    and %s3, %s1, (32)0
8; CHECK-NEXT:    fencem 3
9; CHECK-NEXT:    and %s1, -4, %s0
10; CHECK-NEXT:    and %s0, 3, %s0
11; CHECK-NEXT:    sla.w.sx %s0, %s0, 3
12; CHECK-NEXT:    sla.w.sx %s2, (56)0, %s0
13; CHECK-NEXT:    ldl.sx %s4, (, %s1)
14; CHECK-NEXT:    xor %s2, -1, %s2
15; CHECK-NEXT:    and %s2, %s2, (32)0
16; CHECK-NEXT:    and %s3, %s3, (56)0
17; CHECK-NEXT:  .LBB0_1: # %atomicrmw.start
18; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
19; CHECK-NEXT:    or %s5, 0, %s4
20; CHECK-NEXT:    and %s4, %s5, (32)0
21; CHECK-NEXT:    srl %s4, %s4, %s0
22; CHECK-NEXT:    and %s6, %s4, (56)0
23; CHECK-NEXT:    adds.w.sx %s4, 1, %s4
24; CHECK-NEXT:    cmpu.w %s6, %s6, %s3
25; CHECK-NEXT:    cmov.w.ge %s4, (0)1, %s6
26; CHECK-NEXT:    and %s4, %s4, (56)0
27; CHECK-NEXT:    sla.w.sx %s4, %s4, %s0
28; CHECK-NEXT:    and %s6, %s5, %s2
29; CHECK-NEXT:    or %s4, %s6, %s4
30; CHECK-NEXT:    cas.w %s4, (%s1), %s5
31; CHECK-NEXT:    brne.w %s4, %s5, .LBB0_1
32; CHECK-NEXT:  # %bb.2: # %atomicrmw.end
33; CHECK-NEXT:    and %s1, %s4, (32)0
34; CHECK-NEXT:    srl %s0, %s1, %s0
35; CHECK-NEXT:    fencem 3
36; CHECK-NEXT:    b.l.t (, %s10)
37  %result = atomicrmw uinc_wrap ptr %ptr, i8 %val seq_cst
38  ret i8 %result
39}
40
41define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) {
42; CHECK-LABEL: atomicrmw_uinc_wrap_i16:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    and %s3, %s1, (32)0
45; CHECK-NEXT:    fencem 3
46; CHECK-NEXT:    and %s1, -4, %s0
47; CHECK-NEXT:    and %s0, 3, %s0
48; CHECK-NEXT:    sla.w.sx %s0, %s0, 3
49; CHECK-NEXT:    sla.w.sx %s2, (48)0, %s0
50; CHECK-NEXT:    ldl.sx %s4, (, %s1)
51; CHECK-NEXT:    xor %s2, -1, %s2
52; CHECK-NEXT:    and %s2, %s2, (32)0
53; CHECK-NEXT:    and %s3, %s3, (48)0
54; CHECK-NEXT:  .LBB1_1: # %atomicrmw.start
55; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
56; CHECK-NEXT:    or %s5, 0, %s4
57; CHECK-NEXT:    and %s4, %s5, (32)0
58; CHECK-NEXT:    srl %s4, %s4, %s0
59; CHECK-NEXT:    and %s6, %s4, (48)0
60; CHECK-NEXT:    adds.w.sx %s4, 1, %s4
61; CHECK-NEXT:    cmpu.w %s6, %s6, %s3
62; CHECK-NEXT:    cmov.w.ge %s4, (0)1, %s6
63; CHECK-NEXT:    and %s4, %s4, (48)0
64; CHECK-NEXT:    sla.w.sx %s4, %s4, %s0
65; CHECK-NEXT:    and %s6, %s5, %s2
66; CHECK-NEXT:    or %s4, %s6, %s4
67; CHECK-NEXT:    cas.w %s4, (%s1), %s5
68; CHECK-NEXT:    brne.w %s4, %s5, .LBB1_1
69; CHECK-NEXT:  # %bb.2: # %atomicrmw.end
70; CHECK-NEXT:    and %s1, %s4, (32)0
71; CHECK-NEXT:    srl %s0, %s1, %s0
72; CHECK-NEXT:    fencem 3
73; CHECK-NEXT:    b.l.t (, %s10)
74  %result = atomicrmw uinc_wrap ptr %ptr, i16 %val seq_cst
75  ret i16 %result
76}
77
78define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) {
79; CHECK-LABEL: atomicrmw_uinc_wrap_i32:
80; CHECK:       # %bb.0:
81; CHECK-NEXT:    fencem 3
82; CHECK-NEXT:    ldl.sx %s2, (, %s0)
83; CHECK-NEXT:    and %s1, %s1, (32)0
84; CHECK-NEXT:  .LBB2_1: # %atomicrmw.start
85; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
86; CHECK-NEXT:    or %s3, 0, %s2
87; CHECK-NEXT:    adds.w.sx %s2, 1, %s2
88; CHECK-NEXT:    cmpu.w %s4, %s3, %s1
89; CHECK-NEXT:    cmov.w.ge %s2, (0)1, %s4
90; CHECK-NEXT:    cas.w %s2, (%s0), %s3
91; CHECK-NEXT:    brne.w %s2, %s3, .LBB2_1
92; CHECK-NEXT:  # %bb.2: # %atomicrmw.end
93; CHECK-NEXT:    fencem 3
94; CHECK-NEXT:    or %s0, 0, %s2
95; CHECK-NEXT:    b.l.t (, %s10)
96  %result = atomicrmw uinc_wrap ptr %ptr, i32 %val seq_cst
97  ret i32 %result
98}
99
100define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) {
101; CHECK-LABEL: atomicrmw_uinc_wrap_i64:
102; CHECK:       # %bb.0:
103; CHECK-NEXT:    fencem 3
104; CHECK-NEXT:    ld %s2, (, %s0)
105; CHECK-NEXT:  .LBB3_1: # %atomicrmw.start
106; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
107; CHECK-NEXT:    or %s3, 0, %s2
108; CHECK-NEXT:    lea %s2, 1(, %s2)
109; CHECK-NEXT:    cmpu.l %s4, %s3, %s1
110; CHECK-NEXT:    cmov.l.ge %s2, (0)1, %s4
111; CHECK-NEXT:    cas.l %s2, (%s0), %s3
112; CHECK-NEXT:    brne.l %s2, %s3, .LBB3_1
113; CHECK-NEXT:  # %bb.2: # %atomicrmw.end
114; CHECK-NEXT:    fencem 3
115; CHECK-NEXT:    or %s0, 0, %s2
116; CHECK-NEXT:    b.l.t (, %s10)
117  %result = atomicrmw uinc_wrap ptr %ptr, i64 %val seq_cst
118  ret i64 %result
119}
120
121define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) {
122; CHECK-LABEL: atomicrmw_udec_wrap_i8:
123; CHECK:       # %bb.0:
124; CHECK-NEXT:    and %s1, %s1, (32)0
125; CHECK-NEXT:    fencem 3
126; CHECK-NEXT:    and %s2, -4, %s0
127; CHECK-NEXT:    and %s0, 3, %s0
128; CHECK-NEXT:    sla.w.sx %s0, %s0, 3
129; CHECK-NEXT:    sla.w.sx %s3, (56)0, %s0
130; CHECK-NEXT:    ldl.sx %s5, (, %s2)
131; CHECK-NEXT:    xor %s3, -1, %s3
132; CHECK-NEXT:    and %s3, %s3, (32)0
133; CHECK-NEXT:    and %s4, %s1, (56)0
134; CHECK-NEXT:  .LBB4_1: # %atomicrmw.start
135; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
136; CHECK-NEXT:    or %s6, 0, %s5
137; CHECK-NEXT:    and %s5, %s6, (32)0
138; CHECK-NEXT:    srl %s5, %s5, %s0
139; CHECK-NEXT:    and %s7, %s5, (56)0
140; CHECK-NEXT:    adds.w.sx %s5, -1, %s5
141; CHECK-NEXT:    cmpu.w %s34, %s7, %s4
142; CHECK-NEXT:    cmov.w.gt %s5, %s1, %s34
143; CHECK-NEXT:    cmov.w.eq %s5, %s1, %s7
144; CHECK-NEXT:    and %s5, %s5, (56)0
145; CHECK-NEXT:    sla.w.sx %s5, %s5, %s0
146; CHECK-NEXT:    and %s7, %s6, %s3
147; CHECK-NEXT:    or %s5, %s7, %s5
148; CHECK-NEXT:    cas.w %s5, (%s2), %s6
149; CHECK-NEXT:    brne.w %s5, %s6, .LBB4_1
150; CHECK-NEXT:  # %bb.2: # %atomicrmw.end
151; CHECK-NEXT:    and %s1, %s5, (32)0
152; CHECK-NEXT:    srl %s0, %s1, %s0
153; CHECK-NEXT:    fencem 3
154; CHECK-NEXT:    b.l.t (, %s10)
155  %result = atomicrmw udec_wrap ptr %ptr, i8 %val seq_cst
156  ret i8 %result
157}
158
159define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) {
160; CHECK-LABEL: atomicrmw_udec_wrap_i16:
161; CHECK:       # %bb.0:
162; CHECK-NEXT:    and %s1, %s1, (32)0
163; CHECK-NEXT:    fencem 3
164; CHECK-NEXT:    and %s2, -4, %s0
165; CHECK-NEXT:    and %s0, 3, %s0
166; CHECK-NEXT:    sla.w.sx %s0, %s0, 3
167; CHECK-NEXT:    sla.w.sx %s3, (48)0, %s0
168; CHECK-NEXT:    ldl.sx %s5, (, %s2)
169; CHECK-NEXT:    xor %s3, -1, %s3
170; CHECK-NEXT:    and %s3, %s3, (32)0
171; CHECK-NEXT:    and %s4, %s1, (48)0
172; CHECK-NEXT:  .LBB5_1: # %atomicrmw.start
173; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
174; CHECK-NEXT:    or %s6, 0, %s5
175; CHECK-NEXT:    and %s5, %s6, (32)0
176; CHECK-NEXT:    srl %s5, %s5, %s0
177; CHECK-NEXT:    and %s7, %s5, (48)0
178; CHECK-NEXT:    adds.w.sx %s5, -1, %s5
179; CHECK-NEXT:    cmpu.w %s34, %s7, %s4
180; CHECK-NEXT:    cmov.w.gt %s5, %s1, %s34
181; CHECK-NEXT:    cmov.w.eq %s5, %s1, %s7
182; CHECK-NEXT:    and %s5, %s5, (48)0
183; CHECK-NEXT:    sla.w.sx %s5, %s5, %s0
184; CHECK-NEXT:    and %s7, %s6, %s3
185; CHECK-NEXT:    or %s5, %s7, %s5
186; CHECK-NEXT:    cas.w %s5, (%s2), %s6
187; CHECK-NEXT:    brne.w %s5, %s6, .LBB5_1
188; CHECK-NEXT:  # %bb.2: # %atomicrmw.end
189; CHECK-NEXT:    and %s1, %s5, (32)0
190; CHECK-NEXT:    srl %s0, %s1, %s0
191; CHECK-NEXT:    fencem 3
192; CHECK-NEXT:    b.l.t (, %s10)
193  %result = atomicrmw udec_wrap ptr %ptr, i16 %val seq_cst
194  ret i16 %result
195}
196
197define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) {
198; CHECK-LABEL: atomicrmw_udec_wrap_i32:
199; CHECK:       # %bb.0:
200; CHECK-NEXT:    fencem 3
201; CHECK-NEXT:    ldl.sx %s2, (, %s0)
202; CHECK-NEXT:    and %s1, %s1, (32)0
203; CHECK-NEXT:  .LBB6_1: # %atomicrmw.start
204; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
205; CHECK-NEXT:    or %s3, 0, %s2
206; CHECK-NEXT:    adds.w.sx %s2, -1, %s2
207; CHECK-NEXT:    cmpu.w %s4, %s3, %s1
208; CHECK-NEXT:    cmov.w.gt %s2, %s1, %s4
209; CHECK-NEXT:    cmov.w.eq %s2, %s1, %s3
210; CHECK-NEXT:    cas.w %s2, (%s0), %s3
211; CHECK-NEXT:    brne.w %s2, %s3, .LBB6_1
212; CHECK-NEXT:  # %bb.2: # %atomicrmw.end
213; CHECK-NEXT:    fencem 3
214; CHECK-NEXT:    or %s0, 0, %s2
215; CHECK-NEXT:    b.l.t (, %s10)
216  %result = atomicrmw udec_wrap ptr %ptr, i32 %val seq_cst
217  ret i32 %result
218}
219
220define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) {
221; CHECK-LABEL: atomicrmw_udec_wrap_i64:
222; CHECK:       # %bb.0:
223; CHECK-NEXT:    fencem 3
224; CHECK-NEXT:    ld %s2, (, %s0)
225; CHECK-NEXT:  .LBB7_1: # %atomicrmw.start
226; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
227; CHECK-NEXT:    or %s3, 0, %s2
228; CHECK-NEXT:    lea %s2, -1(, %s2)
229; CHECK-NEXT:    cmpu.l %s4, %s3, %s1
230; CHECK-NEXT:    cmov.l.gt %s2, %s1, %s4
231; CHECK-NEXT:    cmov.l.eq %s2, %s1, %s3
232; CHECK-NEXT:    cas.l %s2, (%s0), %s3
233; CHECK-NEXT:    brne.l %s2, %s3, .LBB7_1
234; CHECK-NEXT:  # %bb.2: # %atomicrmw.end
235; CHECK-NEXT:    fencem 3
236; CHECK-NEXT:    or %s0, 0, %s2
237; CHECK-NEXT:    b.l.t (, %s10)
238  %result = atomicrmw udec_wrap ptr %ptr, i64 %val seq_cst
239  ret i64 %result
240}
241