1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE 3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVEFP 4 5define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 6; CHECK-MVE-LABEL: vcmp_oeq_v4f32: 7; CHECK-MVE: @ %bb.0: @ %entry 8; CHECK-MVE-NEXT: vcmp.f32 s0, #0 9; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 10; CHECK-MVE-NEXT: vcmp.f32 s3, #0 11; CHECK-MVE-NEXT: cset r0, eq 12; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 13; CHECK-MVE-NEXT: vcmp.f32 s1, #0 14; CHECK-MVE-NEXT: cset r1, eq 15; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 16; CHECK-MVE-NEXT: vcmp.f32 s2, #0 17; CHECK-MVE-NEXT: cset r2, eq 18; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 19; CHECK-MVE-NEXT: cset r3, eq 20; CHECK-MVE-NEXT: cmp r3, #0 21; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 22; CHECK-MVE-NEXT: cmp r2, #0 23; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 24; CHECK-MVE-NEXT: cmp r1, #0 25; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 26; CHECK-MVE-NEXT: cmp r0, #0 27; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 28; CHECK-MVE-NEXT: bx lr 29; 30; CHECK-MVEFP-LABEL: vcmp_oeq_v4f32: 31; CHECK-MVEFP: @ %bb.0: @ %entry 32; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, zr 33; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 34; CHECK-MVEFP-NEXT: bx lr 35entry: 36 %c = fcmp oeq <4 x float> %src, zeroinitializer 37 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 38 ret <4 x float> %s 39} 40 41define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 42; CHECK-MVE-LABEL: vcmp_one_v4f32: 43; CHECK-MVE: @ %bb.0: @ %entry 44; CHECK-MVE-NEXT: vcmp.f32 s0, #0 45; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 46; CHECK-MVE-NEXT: vcmp.f32 s3, #0 47; CHECK-MVE-NEXT: cset r0, mi 48; CHECK-MVE-NEXT: csinc r0, r0, zr, le 49; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 50; CHECK-MVE-NEXT: vcmp.f32 s1, #0 51; CHECK-MVE-NEXT: cset r1, mi 52; CHECK-MVE-NEXT: csinc r1, r1, zr, le 53; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 54; CHECK-MVE-NEXT: vcmp.f32 s2, #0 55; CHECK-MVE-NEXT: cset r2, mi 56; CHECK-MVE-NEXT: csinc r2, r2, zr, le 57; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 58; CHECK-MVE-NEXT: cset r3, mi 59; CHECK-MVE-NEXT: csinc r3, r3, zr, le 60; CHECK-MVE-NEXT: cmp r3, #0 61; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 62; CHECK-MVE-NEXT: cmp r2, #0 63; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 64; CHECK-MVE-NEXT: cmp r1, #0 65; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 66; CHECK-MVE-NEXT: cmp r0, #0 67; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 68; CHECK-MVE-NEXT: bx lr 69; 70; CHECK-MVEFP-LABEL: vcmp_one_v4f32: 71; CHECK-MVEFP: @ %bb.0: @ %entry 72; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr 73; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, zr 74; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 75; CHECK-MVEFP-NEXT: bx lr 76entry: 77 %c = fcmp one <4 x float> %src, zeroinitializer 78 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 79 ret <4 x float> %s 80} 81 82define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 83; CHECK-MVE-LABEL: vcmp_ogt_v4f32: 84; CHECK-MVE: @ %bb.0: @ %entry 85; CHECK-MVE-NEXT: vcmp.f32 s0, #0 86; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 87; CHECK-MVE-NEXT: vcmp.f32 s3, #0 88; CHECK-MVE-NEXT: cset r0, gt 89; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 90; CHECK-MVE-NEXT: vcmp.f32 s1, #0 91; CHECK-MVE-NEXT: cset r1, gt 92; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 93; CHECK-MVE-NEXT: vcmp.f32 s2, #0 94; CHECK-MVE-NEXT: cset r2, gt 95; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 96; CHECK-MVE-NEXT: cset r3, gt 97; CHECK-MVE-NEXT: cmp r3, #0 98; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 99; CHECK-MVE-NEXT: cmp r2, #0 100; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 101; CHECK-MVE-NEXT: cmp r1, #0 102; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 103; CHECK-MVE-NEXT: cmp r0, #0 104; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 105; CHECK-MVE-NEXT: bx lr 106; 107; CHECK-MVEFP-LABEL: vcmp_ogt_v4f32: 108; CHECK-MVEFP: @ %bb.0: @ %entry 109; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr 110; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 111; CHECK-MVEFP-NEXT: bx lr 112entry: 113 %c = fcmp ogt <4 x float> %src, zeroinitializer 114 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 115 ret <4 x float> %s 116} 117 118define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 119; CHECK-MVE-LABEL: vcmp_oge_v4f32: 120; CHECK-MVE: @ %bb.0: @ %entry 121; CHECK-MVE-NEXT: vcmp.f32 s0, #0 122; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 123; CHECK-MVE-NEXT: vcmp.f32 s3, #0 124; CHECK-MVE-NEXT: cset r0, ge 125; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 126; CHECK-MVE-NEXT: vcmp.f32 s1, #0 127; CHECK-MVE-NEXT: cset r1, ge 128; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 129; CHECK-MVE-NEXT: vcmp.f32 s2, #0 130; CHECK-MVE-NEXT: cset r2, ge 131; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 132; CHECK-MVE-NEXT: cset r3, ge 133; CHECK-MVE-NEXT: cmp r3, #0 134; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 135; CHECK-MVE-NEXT: cmp r2, #0 136; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 137; CHECK-MVE-NEXT: cmp r1, #0 138; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 139; CHECK-MVE-NEXT: cmp r0, #0 140; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 141; CHECK-MVE-NEXT: bx lr 142; 143; CHECK-MVEFP-LABEL: vcmp_oge_v4f32: 144; CHECK-MVEFP: @ %bb.0: @ %entry 145; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr 146; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 147; CHECK-MVEFP-NEXT: bx lr 148entry: 149 %c = fcmp oge <4 x float> %src, zeroinitializer 150 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 151 ret <4 x float> %s 152} 153 154define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 155; CHECK-MVE-LABEL: vcmp_olt_v4f32: 156; CHECK-MVE: @ %bb.0: @ %entry 157; CHECK-MVE-NEXT: vcmp.f32 s0, #0 158; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 159; CHECK-MVE-NEXT: vcmp.f32 s3, #0 160; CHECK-MVE-NEXT: cset r0, mi 161; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 162; CHECK-MVE-NEXT: vcmp.f32 s1, #0 163; CHECK-MVE-NEXT: cset r1, mi 164; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 165; CHECK-MVE-NEXT: vcmp.f32 s2, #0 166; CHECK-MVE-NEXT: cset r2, mi 167; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 168; CHECK-MVE-NEXT: cset r3, mi 169; CHECK-MVE-NEXT: cmp r3, #0 170; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 171; CHECK-MVE-NEXT: cmp r2, #0 172; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 173; CHECK-MVE-NEXT: cmp r1, #0 174; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 175; CHECK-MVE-NEXT: cmp r0, #0 176; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 177; CHECK-MVE-NEXT: bx lr 178; 179; CHECK-MVEFP-LABEL: vcmp_olt_v4f32: 180; CHECK-MVEFP: @ %bb.0: @ %entry 181; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr 182; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 183; CHECK-MVEFP-NEXT: bx lr 184entry: 185 %c = fcmp olt <4 x float> %src, zeroinitializer 186 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 187 ret <4 x float> %s 188} 189 190define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 191; CHECK-MVE-LABEL: vcmp_ole_v4f32: 192; CHECK-MVE: @ %bb.0: @ %entry 193; CHECK-MVE-NEXT: vcmp.f32 s0, #0 194; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 195; CHECK-MVE-NEXT: vcmp.f32 s3, #0 196; CHECK-MVE-NEXT: cset r0, ls 197; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 198; CHECK-MVE-NEXT: vcmp.f32 s1, #0 199; CHECK-MVE-NEXT: cset r1, ls 200; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 201; CHECK-MVE-NEXT: vcmp.f32 s2, #0 202; CHECK-MVE-NEXT: cset r2, ls 203; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 204; CHECK-MVE-NEXT: cset r3, ls 205; CHECK-MVE-NEXT: cmp r3, #0 206; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 207; CHECK-MVE-NEXT: cmp r2, #0 208; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 209; CHECK-MVE-NEXT: cmp r1, #0 210; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 211; CHECK-MVE-NEXT: cmp r0, #0 212; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 213; CHECK-MVE-NEXT: bx lr 214; 215; CHECK-MVEFP-LABEL: vcmp_ole_v4f32: 216; CHECK-MVEFP: @ %bb.0: @ %entry 217; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr 218; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 219; CHECK-MVEFP-NEXT: bx lr 220entry: 221 %c = fcmp ole <4 x float> %src, zeroinitializer 222 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 223 ret <4 x float> %s 224} 225 226define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 227; CHECK-MVE-LABEL: vcmp_ueq_v4f32: 228; CHECK-MVE: @ %bb.0: @ %entry 229; CHECK-MVE-NEXT: vcmp.f32 s0, #0 230; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 231; CHECK-MVE-NEXT: vcmp.f32 s3, #0 232; CHECK-MVE-NEXT: cset r0, eq 233; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 234; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 235; CHECK-MVE-NEXT: vcmp.f32 s1, #0 236; CHECK-MVE-NEXT: cset r1, eq 237; CHECK-MVE-NEXT: csinc r1, r1, zr, vc 238; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 239; CHECK-MVE-NEXT: vcmp.f32 s2, #0 240; CHECK-MVE-NEXT: cset r2, eq 241; CHECK-MVE-NEXT: csinc r2, r2, zr, vc 242; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 243; CHECK-MVE-NEXT: cset r3, eq 244; CHECK-MVE-NEXT: csinc r3, r3, zr, vc 245; CHECK-MVE-NEXT: cmp r3, #0 246; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 247; CHECK-MVE-NEXT: cmp r2, #0 248; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 249; CHECK-MVE-NEXT: cmp r1, #0 250; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 251; CHECK-MVE-NEXT: cmp r0, #0 252; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 253; CHECK-MVE-NEXT: bx lr 254; 255; CHECK-MVEFP-LABEL: vcmp_ueq_v4f32: 256; CHECK-MVEFP: @ %bb.0: @ %entry 257; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr 258; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, zr 259; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 260; CHECK-MVEFP-NEXT: bx lr 261entry: 262 %c = fcmp ueq <4 x float> %src, zeroinitializer 263 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 264 ret <4 x float> %s 265} 266 267define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 268; CHECK-MVE-LABEL: vcmp_une_v4f32: 269; CHECK-MVE: @ %bb.0: @ %entry 270; CHECK-MVE-NEXT: vcmp.f32 s2, #0 271; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 272; CHECK-MVE-NEXT: vcmp.f32 s1, #0 273; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 274; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 275; CHECK-MVE-NEXT: vcmp.f32 s3, #0 276; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 277; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 278; CHECK-MVE-NEXT: vcmp.f32 s0, #0 279; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 280; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 281; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 282; CHECK-MVE-NEXT: bx lr 283; 284; CHECK-MVEFP-LABEL: vcmp_une_v4f32: 285; CHECK-MVEFP: @ %bb.0: @ %entry 286; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, zr 287; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 288; CHECK-MVEFP-NEXT: bx lr 289entry: 290 %c = fcmp une <4 x float> %src, zeroinitializer 291 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 292 ret <4 x float> %s 293} 294 295define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 296; CHECK-MVE-LABEL: vcmp_ugt_v4f32: 297; CHECK-MVE: @ %bb.0: @ %entry 298; CHECK-MVE-NEXT: vcmp.f32 s0, #0 299; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 300; CHECK-MVE-NEXT: vcmp.f32 s3, #0 301; CHECK-MVE-NEXT: cset r0, hi 302; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 303; CHECK-MVE-NEXT: vcmp.f32 s1, #0 304; CHECK-MVE-NEXT: cset r1, hi 305; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 306; CHECK-MVE-NEXT: vcmp.f32 s2, #0 307; CHECK-MVE-NEXT: cset r2, hi 308; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 309; CHECK-MVE-NEXT: cset r3, hi 310; CHECK-MVE-NEXT: cmp r3, #0 311; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 312; CHECK-MVE-NEXT: cmp r2, #0 313; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 314; CHECK-MVE-NEXT: cmp r1, #0 315; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 316; CHECK-MVE-NEXT: cmp r0, #0 317; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 318; CHECK-MVE-NEXT: bx lr 319; 320; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32: 321; CHECK-MVEFP: @ %bb.0: @ %entry 322; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr 323; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 324; CHECK-MVEFP-NEXT: bx lr 325entry: 326 %c = fcmp ugt <4 x float> %src, zeroinitializer 327 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 328 ret <4 x float> %s 329} 330 331define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 332; CHECK-MVE-LABEL: vcmp_uge_v4f32: 333; CHECK-MVE: @ %bb.0: @ %entry 334; CHECK-MVE-NEXT: vcmp.f32 s0, #0 335; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 336; CHECK-MVE-NEXT: vcmp.f32 s3, #0 337; CHECK-MVE-NEXT: cset r0, pl 338; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 339; CHECK-MVE-NEXT: vcmp.f32 s1, #0 340; CHECK-MVE-NEXT: cset r1, pl 341; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 342; CHECK-MVE-NEXT: vcmp.f32 s2, #0 343; CHECK-MVE-NEXT: cset r2, pl 344; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 345; CHECK-MVE-NEXT: cset r3, pl 346; CHECK-MVE-NEXT: cmp r3, #0 347; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 348; CHECK-MVE-NEXT: cmp r2, #0 349; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 350; CHECK-MVE-NEXT: cmp r1, #0 351; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 352; CHECK-MVE-NEXT: cmp r0, #0 353; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 354; CHECK-MVE-NEXT: bx lr 355; 356; CHECK-MVEFP-LABEL: vcmp_uge_v4f32: 357; CHECK-MVEFP: @ %bb.0: @ %entry 358; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr 359; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 360; CHECK-MVEFP-NEXT: bx lr 361entry: 362 %c = fcmp uge <4 x float> %src, zeroinitializer 363 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 364 ret <4 x float> %s 365} 366 367define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 368; CHECK-MVE-LABEL: vcmp_ult_v4f32: 369; CHECK-MVE: @ %bb.0: @ %entry 370; CHECK-MVE-NEXT: vcmp.f32 s0, #0 371; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 372; CHECK-MVE-NEXT: vcmp.f32 s3, #0 373; CHECK-MVE-NEXT: cset r0, lt 374; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 375; CHECK-MVE-NEXT: vcmp.f32 s1, #0 376; CHECK-MVE-NEXT: cset r1, lt 377; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 378; CHECK-MVE-NEXT: vcmp.f32 s2, #0 379; CHECK-MVE-NEXT: cset r2, lt 380; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 381; CHECK-MVE-NEXT: cset r3, lt 382; CHECK-MVE-NEXT: cmp r3, #0 383; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 384; CHECK-MVE-NEXT: cmp r2, #0 385; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 386; CHECK-MVE-NEXT: cmp r1, #0 387; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 388; CHECK-MVE-NEXT: cmp r0, #0 389; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 390; CHECK-MVE-NEXT: bx lr 391; 392; CHECK-MVEFP-LABEL: vcmp_ult_v4f32: 393; CHECK-MVEFP: @ %bb.0: @ %entry 394; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr 395; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 396; CHECK-MVEFP-NEXT: bx lr 397entry: 398 %c = fcmp ult <4 x float> %src, zeroinitializer 399 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 400 ret <4 x float> %s 401} 402 403define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 404; CHECK-MVE-LABEL: vcmp_ule_v4f32: 405; CHECK-MVE: @ %bb.0: @ %entry 406; CHECK-MVE-NEXT: vcmp.f32 s0, #0 407; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 408; CHECK-MVE-NEXT: vcmp.f32 s3, #0 409; CHECK-MVE-NEXT: cset r0, le 410; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 411; CHECK-MVE-NEXT: vcmp.f32 s1, #0 412; CHECK-MVE-NEXT: cset r1, le 413; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 414; CHECK-MVE-NEXT: vcmp.f32 s2, #0 415; CHECK-MVE-NEXT: cset r2, le 416; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 417; CHECK-MVE-NEXT: cset r3, le 418; CHECK-MVE-NEXT: cmp r3, #0 419; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 420; CHECK-MVE-NEXT: cmp r2, #0 421; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 422; CHECK-MVE-NEXT: cmp r1, #0 423; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 424; CHECK-MVE-NEXT: cmp r0, #0 425; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 426; CHECK-MVE-NEXT: bx lr 427; 428; CHECK-MVEFP-LABEL: vcmp_ule_v4f32: 429; CHECK-MVEFP: @ %bb.0: @ %entry 430; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr 431; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 432; CHECK-MVEFP-NEXT: bx lr 433entry: 434 %c = fcmp ule <4 x float> %src, zeroinitializer 435 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 436 ret <4 x float> %s 437} 438 439define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 440; CHECK-MVE-LABEL: vcmp_ord_v4f32: 441; CHECK-MVE: @ %bb.0: @ %entry 442; CHECK-MVE-NEXT: vcmp.f32 s0, s0 443; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 444; CHECK-MVE-NEXT: vcmp.f32 s3, s3 445; CHECK-MVE-NEXT: cset r0, vc 446; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 447; CHECK-MVE-NEXT: vcmp.f32 s1, s1 448; CHECK-MVE-NEXT: cset r1, vc 449; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 450; CHECK-MVE-NEXT: vcmp.f32 s2, s2 451; CHECK-MVE-NEXT: cset r2, vc 452; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 453; CHECK-MVE-NEXT: cset r3, vc 454; CHECK-MVE-NEXT: cmp r3, #0 455; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 456; CHECK-MVE-NEXT: cmp r2, #0 457; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 458; CHECK-MVE-NEXT: cmp r1, #0 459; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 460; CHECK-MVE-NEXT: cmp r0, #0 461; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 462; CHECK-MVE-NEXT: bx lr 463; 464; CHECK-MVEFP-LABEL: vcmp_ord_v4f32: 465; CHECK-MVEFP: @ %bb.0: @ %entry 466; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr 467; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, zr 468; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 469; CHECK-MVEFP-NEXT: bx lr 470entry: 471 %c = fcmp ord <4 x float> %src, zeroinitializer 472 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 473 ret <4 x float> %s 474} 475 476define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 477; CHECK-MVE-LABEL: vcmp_uno_v4f32: 478; CHECK-MVE: @ %bb.0: @ %entry 479; CHECK-MVE-NEXT: vcmp.f32 s0, s0 480; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 481; CHECK-MVE-NEXT: vcmp.f32 s3, s3 482; CHECK-MVE-NEXT: cset r0, vs 483; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 484; CHECK-MVE-NEXT: vcmp.f32 s1, s1 485; CHECK-MVE-NEXT: cset r1, vs 486; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 487; CHECK-MVE-NEXT: vcmp.f32 s2, s2 488; CHECK-MVE-NEXT: cset r2, vs 489; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 490; CHECK-MVE-NEXT: cset r3, vs 491; CHECK-MVE-NEXT: cmp r3, #0 492; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 493; CHECK-MVE-NEXT: cmp r2, #0 494; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 495; CHECK-MVE-NEXT: cmp r1, #0 496; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 497; CHECK-MVE-NEXT: cmp r0, #0 498; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 499; CHECK-MVE-NEXT: bx lr 500; 501; CHECK-MVEFP-LABEL: vcmp_uno_v4f32: 502; CHECK-MVEFP: @ %bb.0: @ %entry 503; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr 504; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, zr 505; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 506; CHECK-MVEFP-NEXT: bx lr 507entry: 508 %c = fcmp uno <4 x float> %src, zeroinitializer 509 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 510 ret <4 x float> %s 511} 512 513 514 515define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 516; CHECK-MVE-LABEL: vcmp_oeq_v8f16: 517; CHECK-MVE: @ %bb.0: @ %entry 518; CHECK-MVE-NEXT: vmovx.f16 s12, s0 519; CHECK-MVE-NEXT: vmovx.f16 s14, s8 520; CHECK-MVE-NEXT: vcmp.f16 s12, #0 521; CHECK-MVE-NEXT: vmovx.f16 s12, s4 522; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 523; CHECK-MVE-NEXT: vcmp.f16 s0, #0 524; CHECK-MVE-NEXT: cset r0, eq 525; CHECK-MVE-NEXT: cmp r0, #0 526; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 527; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 528; CHECK-MVE-NEXT: cset r0, eq 529; CHECK-MVE-NEXT: cmp r0, #0 530; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 531; CHECK-MVE-NEXT: vmovx.f16 s4, s1 532; CHECK-MVE-NEXT: vcmp.f16 s4, #0 533; CHECK-MVE-NEXT: vmovx.f16 s4, s5 534; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 535; CHECK-MVE-NEXT: vmovx.f16 s8, s9 536; CHECK-MVE-NEXT: vcmp.f16 s1, #0 537; CHECK-MVE-NEXT: vins.f16 s0, s12 538; CHECK-MVE-NEXT: cset r0, eq 539; CHECK-MVE-NEXT: cmp r0, #0 540; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 541; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 542; CHECK-MVE-NEXT: vmovx.f16 s8, s10 543; CHECK-MVE-NEXT: cset r0, eq 544; CHECK-MVE-NEXT: cmp r0, #0 545; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 546; CHECK-MVE-NEXT: vins.f16 s1, s4 547; CHECK-MVE-NEXT: vmovx.f16 s4, s2 548; CHECK-MVE-NEXT: vcmp.f16 s4, #0 549; CHECK-MVE-NEXT: vmovx.f16 s4, s6 550; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 551; CHECK-MVE-NEXT: vcmp.f16 s2, #0 552; CHECK-MVE-NEXT: cset r0, eq 553; CHECK-MVE-NEXT: cmp r0, #0 554; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 555; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 556; CHECK-MVE-NEXT: cset r0, eq 557; CHECK-MVE-NEXT: cmp r0, #0 558; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 559; CHECK-MVE-NEXT: vmovx.f16 s6, s11 560; CHECK-MVE-NEXT: vins.f16 s2, s4 561; CHECK-MVE-NEXT: vmovx.f16 s4, s3 562; CHECK-MVE-NEXT: vcmp.f16 s4, #0 563; CHECK-MVE-NEXT: vmovx.f16 s4, s7 564; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 565; CHECK-MVE-NEXT: vcmp.f16 s3, #0 566; CHECK-MVE-NEXT: cset r0, eq 567; CHECK-MVE-NEXT: cmp r0, #0 568; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 569; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 570; CHECK-MVE-NEXT: cset r0, eq 571; CHECK-MVE-NEXT: cmp r0, #0 572; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 573; CHECK-MVE-NEXT: vins.f16 s3, s4 574; CHECK-MVE-NEXT: bx lr 575; 576; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16: 577; CHECK-MVEFP: @ %bb.0: @ %entry 578; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr 579; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 580; CHECK-MVEFP-NEXT: bx lr 581entry: 582 %c = fcmp oeq <8 x half> %src, zeroinitializer 583 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 584 ret <8 x half> %s 585} 586 587define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 588; CHECK-MVE-LABEL: vcmp_one_v8f16: 589; CHECK-MVE: @ %bb.0: @ %entry 590; CHECK-MVE-NEXT: vmovx.f16 s12, s0 591; CHECK-MVE-NEXT: vmovx.f16 s14, s8 592; CHECK-MVE-NEXT: vcmp.f16 s12, #0 593; CHECK-MVE-NEXT: vmovx.f16 s12, s4 594; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 595; CHECK-MVE-NEXT: vcmp.f16 s0, #0 596; CHECK-MVE-NEXT: cset r0, mi 597; CHECK-MVE-NEXT: csinc r0, r0, zr, le 598; CHECK-MVE-NEXT: cmp r0, #0 599; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 600; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 601; CHECK-MVE-NEXT: cset r0, mi 602; CHECK-MVE-NEXT: csinc r0, r0, zr, le 603; CHECK-MVE-NEXT: cmp r0, #0 604; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 605; CHECK-MVE-NEXT: vmovx.f16 s4, s1 606; CHECK-MVE-NEXT: vcmp.f16 s4, #0 607; CHECK-MVE-NEXT: vmovx.f16 s4, s5 608; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 609; CHECK-MVE-NEXT: vmovx.f16 s8, s9 610; CHECK-MVE-NEXT: vcmp.f16 s1, #0 611; CHECK-MVE-NEXT: vins.f16 s0, s12 612; CHECK-MVE-NEXT: cset r0, mi 613; CHECK-MVE-NEXT: csinc r0, r0, zr, le 614; CHECK-MVE-NEXT: cmp r0, #0 615; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 616; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 617; CHECK-MVE-NEXT: vmovx.f16 s8, s10 618; CHECK-MVE-NEXT: cset r0, mi 619; CHECK-MVE-NEXT: csinc r0, r0, zr, le 620; CHECK-MVE-NEXT: cmp r0, #0 621; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 622; CHECK-MVE-NEXT: vins.f16 s1, s4 623; CHECK-MVE-NEXT: vmovx.f16 s4, s2 624; CHECK-MVE-NEXT: vcmp.f16 s4, #0 625; CHECK-MVE-NEXT: vmovx.f16 s4, s6 626; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 627; CHECK-MVE-NEXT: vcmp.f16 s2, #0 628; CHECK-MVE-NEXT: cset r0, mi 629; CHECK-MVE-NEXT: csinc r0, r0, zr, le 630; CHECK-MVE-NEXT: cmp r0, #0 631; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 632; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 633; CHECK-MVE-NEXT: cset r0, mi 634; CHECK-MVE-NEXT: csinc r0, r0, zr, le 635; CHECK-MVE-NEXT: cmp r0, #0 636; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 637; CHECK-MVE-NEXT: vmovx.f16 s6, s11 638; CHECK-MVE-NEXT: vins.f16 s2, s4 639; CHECK-MVE-NEXT: vmovx.f16 s4, s3 640; CHECK-MVE-NEXT: vcmp.f16 s4, #0 641; CHECK-MVE-NEXT: vmovx.f16 s4, s7 642; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 643; CHECK-MVE-NEXT: vcmp.f16 s3, #0 644; CHECK-MVE-NEXT: cset r0, mi 645; CHECK-MVE-NEXT: csinc r0, r0, zr, le 646; CHECK-MVE-NEXT: cmp r0, #0 647; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 648; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 649; CHECK-MVE-NEXT: cset r0, mi 650; CHECK-MVE-NEXT: csinc r0, r0, zr, le 651; CHECK-MVE-NEXT: cmp r0, #0 652; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 653; CHECK-MVE-NEXT: vins.f16 s3, s4 654; CHECK-MVE-NEXT: bx lr 655; 656; CHECK-MVEFP-LABEL: vcmp_one_v8f16: 657; CHECK-MVEFP: @ %bb.0: @ %entry 658; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr 659; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr 660; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 661; CHECK-MVEFP-NEXT: bx lr 662entry: 663 %c = fcmp one <8 x half> %src, zeroinitializer 664 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 665 ret <8 x half> %s 666} 667 668define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 669; CHECK-MVE-LABEL: vcmp_ogt_v8f16: 670; CHECK-MVE: @ %bb.0: @ %entry 671; CHECK-MVE-NEXT: vmovx.f16 s12, s0 672; CHECK-MVE-NEXT: vmovx.f16 s14, s8 673; CHECK-MVE-NEXT: vcmp.f16 s12, #0 674; CHECK-MVE-NEXT: vmovx.f16 s12, s4 675; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 676; CHECK-MVE-NEXT: vcmp.f16 s0, #0 677; CHECK-MVE-NEXT: cset r0, gt 678; CHECK-MVE-NEXT: cmp r0, #0 679; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 680; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 681; CHECK-MVE-NEXT: cset r0, gt 682; CHECK-MVE-NEXT: cmp r0, #0 683; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 684; CHECK-MVE-NEXT: vmovx.f16 s4, s1 685; CHECK-MVE-NEXT: vcmp.f16 s4, #0 686; CHECK-MVE-NEXT: vmovx.f16 s4, s5 687; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 688; CHECK-MVE-NEXT: vmovx.f16 s8, s9 689; CHECK-MVE-NEXT: vcmp.f16 s1, #0 690; CHECK-MVE-NEXT: vins.f16 s0, s12 691; CHECK-MVE-NEXT: cset r0, gt 692; CHECK-MVE-NEXT: cmp r0, #0 693; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 694; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 695; CHECK-MVE-NEXT: vmovx.f16 s8, s10 696; CHECK-MVE-NEXT: cset r0, gt 697; CHECK-MVE-NEXT: cmp r0, #0 698; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 699; CHECK-MVE-NEXT: vins.f16 s1, s4 700; CHECK-MVE-NEXT: vmovx.f16 s4, s2 701; CHECK-MVE-NEXT: vcmp.f16 s4, #0 702; CHECK-MVE-NEXT: vmovx.f16 s4, s6 703; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 704; CHECK-MVE-NEXT: vcmp.f16 s2, #0 705; CHECK-MVE-NEXT: cset r0, gt 706; CHECK-MVE-NEXT: cmp r0, #0 707; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 708; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 709; CHECK-MVE-NEXT: cset r0, gt 710; CHECK-MVE-NEXT: cmp r0, #0 711; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 712; CHECK-MVE-NEXT: vmovx.f16 s6, s11 713; CHECK-MVE-NEXT: vins.f16 s2, s4 714; CHECK-MVE-NEXT: vmovx.f16 s4, s3 715; CHECK-MVE-NEXT: vcmp.f16 s4, #0 716; CHECK-MVE-NEXT: vmovx.f16 s4, s7 717; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 718; CHECK-MVE-NEXT: vcmp.f16 s3, #0 719; CHECK-MVE-NEXT: cset r0, gt 720; CHECK-MVE-NEXT: cmp r0, #0 721; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 722; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 723; CHECK-MVE-NEXT: cset r0, gt 724; CHECK-MVE-NEXT: cmp r0, #0 725; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 726; CHECK-MVE-NEXT: vins.f16 s3, s4 727; CHECK-MVE-NEXT: bx lr 728; 729; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16: 730; CHECK-MVEFP: @ %bb.0: @ %entry 731; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr 732; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 733; CHECK-MVEFP-NEXT: bx lr 734entry: 735 %c = fcmp ogt <8 x half> %src, zeroinitializer 736 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 737 ret <8 x half> %s 738} 739 740define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 741; CHECK-MVE-LABEL: vcmp_oge_v8f16: 742; CHECK-MVE: @ %bb.0: @ %entry 743; CHECK-MVE-NEXT: vmovx.f16 s12, s0 744; CHECK-MVE-NEXT: vmovx.f16 s14, s8 745; CHECK-MVE-NEXT: vcmp.f16 s12, #0 746; CHECK-MVE-NEXT: vmovx.f16 s12, s4 747; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 748; CHECK-MVE-NEXT: vcmp.f16 s0, #0 749; CHECK-MVE-NEXT: cset r0, ge 750; CHECK-MVE-NEXT: cmp r0, #0 751; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 752; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 753; CHECK-MVE-NEXT: cset r0, ge 754; CHECK-MVE-NEXT: cmp r0, #0 755; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 756; CHECK-MVE-NEXT: vmovx.f16 s4, s1 757; CHECK-MVE-NEXT: vcmp.f16 s4, #0 758; CHECK-MVE-NEXT: vmovx.f16 s4, s5 759; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 760; CHECK-MVE-NEXT: vmovx.f16 s8, s9 761; CHECK-MVE-NEXT: vcmp.f16 s1, #0 762; CHECK-MVE-NEXT: vins.f16 s0, s12 763; CHECK-MVE-NEXT: cset r0, ge 764; CHECK-MVE-NEXT: cmp r0, #0 765; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 766; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 767; CHECK-MVE-NEXT: vmovx.f16 s8, s10 768; CHECK-MVE-NEXT: cset r0, ge 769; CHECK-MVE-NEXT: cmp r0, #0 770; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 771; CHECK-MVE-NEXT: vins.f16 s1, s4 772; CHECK-MVE-NEXT: vmovx.f16 s4, s2 773; CHECK-MVE-NEXT: vcmp.f16 s4, #0 774; CHECK-MVE-NEXT: vmovx.f16 s4, s6 775; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 776; CHECK-MVE-NEXT: vcmp.f16 s2, #0 777; CHECK-MVE-NEXT: cset r0, ge 778; CHECK-MVE-NEXT: cmp r0, #0 779; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 780; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 781; CHECK-MVE-NEXT: cset r0, ge 782; CHECK-MVE-NEXT: cmp r0, #0 783; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 784; CHECK-MVE-NEXT: vmovx.f16 s6, s11 785; CHECK-MVE-NEXT: vins.f16 s2, s4 786; CHECK-MVE-NEXT: vmovx.f16 s4, s3 787; CHECK-MVE-NEXT: vcmp.f16 s4, #0 788; CHECK-MVE-NEXT: vmovx.f16 s4, s7 789; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 790; CHECK-MVE-NEXT: vcmp.f16 s3, #0 791; CHECK-MVE-NEXT: cset r0, ge 792; CHECK-MVE-NEXT: cmp r0, #0 793; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 794; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 795; CHECK-MVE-NEXT: cset r0, ge 796; CHECK-MVE-NEXT: cmp r0, #0 797; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 798; CHECK-MVE-NEXT: vins.f16 s3, s4 799; CHECK-MVE-NEXT: bx lr 800; 801; CHECK-MVEFP-LABEL: vcmp_oge_v8f16: 802; CHECK-MVEFP: @ %bb.0: @ %entry 803; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr 804; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 805; CHECK-MVEFP-NEXT: bx lr 806entry: 807 %c = fcmp oge <8 x half> %src, zeroinitializer 808 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 809 ret <8 x half> %s 810} 811 812define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 813; CHECK-MVE-LABEL: vcmp_olt_v8f16: 814; CHECK-MVE: @ %bb.0: @ %entry 815; CHECK-MVE-NEXT: vmovx.f16 s12, s0 816; CHECK-MVE-NEXT: vmovx.f16 s14, s8 817; CHECK-MVE-NEXT: vcmp.f16 s12, #0 818; CHECK-MVE-NEXT: vmovx.f16 s12, s4 819; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 820; CHECK-MVE-NEXT: vcmp.f16 s0, #0 821; CHECK-MVE-NEXT: cset r0, mi 822; CHECK-MVE-NEXT: cmp r0, #0 823; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 824; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 825; CHECK-MVE-NEXT: cset r0, mi 826; CHECK-MVE-NEXT: cmp r0, #0 827; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 828; CHECK-MVE-NEXT: vmovx.f16 s4, s1 829; CHECK-MVE-NEXT: vcmp.f16 s4, #0 830; CHECK-MVE-NEXT: vmovx.f16 s4, s5 831; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 832; CHECK-MVE-NEXT: vmovx.f16 s8, s9 833; CHECK-MVE-NEXT: vcmp.f16 s1, #0 834; CHECK-MVE-NEXT: vins.f16 s0, s12 835; CHECK-MVE-NEXT: cset r0, mi 836; CHECK-MVE-NEXT: cmp r0, #0 837; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 838; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 839; CHECK-MVE-NEXT: vmovx.f16 s8, s10 840; CHECK-MVE-NEXT: cset r0, mi 841; CHECK-MVE-NEXT: cmp r0, #0 842; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 843; CHECK-MVE-NEXT: vins.f16 s1, s4 844; CHECK-MVE-NEXT: vmovx.f16 s4, s2 845; CHECK-MVE-NEXT: vcmp.f16 s4, #0 846; CHECK-MVE-NEXT: vmovx.f16 s4, s6 847; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 848; CHECK-MVE-NEXT: vcmp.f16 s2, #0 849; CHECK-MVE-NEXT: cset r0, mi 850; CHECK-MVE-NEXT: cmp r0, #0 851; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 852; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 853; CHECK-MVE-NEXT: cset r0, mi 854; CHECK-MVE-NEXT: cmp r0, #0 855; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 856; CHECK-MVE-NEXT: vmovx.f16 s6, s11 857; CHECK-MVE-NEXT: vins.f16 s2, s4 858; CHECK-MVE-NEXT: vmovx.f16 s4, s3 859; CHECK-MVE-NEXT: vcmp.f16 s4, #0 860; CHECK-MVE-NEXT: vmovx.f16 s4, s7 861; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 862; CHECK-MVE-NEXT: vcmp.f16 s3, #0 863; CHECK-MVE-NEXT: cset r0, mi 864; CHECK-MVE-NEXT: cmp r0, #0 865; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 866; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 867; CHECK-MVE-NEXT: cset r0, mi 868; CHECK-MVE-NEXT: cmp r0, #0 869; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 870; CHECK-MVE-NEXT: vins.f16 s3, s4 871; CHECK-MVE-NEXT: bx lr 872; 873; CHECK-MVEFP-LABEL: vcmp_olt_v8f16: 874; CHECK-MVEFP: @ %bb.0: @ %entry 875; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr 876; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 877; CHECK-MVEFP-NEXT: bx lr 878entry: 879 %c = fcmp olt <8 x half> %src, zeroinitializer 880 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 881 ret <8 x half> %s 882} 883 884define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 885; CHECK-MVE-LABEL: vcmp_ole_v8f16: 886; CHECK-MVE: @ %bb.0: @ %entry 887; CHECK-MVE-NEXT: vmovx.f16 s12, s0 888; CHECK-MVE-NEXT: vmovx.f16 s14, s8 889; CHECK-MVE-NEXT: vcmp.f16 s12, #0 890; CHECK-MVE-NEXT: vmovx.f16 s12, s4 891; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 892; CHECK-MVE-NEXT: vcmp.f16 s0, #0 893; CHECK-MVE-NEXT: cset r0, ls 894; CHECK-MVE-NEXT: cmp r0, #0 895; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 896; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 897; CHECK-MVE-NEXT: cset r0, ls 898; CHECK-MVE-NEXT: cmp r0, #0 899; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 900; CHECK-MVE-NEXT: vmovx.f16 s4, s1 901; CHECK-MVE-NEXT: vcmp.f16 s4, #0 902; CHECK-MVE-NEXT: vmovx.f16 s4, s5 903; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 904; CHECK-MVE-NEXT: vmovx.f16 s8, s9 905; CHECK-MVE-NEXT: vcmp.f16 s1, #0 906; CHECK-MVE-NEXT: vins.f16 s0, s12 907; CHECK-MVE-NEXT: cset r0, ls 908; CHECK-MVE-NEXT: cmp r0, #0 909; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 910; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 911; CHECK-MVE-NEXT: vmovx.f16 s8, s10 912; CHECK-MVE-NEXT: cset r0, ls 913; CHECK-MVE-NEXT: cmp r0, #0 914; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 915; CHECK-MVE-NEXT: vins.f16 s1, s4 916; CHECK-MVE-NEXT: vmovx.f16 s4, s2 917; CHECK-MVE-NEXT: vcmp.f16 s4, #0 918; CHECK-MVE-NEXT: vmovx.f16 s4, s6 919; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 920; CHECK-MVE-NEXT: vcmp.f16 s2, #0 921; CHECK-MVE-NEXT: cset r0, ls 922; CHECK-MVE-NEXT: cmp r0, #0 923; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 924; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 925; CHECK-MVE-NEXT: cset r0, ls 926; CHECK-MVE-NEXT: cmp r0, #0 927; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 928; CHECK-MVE-NEXT: vmovx.f16 s6, s11 929; CHECK-MVE-NEXT: vins.f16 s2, s4 930; CHECK-MVE-NEXT: vmovx.f16 s4, s3 931; CHECK-MVE-NEXT: vcmp.f16 s4, #0 932; CHECK-MVE-NEXT: vmovx.f16 s4, s7 933; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 934; CHECK-MVE-NEXT: vcmp.f16 s3, #0 935; CHECK-MVE-NEXT: cset r0, ls 936; CHECK-MVE-NEXT: cmp r0, #0 937; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 938; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 939; CHECK-MVE-NEXT: cset r0, ls 940; CHECK-MVE-NEXT: cmp r0, #0 941; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 942; CHECK-MVE-NEXT: vins.f16 s3, s4 943; CHECK-MVE-NEXT: bx lr 944; 945; CHECK-MVEFP-LABEL: vcmp_ole_v8f16: 946; CHECK-MVEFP: @ %bb.0: @ %entry 947; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr 948; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 949; CHECK-MVEFP-NEXT: bx lr 950entry: 951 %c = fcmp ole <8 x half> %src, zeroinitializer 952 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 953 ret <8 x half> %s 954} 955 956define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 957; CHECK-MVE-LABEL: vcmp_ueq_v8f16: 958; CHECK-MVE: @ %bb.0: @ %entry 959; CHECK-MVE-NEXT: vmovx.f16 s12, s0 960; CHECK-MVE-NEXT: vmovx.f16 s14, s8 961; CHECK-MVE-NEXT: vcmp.f16 s12, #0 962; CHECK-MVE-NEXT: vmovx.f16 s12, s4 963; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 964; CHECK-MVE-NEXT: vcmp.f16 s0, #0 965; CHECK-MVE-NEXT: cset r0, eq 966; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 967; CHECK-MVE-NEXT: cmp r0, #0 968; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 969; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 970; CHECK-MVE-NEXT: cset r0, eq 971; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 972; CHECK-MVE-NEXT: cmp r0, #0 973; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 974; CHECK-MVE-NEXT: vmovx.f16 s4, s1 975; CHECK-MVE-NEXT: vcmp.f16 s4, #0 976; CHECK-MVE-NEXT: vmovx.f16 s4, s5 977; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 978; CHECK-MVE-NEXT: vmovx.f16 s8, s9 979; CHECK-MVE-NEXT: vcmp.f16 s1, #0 980; CHECK-MVE-NEXT: vins.f16 s0, s12 981; CHECK-MVE-NEXT: cset r0, eq 982; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 983; CHECK-MVE-NEXT: cmp r0, #0 984; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 985; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 986; CHECK-MVE-NEXT: vmovx.f16 s8, s10 987; CHECK-MVE-NEXT: cset r0, eq 988; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 989; CHECK-MVE-NEXT: cmp r0, #0 990; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 991; CHECK-MVE-NEXT: vins.f16 s1, s4 992; CHECK-MVE-NEXT: vmovx.f16 s4, s2 993; CHECK-MVE-NEXT: vcmp.f16 s4, #0 994; CHECK-MVE-NEXT: vmovx.f16 s4, s6 995; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 996; CHECK-MVE-NEXT: vcmp.f16 s2, #0 997; CHECK-MVE-NEXT: cset r0, eq 998; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 999; CHECK-MVE-NEXT: cmp r0, #0 1000; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 1001; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1002; CHECK-MVE-NEXT: cset r0, eq 1003; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 1004; CHECK-MVE-NEXT: cmp r0, #0 1005; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 1006; CHECK-MVE-NEXT: vmovx.f16 s6, s11 1007; CHECK-MVE-NEXT: vins.f16 s2, s4 1008; CHECK-MVE-NEXT: vmovx.f16 s4, s3 1009; CHECK-MVE-NEXT: vcmp.f16 s4, #0 1010; CHECK-MVE-NEXT: vmovx.f16 s4, s7 1011; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1012; CHECK-MVE-NEXT: vcmp.f16 s3, #0 1013; CHECK-MVE-NEXT: cset r0, eq 1014; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 1015; CHECK-MVE-NEXT: cmp r0, #0 1016; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 1017; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1018; CHECK-MVE-NEXT: cset r0, eq 1019; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 1020; CHECK-MVE-NEXT: cmp r0, #0 1021; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 1022; CHECK-MVE-NEXT: vins.f16 s3, s4 1023; CHECK-MVE-NEXT: bx lr 1024; 1025; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16: 1026; CHECK-MVEFP: @ %bb.0: @ %entry 1027; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr 1028; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr 1029; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1030; CHECK-MVEFP-NEXT: bx lr 1031entry: 1032 %c = fcmp ueq <8 x half> %src, zeroinitializer 1033 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 1034 ret <8 x half> %s 1035} 1036 1037define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 1038; CHECK-MVE-LABEL: vcmp_une_v8f16: 1039; CHECK-MVE: @ %bb.0: @ %entry 1040; CHECK-MVE-NEXT: vmovx.f16 s12, s0 1041; CHECK-MVE-NEXT: vmovx.f16 s14, s8 1042; CHECK-MVE-NEXT: vcmp.f16 s12, #0 1043; CHECK-MVE-NEXT: vmovx.f16 s12, s4 1044; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1045; CHECK-MVE-NEXT: vcmp.f16 s0, #0 1046; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 1047; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1048; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 1049; CHECK-MVE-NEXT: vmovx.f16 s4, s1 1050; CHECK-MVE-NEXT: vcmp.f16 s4, #0 1051; CHECK-MVE-NEXT: vmovx.f16 s4, s5 1052; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1053; CHECK-MVE-NEXT: vmovx.f16 s8, s9 1054; CHECK-MVE-NEXT: vcmp.f16 s1, #0 1055; CHECK-MVE-NEXT: vins.f16 s0, s12 1056; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 1057; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1058; CHECK-MVE-NEXT: vmovx.f16 s8, s10 1059; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 1060; CHECK-MVE-NEXT: vins.f16 s1, s4 1061; CHECK-MVE-NEXT: vmovx.f16 s4, s2 1062; CHECK-MVE-NEXT: vcmp.f16 s4, #0 1063; CHECK-MVE-NEXT: vmovx.f16 s4, s6 1064; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1065; CHECK-MVE-NEXT: vcmp.f16 s2, #0 1066; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 1067; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1068; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 1069; CHECK-MVE-NEXT: vmovx.f16 s6, s11 1070; CHECK-MVE-NEXT: vins.f16 s2, s4 1071; CHECK-MVE-NEXT: vmovx.f16 s4, s3 1072; CHECK-MVE-NEXT: vcmp.f16 s4, #0 1073; CHECK-MVE-NEXT: vmovx.f16 s4, s7 1074; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1075; CHECK-MVE-NEXT: vcmp.f16 s3, #0 1076; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 1077; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1078; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 1079; CHECK-MVE-NEXT: vins.f16 s3, s4 1080; CHECK-MVE-NEXT: bx lr 1081; 1082; CHECK-MVEFP-LABEL: vcmp_une_v8f16: 1083; CHECK-MVEFP: @ %bb.0: @ %entry 1084; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr 1085; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1086; CHECK-MVEFP-NEXT: bx lr 1087entry: 1088 %c = fcmp une <8 x half> %src, zeroinitializer 1089 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 1090 ret <8 x half> %s 1091} 1092 1093define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 1094; CHECK-MVE-LABEL: vcmp_ugt_v8f16: 1095; CHECK-MVE: @ %bb.0: @ %entry 1096; CHECK-MVE-NEXT: vmovx.f16 s12, s0 1097; CHECK-MVE-NEXT: vmovx.f16 s14, s8 1098; CHECK-MVE-NEXT: vcmp.f16 s12, #0 1099; CHECK-MVE-NEXT: vmovx.f16 s12, s4 1100; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1101; CHECK-MVE-NEXT: vcmp.f16 s0, #0 1102; CHECK-MVE-NEXT: cset r0, hi 1103; CHECK-MVE-NEXT: cmp r0, #0 1104; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 1105; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1106; CHECK-MVE-NEXT: cset r0, hi 1107; CHECK-MVE-NEXT: cmp r0, #0 1108; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 1109; CHECK-MVE-NEXT: vmovx.f16 s4, s1 1110; CHECK-MVE-NEXT: vcmp.f16 s4, #0 1111; CHECK-MVE-NEXT: vmovx.f16 s4, s5 1112; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1113; CHECK-MVE-NEXT: vmovx.f16 s8, s9 1114; CHECK-MVE-NEXT: vcmp.f16 s1, #0 1115; CHECK-MVE-NEXT: vins.f16 s0, s12 1116; CHECK-MVE-NEXT: cset r0, hi 1117; CHECK-MVE-NEXT: cmp r0, #0 1118; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 1119; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1120; CHECK-MVE-NEXT: vmovx.f16 s8, s10 1121; CHECK-MVE-NEXT: cset r0, hi 1122; CHECK-MVE-NEXT: cmp r0, #0 1123; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 1124; CHECK-MVE-NEXT: vins.f16 s1, s4 1125; CHECK-MVE-NEXT: vmovx.f16 s4, s2 1126; CHECK-MVE-NEXT: vcmp.f16 s4, #0 1127; CHECK-MVE-NEXT: vmovx.f16 s4, s6 1128; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1129; CHECK-MVE-NEXT: vcmp.f16 s2, #0 1130; CHECK-MVE-NEXT: cset r0, hi 1131; CHECK-MVE-NEXT: cmp r0, #0 1132; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 1133; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1134; CHECK-MVE-NEXT: cset r0, hi 1135; CHECK-MVE-NEXT: cmp r0, #0 1136; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 1137; CHECK-MVE-NEXT: vmovx.f16 s6, s11 1138; CHECK-MVE-NEXT: vins.f16 s2, s4 1139; CHECK-MVE-NEXT: vmovx.f16 s4, s3 1140; CHECK-MVE-NEXT: vcmp.f16 s4, #0 1141; CHECK-MVE-NEXT: vmovx.f16 s4, s7 1142; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1143; CHECK-MVE-NEXT: vcmp.f16 s3, #0 1144; CHECK-MVE-NEXT: cset r0, hi 1145; CHECK-MVE-NEXT: cmp r0, #0 1146; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 1147; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1148; CHECK-MVE-NEXT: cset r0, hi 1149; CHECK-MVE-NEXT: cmp r0, #0 1150; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 1151; CHECK-MVE-NEXT: vins.f16 s3, s4 1152; CHECK-MVE-NEXT: bx lr 1153; 1154; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16: 1155; CHECK-MVEFP: @ %bb.0: @ %entry 1156; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr 1157; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1158; CHECK-MVEFP-NEXT: bx lr 1159entry: 1160 %c = fcmp ugt <8 x half> %src, zeroinitializer 1161 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 1162 ret <8 x half> %s 1163} 1164 1165define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 1166; CHECK-MVE-LABEL: vcmp_uge_v8f16: 1167; CHECK-MVE: @ %bb.0: @ %entry 1168; CHECK-MVE-NEXT: vmovx.f16 s12, s0 1169; CHECK-MVE-NEXT: vmovx.f16 s14, s8 1170; CHECK-MVE-NEXT: vcmp.f16 s12, #0 1171; CHECK-MVE-NEXT: vmovx.f16 s12, s4 1172; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1173; CHECK-MVE-NEXT: vcmp.f16 s0, #0 1174; CHECK-MVE-NEXT: cset r0, pl 1175; CHECK-MVE-NEXT: cmp r0, #0 1176; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 1177; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1178; CHECK-MVE-NEXT: cset r0, pl 1179; CHECK-MVE-NEXT: cmp r0, #0 1180; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 1181; CHECK-MVE-NEXT: vmovx.f16 s4, s1 1182; CHECK-MVE-NEXT: vcmp.f16 s4, #0 1183; CHECK-MVE-NEXT: vmovx.f16 s4, s5 1184; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1185; CHECK-MVE-NEXT: vmovx.f16 s8, s9 1186; CHECK-MVE-NEXT: vcmp.f16 s1, #0 1187; CHECK-MVE-NEXT: vins.f16 s0, s12 1188; CHECK-MVE-NEXT: cset r0, pl 1189; CHECK-MVE-NEXT: cmp r0, #0 1190; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 1191; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1192; CHECK-MVE-NEXT: vmovx.f16 s8, s10 1193; CHECK-MVE-NEXT: cset r0, pl 1194; CHECK-MVE-NEXT: cmp r0, #0 1195; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 1196; CHECK-MVE-NEXT: vins.f16 s1, s4 1197; CHECK-MVE-NEXT: vmovx.f16 s4, s2 1198; CHECK-MVE-NEXT: vcmp.f16 s4, #0 1199; CHECK-MVE-NEXT: vmovx.f16 s4, s6 1200; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1201; CHECK-MVE-NEXT: vcmp.f16 s2, #0 1202; CHECK-MVE-NEXT: cset r0, pl 1203; CHECK-MVE-NEXT: cmp r0, #0 1204; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 1205; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1206; CHECK-MVE-NEXT: cset r0, pl 1207; CHECK-MVE-NEXT: cmp r0, #0 1208; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 1209; CHECK-MVE-NEXT: vmovx.f16 s6, s11 1210; CHECK-MVE-NEXT: vins.f16 s2, s4 1211; CHECK-MVE-NEXT: vmovx.f16 s4, s3 1212; CHECK-MVE-NEXT: vcmp.f16 s4, #0 1213; CHECK-MVE-NEXT: vmovx.f16 s4, s7 1214; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1215; CHECK-MVE-NEXT: vcmp.f16 s3, #0 1216; CHECK-MVE-NEXT: cset r0, pl 1217; CHECK-MVE-NEXT: cmp r0, #0 1218; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 1219; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1220; CHECK-MVE-NEXT: cset r0, pl 1221; CHECK-MVE-NEXT: cmp r0, #0 1222; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 1223; CHECK-MVE-NEXT: vins.f16 s3, s4 1224; CHECK-MVE-NEXT: bx lr 1225; 1226; CHECK-MVEFP-LABEL: vcmp_uge_v8f16: 1227; CHECK-MVEFP: @ %bb.0: @ %entry 1228; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr 1229; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1230; CHECK-MVEFP-NEXT: bx lr 1231entry: 1232 %c = fcmp uge <8 x half> %src, zeroinitializer 1233 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 1234 ret <8 x half> %s 1235} 1236 1237define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 1238; CHECK-MVE-LABEL: vcmp_ult_v8f16: 1239; CHECK-MVE: @ %bb.0: @ %entry 1240; CHECK-MVE-NEXT: vmovx.f16 s12, s0 1241; CHECK-MVE-NEXT: vmovx.f16 s14, s8 1242; CHECK-MVE-NEXT: vcmp.f16 s12, #0 1243; CHECK-MVE-NEXT: vmovx.f16 s12, s4 1244; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1245; CHECK-MVE-NEXT: vcmp.f16 s0, #0 1246; CHECK-MVE-NEXT: cset r0, lt 1247; CHECK-MVE-NEXT: cmp r0, #0 1248; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 1249; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1250; CHECK-MVE-NEXT: cset r0, lt 1251; CHECK-MVE-NEXT: cmp r0, #0 1252; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 1253; CHECK-MVE-NEXT: vmovx.f16 s4, s1 1254; CHECK-MVE-NEXT: vcmp.f16 s4, #0 1255; CHECK-MVE-NEXT: vmovx.f16 s4, s5 1256; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1257; CHECK-MVE-NEXT: vmovx.f16 s8, s9 1258; CHECK-MVE-NEXT: vcmp.f16 s1, #0 1259; CHECK-MVE-NEXT: vins.f16 s0, s12 1260; CHECK-MVE-NEXT: cset r0, lt 1261; CHECK-MVE-NEXT: cmp r0, #0 1262; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 1263; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1264; CHECK-MVE-NEXT: vmovx.f16 s8, s10 1265; CHECK-MVE-NEXT: cset r0, lt 1266; CHECK-MVE-NEXT: cmp r0, #0 1267; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 1268; CHECK-MVE-NEXT: vins.f16 s1, s4 1269; CHECK-MVE-NEXT: vmovx.f16 s4, s2 1270; CHECK-MVE-NEXT: vcmp.f16 s4, #0 1271; CHECK-MVE-NEXT: vmovx.f16 s4, s6 1272; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1273; CHECK-MVE-NEXT: vcmp.f16 s2, #0 1274; CHECK-MVE-NEXT: cset r0, lt 1275; CHECK-MVE-NEXT: cmp r0, #0 1276; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 1277; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1278; CHECK-MVE-NEXT: cset r0, lt 1279; CHECK-MVE-NEXT: cmp r0, #0 1280; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 1281; CHECK-MVE-NEXT: vmovx.f16 s6, s11 1282; CHECK-MVE-NEXT: vins.f16 s2, s4 1283; CHECK-MVE-NEXT: vmovx.f16 s4, s3 1284; CHECK-MVE-NEXT: vcmp.f16 s4, #0 1285; CHECK-MVE-NEXT: vmovx.f16 s4, s7 1286; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1287; CHECK-MVE-NEXT: vcmp.f16 s3, #0 1288; CHECK-MVE-NEXT: cset r0, lt 1289; CHECK-MVE-NEXT: cmp r0, #0 1290; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 1291; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1292; CHECK-MVE-NEXT: cset r0, lt 1293; CHECK-MVE-NEXT: cmp r0, #0 1294; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 1295; CHECK-MVE-NEXT: vins.f16 s3, s4 1296; CHECK-MVE-NEXT: bx lr 1297; 1298; CHECK-MVEFP-LABEL: vcmp_ult_v8f16: 1299; CHECK-MVEFP: @ %bb.0: @ %entry 1300; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr 1301; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1302; CHECK-MVEFP-NEXT: bx lr 1303entry: 1304 %c = fcmp ult <8 x half> %src, zeroinitializer 1305 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 1306 ret <8 x half> %s 1307} 1308 1309define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 1310; CHECK-MVE-LABEL: vcmp_ule_v8f16: 1311; CHECK-MVE: @ %bb.0: @ %entry 1312; CHECK-MVE-NEXT: vmovx.f16 s12, s0 1313; CHECK-MVE-NEXT: vmovx.f16 s14, s8 1314; CHECK-MVE-NEXT: vcmp.f16 s12, #0 1315; CHECK-MVE-NEXT: vmovx.f16 s12, s4 1316; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1317; CHECK-MVE-NEXT: vcmp.f16 s0, #0 1318; CHECK-MVE-NEXT: cset r0, le 1319; CHECK-MVE-NEXT: cmp r0, #0 1320; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 1321; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1322; CHECK-MVE-NEXT: cset r0, le 1323; CHECK-MVE-NEXT: cmp r0, #0 1324; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 1325; CHECK-MVE-NEXT: vmovx.f16 s4, s1 1326; CHECK-MVE-NEXT: vcmp.f16 s4, #0 1327; CHECK-MVE-NEXT: vmovx.f16 s4, s5 1328; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1329; CHECK-MVE-NEXT: vmovx.f16 s8, s9 1330; CHECK-MVE-NEXT: vcmp.f16 s1, #0 1331; CHECK-MVE-NEXT: vins.f16 s0, s12 1332; CHECK-MVE-NEXT: cset r0, le 1333; CHECK-MVE-NEXT: cmp r0, #0 1334; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 1335; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1336; CHECK-MVE-NEXT: vmovx.f16 s8, s10 1337; CHECK-MVE-NEXT: cset r0, le 1338; CHECK-MVE-NEXT: cmp r0, #0 1339; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 1340; CHECK-MVE-NEXT: vins.f16 s1, s4 1341; CHECK-MVE-NEXT: vmovx.f16 s4, s2 1342; CHECK-MVE-NEXT: vcmp.f16 s4, #0 1343; CHECK-MVE-NEXT: vmovx.f16 s4, s6 1344; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1345; CHECK-MVE-NEXT: vcmp.f16 s2, #0 1346; CHECK-MVE-NEXT: cset r0, le 1347; CHECK-MVE-NEXT: cmp r0, #0 1348; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 1349; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1350; CHECK-MVE-NEXT: cset r0, le 1351; CHECK-MVE-NEXT: cmp r0, #0 1352; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 1353; CHECK-MVE-NEXT: vmovx.f16 s6, s11 1354; CHECK-MVE-NEXT: vins.f16 s2, s4 1355; CHECK-MVE-NEXT: vmovx.f16 s4, s3 1356; CHECK-MVE-NEXT: vcmp.f16 s4, #0 1357; CHECK-MVE-NEXT: vmovx.f16 s4, s7 1358; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1359; CHECK-MVE-NEXT: vcmp.f16 s3, #0 1360; CHECK-MVE-NEXT: cset r0, le 1361; CHECK-MVE-NEXT: cmp r0, #0 1362; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 1363; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1364; CHECK-MVE-NEXT: cset r0, le 1365; CHECK-MVE-NEXT: cmp r0, #0 1366; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 1367; CHECK-MVE-NEXT: vins.f16 s3, s4 1368; CHECK-MVE-NEXT: bx lr 1369; 1370; CHECK-MVEFP-LABEL: vcmp_ule_v8f16: 1371; CHECK-MVEFP: @ %bb.0: @ %entry 1372; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr 1373; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1374; CHECK-MVEFP-NEXT: bx lr 1375entry: 1376 %c = fcmp ule <8 x half> %src, zeroinitializer 1377 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 1378 ret <8 x half> %s 1379} 1380 1381define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 1382; CHECK-MVE-LABEL: vcmp_ord_v8f16: 1383; CHECK-MVE: @ %bb.0: @ %entry 1384; CHECK-MVE-NEXT: vmovx.f16 s12, s0 1385; CHECK-MVE-NEXT: vmovx.f16 s14, s8 1386; CHECK-MVE-NEXT: vcmp.f16 s12, s12 1387; CHECK-MVE-NEXT: vmovx.f16 s12, s4 1388; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1389; CHECK-MVE-NEXT: vcmp.f16 s0, s0 1390; CHECK-MVE-NEXT: cset r0, vc 1391; CHECK-MVE-NEXT: cmp r0, #0 1392; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 1393; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1394; CHECK-MVE-NEXT: cset r0, vc 1395; CHECK-MVE-NEXT: cmp r0, #0 1396; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 1397; CHECK-MVE-NEXT: vmovx.f16 s4, s1 1398; CHECK-MVE-NEXT: vcmp.f16 s4, s4 1399; CHECK-MVE-NEXT: vmovx.f16 s4, s5 1400; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1401; CHECK-MVE-NEXT: vmovx.f16 s8, s9 1402; CHECK-MVE-NEXT: vcmp.f16 s1, s1 1403; CHECK-MVE-NEXT: vins.f16 s0, s12 1404; CHECK-MVE-NEXT: cset r0, vc 1405; CHECK-MVE-NEXT: cmp r0, #0 1406; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 1407; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1408; CHECK-MVE-NEXT: vmovx.f16 s8, s10 1409; CHECK-MVE-NEXT: cset r0, vc 1410; CHECK-MVE-NEXT: cmp r0, #0 1411; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 1412; CHECK-MVE-NEXT: vins.f16 s1, s4 1413; CHECK-MVE-NEXT: vmovx.f16 s4, s2 1414; CHECK-MVE-NEXT: vcmp.f16 s4, s4 1415; CHECK-MVE-NEXT: vmovx.f16 s4, s6 1416; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1417; CHECK-MVE-NEXT: vcmp.f16 s2, s2 1418; CHECK-MVE-NEXT: cset r0, vc 1419; CHECK-MVE-NEXT: cmp r0, #0 1420; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 1421; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1422; CHECK-MVE-NEXT: cset r0, vc 1423; CHECK-MVE-NEXT: cmp r0, #0 1424; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 1425; CHECK-MVE-NEXT: vmovx.f16 s6, s11 1426; CHECK-MVE-NEXT: vins.f16 s2, s4 1427; CHECK-MVE-NEXT: vmovx.f16 s4, s3 1428; CHECK-MVE-NEXT: vcmp.f16 s4, s4 1429; CHECK-MVE-NEXT: vmovx.f16 s4, s7 1430; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1431; CHECK-MVE-NEXT: vcmp.f16 s3, s3 1432; CHECK-MVE-NEXT: cset r0, vc 1433; CHECK-MVE-NEXT: cmp r0, #0 1434; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 1435; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1436; CHECK-MVE-NEXT: cset r0, vc 1437; CHECK-MVE-NEXT: cmp r0, #0 1438; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 1439; CHECK-MVE-NEXT: vins.f16 s3, s4 1440; CHECK-MVE-NEXT: bx lr 1441; 1442; CHECK-MVEFP-LABEL: vcmp_ord_v8f16: 1443; CHECK-MVEFP: @ %bb.0: @ %entry 1444; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr 1445; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr 1446; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 1447; CHECK-MVEFP-NEXT: bx lr 1448entry: 1449 %c = fcmp ord <8 x half> %src, zeroinitializer 1450 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 1451 ret <8 x half> %s 1452} 1453 1454define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 1455; CHECK-MVE-LABEL: vcmp_uno_v8f16: 1456; CHECK-MVE: @ %bb.0: @ %entry 1457; CHECK-MVE-NEXT: vmovx.f16 s12, s0 1458; CHECK-MVE-NEXT: vmovx.f16 s14, s8 1459; CHECK-MVE-NEXT: vcmp.f16 s12, s12 1460; CHECK-MVE-NEXT: vmovx.f16 s12, s4 1461; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1462; CHECK-MVE-NEXT: vcmp.f16 s0, s0 1463; CHECK-MVE-NEXT: cset r0, vs 1464; CHECK-MVE-NEXT: cmp r0, #0 1465; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 1466; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1467; CHECK-MVE-NEXT: cset r0, vs 1468; CHECK-MVE-NEXT: cmp r0, #0 1469; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 1470; CHECK-MVE-NEXT: vmovx.f16 s4, s1 1471; CHECK-MVE-NEXT: vcmp.f16 s4, s4 1472; CHECK-MVE-NEXT: vmovx.f16 s4, s5 1473; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1474; CHECK-MVE-NEXT: vmovx.f16 s8, s9 1475; CHECK-MVE-NEXT: vcmp.f16 s1, s1 1476; CHECK-MVE-NEXT: vins.f16 s0, s12 1477; CHECK-MVE-NEXT: cset r0, vs 1478; CHECK-MVE-NEXT: cmp r0, #0 1479; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 1480; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1481; CHECK-MVE-NEXT: vmovx.f16 s8, s10 1482; CHECK-MVE-NEXT: cset r0, vs 1483; CHECK-MVE-NEXT: cmp r0, #0 1484; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 1485; CHECK-MVE-NEXT: vins.f16 s1, s4 1486; CHECK-MVE-NEXT: vmovx.f16 s4, s2 1487; CHECK-MVE-NEXT: vcmp.f16 s4, s4 1488; CHECK-MVE-NEXT: vmovx.f16 s4, s6 1489; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1490; CHECK-MVE-NEXT: vcmp.f16 s2, s2 1491; CHECK-MVE-NEXT: cset r0, vs 1492; CHECK-MVE-NEXT: cmp r0, #0 1493; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 1494; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1495; CHECK-MVE-NEXT: cset r0, vs 1496; CHECK-MVE-NEXT: cmp r0, #0 1497; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 1498; CHECK-MVE-NEXT: vmovx.f16 s6, s11 1499; CHECK-MVE-NEXT: vins.f16 s2, s4 1500; CHECK-MVE-NEXT: vmovx.f16 s4, s3 1501; CHECK-MVE-NEXT: vcmp.f16 s4, s4 1502; CHECK-MVE-NEXT: vmovx.f16 s4, s7 1503; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1504; CHECK-MVE-NEXT: vcmp.f16 s3, s3 1505; CHECK-MVE-NEXT: cset r0, vs 1506; CHECK-MVE-NEXT: cmp r0, #0 1507; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 1508; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1509; CHECK-MVE-NEXT: cset r0, vs 1510; CHECK-MVE-NEXT: cmp r0, #0 1511; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 1512; CHECK-MVE-NEXT: vins.f16 s3, s4 1513; CHECK-MVE-NEXT: bx lr 1514; 1515; CHECK-MVEFP-LABEL: vcmp_uno_v8f16: 1516; CHECK-MVEFP: @ %bb.0: @ %entry 1517; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr 1518; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr 1519; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1520; CHECK-MVEFP-NEXT: bx lr 1521entry: 1522 %c = fcmp uno <8 x half> %src, zeroinitializer 1523 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 1524 ret <8 x half> %s 1525} 1526 1527 1528; Reversed 1529 1530define arm_aapcs_vfpcc <4 x float> @vcmp_r_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 1531; CHECK-MVE-LABEL: vcmp_r_oeq_v4f32: 1532; CHECK-MVE: @ %bb.0: @ %entry 1533; CHECK-MVE-NEXT: vcmp.f32 s0, #0 1534; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1535; CHECK-MVE-NEXT: vcmp.f32 s3, #0 1536; CHECK-MVE-NEXT: cset r0, eq 1537; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1538; CHECK-MVE-NEXT: vcmp.f32 s1, #0 1539; CHECK-MVE-NEXT: cset r1, eq 1540; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1541; CHECK-MVE-NEXT: vcmp.f32 s2, #0 1542; CHECK-MVE-NEXT: cset r2, eq 1543; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1544; CHECK-MVE-NEXT: cset r3, eq 1545; CHECK-MVE-NEXT: cmp r3, #0 1546; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 1547; CHECK-MVE-NEXT: cmp r2, #0 1548; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 1549; CHECK-MVE-NEXT: cmp r1, #0 1550; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 1551; CHECK-MVE-NEXT: cmp r0, #0 1552; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 1553; CHECK-MVE-NEXT: bx lr 1554; 1555; CHECK-MVEFP-LABEL: vcmp_r_oeq_v4f32: 1556; CHECK-MVEFP: @ %bb.0: @ %entry 1557; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, zr 1558; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1559; CHECK-MVEFP-NEXT: bx lr 1560entry: 1561 %c = fcmp oeq <4 x float> zeroinitializer, %src 1562 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1563 ret <4 x float> %s 1564} 1565 1566define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 1567; CHECK-MVE-LABEL: vcmp_r_one_v4f32: 1568; CHECK-MVE: @ %bb.0: @ %entry 1569; CHECK-MVE-NEXT: vcmp.f32 s0, #0 1570; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1571; CHECK-MVE-NEXT: vcmp.f32 s3, #0 1572; CHECK-MVE-NEXT: cset r0, mi 1573; CHECK-MVE-NEXT: csinc r0, r0, zr, le 1574; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1575; CHECK-MVE-NEXT: vcmp.f32 s1, #0 1576; CHECK-MVE-NEXT: cset r1, mi 1577; CHECK-MVE-NEXT: csinc r1, r1, zr, le 1578; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1579; CHECK-MVE-NEXT: vcmp.f32 s2, #0 1580; CHECK-MVE-NEXT: cset r2, mi 1581; CHECK-MVE-NEXT: csinc r2, r2, zr, le 1582; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1583; CHECK-MVE-NEXT: cset r3, mi 1584; CHECK-MVE-NEXT: csinc r3, r3, zr, le 1585; CHECK-MVE-NEXT: cmp r3, #0 1586; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 1587; CHECK-MVE-NEXT: cmp r2, #0 1588; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 1589; CHECK-MVE-NEXT: cmp r1, #0 1590; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 1591; CHECK-MVE-NEXT: cmp r0, #0 1592; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 1593; CHECK-MVE-NEXT: bx lr 1594; 1595; CHECK-MVEFP-LABEL: vcmp_r_one_v4f32: 1596; CHECK-MVEFP: @ %bb.0: @ %entry 1597; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr 1598; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, zr 1599; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 1600; CHECK-MVEFP-NEXT: bx lr 1601entry: 1602 %c = fcmp one <4 x float> zeroinitializer, %src 1603 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1604 ret <4 x float> %s 1605} 1606 1607define arm_aapcs_vfpcc <4 x float> @vcmp_r_ogt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 1608; CHECK-MVE-LABEL: vcmp_r_ogt_v4f32: 1609; CHECK-MVE: @ %bb.0: @ %entry 1610; CHECK-MVE-NEXT: vcmp.f32 s0, #0 1611; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1612; CHECK-MVE-NEXT: vcmp.f32 s3, #0 1613; CHECK-MVE-NEXT: cset r0, mi 1614; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1615; CHECK-MVE-NEXT: vcmp.f32 s1, #0 1616; CHECK-MVE-NEXT: cset r1, mi 1617; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1618; CHECK-MVE-NEXT: vcmp.f32 s2, #0 1619; CHECK-MVE-NEXT: cset r2, mi 1620; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1621; CHECK-MVE-NEXT: cset r3, mi 1622; CHECK-MVE-NEXT: cmp r3, #0 1623; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 1624; CHECK-MVE-NEXT: cmp r2, #0 1625; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 1626; CHECK-MVE-NEXT: cmp r1, #0 1627; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 1628; CHECK-MVE-NEXT: cmp r0, #0 1629; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 1630; CHECK-MVE-NEXT: bx lr 1631; 1632; CHECK-MVEFP-LABEL: vcmp_r_ogt_v4f32: 1633; CHECK-MVEFP: @ %bb.0: @ %entry 1634; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr 1635; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1636; CHECK-MVEFP-NEXT: bx lr 1637entry: 1638 %c = fcmp ogt <4 x float> zeroinitializer, %src 1639 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1640 ret <4 x float> %s 1641} 1642 1643define arm_aapcs_vfpcc <4 x float> @vcmp_r_oge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 1644; CHECK-MVE-LABEL: vcmp_r_oge_v4f32: 1645; CHECK-MVE: @ %bb.0: @ %entry 1646; CHECK-MVE-NEXT: vcmp.f32 s0, #0 1647; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1648; CHECK-MVE-NEXT: vcmp.f32 s3, #0 1649; CHECK-MVE-NEXT: cset r0, ls 1650; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1651; CHECK-MVE-NEXT: vcmp.f32 s1, #0 1652; CHECK-MVE-NEXT: cset r1, ls 1653; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1654; CHECK-MVE-NEXT: vcmp.f32 s2, #0 1655; CHECK-MVE-NEXT: cset r2, ls 1656; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1657; CHECK-MVE-NEXT: cset r3, ls 1658; CHECK-MVE-NEXT: cmp r3, #0 1659; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 1660; CHECK-MVE-NEXT: cmp r2, #0 1661; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 1662; CHECK-MVE-NEXT: cmp r1, #0 1663; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 1664; CHECK-MVE-NEXT: cmp r0, #0 1665; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 1666; CHECK-MVE-NEXT: bx lr 1667; 1668; CHECK-MVEFP-LABEL: vcmp_r_oge_v4f32: 1669; CHECK-MVEFP: @ %bb.0: @ %entry 1670; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr 1671; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1672; CHECK-MVEFP-NEXT: bx lr 1673entry: 1674 %c = fcmp oge <4 x float> zeroinitializer, %src 1675 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1676 ret <4 x float> %s 1677} 1678 1679define arm_aapcs_vfpcc <4 x float> @vcmp_r_olt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 1680; CHECK-MVE-LABEL: vcmp_r_olt_v4f32: 1681; CHECK-MVE: @ %bb.0: @ %entry 1682; CHECK-MVE-NEXT: vcmp.f32 s0, #0 1683; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1684; CHECK-MVE-NEXT: vcmp.f32 s3, #0 1685; CHECK-MVE-NEXT: cset r0, gt 1686; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1687; CHECK-MVE-NEXT: vcmp.f32 s1, #0 1688; CHECK-MVE-NEXT: cset r1, gt 1689; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1690; CHECK-MVE-NEXT: vcmp.f32 s2, #0 1691; CHECK-MVE-NEXT: cset r2, gt 1692; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1693; CHECK-MVE-NEXT: cset r3, gt 1694; CHECK-MVE-NEXT: cmp r3, #0 1695; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 1696; CHECK-MVE-NEXT: cmp r2, #0 1697; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 1698; CHECK-MVE-NEXT: cmp r1, #0 1699; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 1700; CHECK-MVE-NEXT: cmp r0, #0 1701; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 1702; CHECK-MVE-NEXT: bx lr 1703; 1704; CHECK-MVEFP-LABEL: vcmp_r_olt_v4f32: 1705; CHECK-MVEFP: @ %bb.0: @ %entry 1706; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr 1707; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1708; CHECK-MVEFP-NEXT: bx lr 1709entry: 1710 %c = fcmp olt <4 x float> zeroinitializer, %src 1711 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1712 ret <4 x float> %s 1713} 1714 1715define arm_aapcs_vfpcc <4 x float> @vcmp_r_ole_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 1716; CHECK-MVE-LABEL: vcmp_r_ole_v4f32: 1717; CHECK-MVE: @ %bb.0: @ %entry 1718; CHECK-MVE-NEXT: vcmp.f32 s0, #0 1719; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1720; CHECK-MVE-NEXT: vcmp.f32 s3, #0 1721; CHECK-MVE-NEXT: cset r0, ge 1722; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1723; CHECK-MVE-NEXT: vcmp.f32 s1, #0 1724; CHECK-MVE-NEXT: cset r1, ge 1725; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1726; CHECK-MVE-NEXT: vcmp.f32 s2, #0 1727; CHECK-MVE-NEXT: cset r2, ge 1728; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1729; CHECK-MVE-NEXT: cset r3, ge 1730; CHECK-MVE-NEXT: cmp r3, #0 1731; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 1732; CHECK-MVE-NEXT: cmp r2, #0 1733; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 1734; CHECK-MVE-NEXT: cmp r1, #0 1735; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 1736; CHECK-MVE-NEXT: cmp r0, #0 1737; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 1738; CHECK-MVE-NEXT: bx lr 1739; 1740; CHECK-MVEFP-LABEL: vcmp_r_ole_v4f32: 1741; CHECK-MVEFP: @ %bb.0: @ %entry 1742; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr 1743; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1744; CHECK-MVEFP-NEXT: bx lr 1745entry: 1746 %c = fcmp ole <4 x float> zeroinitializer, %src 1747 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1748 ret <4 x float> %s 1749} 1750 1751define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 1752; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32: 1753; CHECK-MVE: @ %bb.0: @ %entry 1754; CHECK-MVE-NEXT: vcmp.f32 s0, #0 1755; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1756; CHECK-MVE-NEXT: vcmp.f32 s3, #0 1757; CHECK-MVE-NEXT: cset r0, eq 1758; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 1759; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1760; CHECK-MVE-NEXT: vcmp.f32 s1, #0 1761; CHECK-MVE-NEXT: cset r1, eq 1762; CHECK-MVE-NEXT: csinc r1, r1, zr, vc 1763; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1764; CHECK-MVE-NEXT: vcmp.f32 s2, #0 1765; CHECK-MVE-NEXT: cset r2, eq 1766; CHECK-MVE-NEXT: csinc r2, r2, zr, vc 1767; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1768; CHECK-MVE-NEXT: cset r3, eq 1769; CHECK-MVE-NEXT: csinc r3, r3, zr, vc 1770; CHECK-MVE-NEXT: cmp r3, #0 1771; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 1772; CHECK-MVE-NEXT: cmp r2, #0 1773; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 1774; CHECK-MVE-NEXT: cmp r1, #0 1775; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 1776; CHECK-MVE-NEXT: cmp r0, #0 1777; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 1778; CHECK-MVE-NEXT: bx lr 1779; 1780; CHECK-MVEFP-LABEL: vcmp_r_ueq_v4f32: 1781; CHECK-MVEFP: @ %bb.0: @ %entry 1782; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr 1783; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, zr 1784; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1785; CHECK-MVEFP-NEXT: bx lr 1786entry: 1787 %c = fcmp ueq <4 x float> zeroinitializer, %src 1788 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1789 ret <4 x float> %s 1790} 1791 1792define arm_aapcs_vfpcc <4 x float> @vcmp_r_une_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 1793; CHECK-MVE-LABEL: vcmp_r_une_v4f32: 1794; CHECK-MVE: @ %bb.0: @ %entry 1795; CHECK-MVE-NEXT: vcmp.f32 s2, #0 1796; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1797; CHECK-MVE-NEXT: vcmp.f32 s1, #0 1798; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 1799; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1800; CHECK-MVE-NEXT: vcmp.f32 s3, #0 1801; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 1802; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1803; CHECK-MVE-NEXT: vcmp.f32 s0, #0 1804; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 1805; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1806; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 1807; CHECK-MVE-NEXT: bx lr 1808; 1809; CHECK-MVEFP-LABEL: vcmp_r_une_v4f32: 1810; CHECK-MVEFP: @ %bb.0: @ %entry 1811; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, zr 1812; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1813; CHECK-MVEFP-NEXT: bx lr 1814entry: 1815 %c = fcmp une <4 x float> zeroinitializer, %src 1816 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1817 ret <4 x float> %s 1818} 1819 1820define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 1821; CHECK-MVE-LABEL: vcmp_r_ugt_v4f32: 1822; CHECK-MVE: @ %bb.0: @ %entry 1823; CHECK-MVE-NEXT: vcmp.f32 s0, #0 1824; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1825; CHECK-MVE-NEXT: vcmp.f32 s3, #0 1826; CHECK-MVE-NEXT: cset r0, lt 1827; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1828; CHECK-MVE-NEXT: vcmp.f32 s1, #0 1829; CHECK-MVE-NEXT: cset r1, lt 1830; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1831; CHECK-MVE-NEXT: vcmp.f32 s2, #0 1832; CHECK-MVE-NEXT: cset r2, lt 1833; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1834; CHECK-MVE-NEXT: cset r3, lt 1835; CHECK-MVE-NEXT: cmp r3, #0 1836; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 1837; CHECK-MVE-NEXT: cmp r2, #0 1838; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 1839; CHECK-MVE-NEXT: cmp r1, #0 1840; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 1841; CHECK-MVE-NEXT: cmp r0, #0 1842; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 1843; CHECK-MVE-NEXT: bx lr 1844; 1845; CHECK-MVEFP-LABEL: vcmp_r_ugt_v4f32: 1846; CHECK-MVEFP: @ %bb.0: @ %entry 1847; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr 1848; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1849; CHECK-MVEFP-NEXT: bx lr 1850entry: 1851 %c = fcmp ugt <4 x float> zeroinitializer, %src 1852 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1853 ret <4 x float> %s 1854} 1855 1856define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 1857; CHECK-MVE-LABEL: vcmp_r_uge_v4f32: 1858; CHECK-MVE: @ %bb.0: @ %entry 1859; CHECK-MVE-NEXT: vcmp.f32 s0, #0 1860; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1861; CHECK-MVE-NEXT: vcmp.f32 s3, #0 1862; CHECK-MVE-NEXT: cset r0, le 1863; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1864; CHECK-MVE-NEXT: vcmp.f32 s1, #0 1865; CHECK-MVE-NEXT: cset r1, le 1866; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1867; CHECK-MVE-NEXT: vcmp.f32 s2, #0 1868; CHECK-MVE-NEXT: cset r2, le 1869; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1870; CHECK-MVE-NEXT: cset r3, le 1871; CHECK-MVE-NEXT: cmp r3, #0 1872; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 1873; CHECK-MVE-NEXT: cmp r2, #0 1874; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 1875; CHECK-MVE-NEXT: cmp r1, #0 1876; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 1877; CHECK-MVE-NEXT: cmp r0, #0 1878; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 1879; CHECK-MVE-NEXT: bx lr 1880; 1881; CHECK-MVEFP-LABEL: vcmp_r_uge_v4f32: 1882; CHECK-MVEFP: @ %bb.0: @ %entry 1883; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr 1884; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1885; CHECK-MVEFP-NEXT: bx lr 1886entry: 1887 %c = fcmp uge <4 x float> zeroinitializer, %src 1888 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1889 ret <4 x float> %s 1890} 1891 1892define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 1893; CHECK-MVE-LABEL: vcmp_r_ult_v4f32: 1894; CHECK-MVE: @ %bb.0: @ %entry 1895; CHECK-MVE-NEXT: vcmp.f32 s0, #0 1896; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1897; CHECK-MVE-NEXT: vcmp.f32 s3, #0 1898; CHECK-MVE-NEXT: cset r0, hi 1899; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1900; CHECK-MVE-NEXT: vcmp.f32 s1, #0 1901; CHECK-MVE-NEXT: cset r1, hi 1902; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1903; CHECK-MVE-NEXT: vcmp.f32 s2, #0 1904; CHECK-MVE-NEXT: cset r2, hi 1905; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1906; CHECK-MVE-NEXT: cset r3, hi 1907; CHECK-MVE-NEXT: cmp r3, #0 1908; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 1909; CHECK-MVE-NEXT: cmp r2, #0 1910; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 1911; CHECK-MVE-NEXT: cmp r1, #0 1912; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 1913; CHECK-MVE-NEXT: cmp r0, #0 1914; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 1915; CHECK-MVE-NEXT: bx lr 1916; 1917; CHECK-MVEFP-LABEL: vcmp_r_ult_v4f32: 1918; CHECK-MVEFP: @ %bb.0: @ %entry 1919; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr 1920; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1921; CHECK-MVEFP-NEXT: bx lr 1922entry: 1923 %c = fcmp ult <4 x float> zeroinitializer, %src 1924 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1925 ret <4 x float> %s 1926} 1927 1928define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 1929; CHECK-MVE-LABEL: vcmp_r_ule_v4f32: 1930; CHECK-MVE: @ %bb.0: @ %entry 1931; CHECK-MVE-NEXT: vcmp.f32 s0, #0 1932; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1933; CHECK-MVE-NEXT: vcmp.f32 s3, #0 1934; CHECK-MVE-NEXT: cset r0, pl 1935; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1936; CHECK-MVE-NEXT: vcmp.f32 s1, #0 1937; CHECK-MVE-NEXT: cset r1, pl 1938; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1939; CHECK-MVE-NEXT: vcmp.f32 s2, #0 1940; CHECK-MVE-NEXT: cset r2, pl 1941; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1942; CHECK-MVE-NEXT: cset r3, pl 1943; CHECK-MVE-NEXT: cmp r3, #0 1944; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 1945; CHECK-MVE-NEXT: cmp r2, #0 1946; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 1947; CHECK-MVE-NEXT: cmp r1, #0 1948; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 1949; CHECK-MVE-NEXT: cmp r0, #0 1950; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 1951; CHECK-MVE-NEXT: bx lr 1952; 1953; CHECK-MVEFP-LABEL: vcmp_r_ule_v4f32: 1954; CHECK-MVEFP: @ %bb.0: @ %entry 1955; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr 1956; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 1957; CHECK-MVEFP-NEXT: bx lr 1958entry: 1959 %c = fcmp ule <4 x float> zeroinitializer, %src 1960 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1961 ret <4 x float> %s 1962} 1963 1964define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 1965; CHECK-MVE-LABEL: vcmp_r_ord_v4f32: 1966; CHECK-MVE: @ %bb.0: @ %entry 1967; CHECK-MVE-NEXT: vcmp.f32 s0, s0 1968; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1969; CHECK-MVE-NEXT: vcmp.f32 s3, s3 1970; CHECK-MVE-NEXT: cset r0, vc 1971; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1972; CHECK-MVE-NEXT: vcmp.f32 s1, s1 1973; CHECK-MVE-NEXT: cset r1, vc 1974; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1975; CHECK-MVE-NEXT: vcmp.f32 s2, s2 1976; CHECK-MVE-NEXT: cset r2, vc 1977; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1978; CHECK-MVE-NEXT: cset r3, vc 1979; CHECK-MVE-NEXT: cmp r3, #0 1980; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 1981; CHECK-MVE-NEXT: cmp r2, #0 1982; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 1983; CHECK-MVE-NEXT: cmp r1, #0 1984; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 1985; CHECK-MVE-NEXT: cmp r0, #0 1986; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 1987; CHECK-MVE-NEXT: bx lr 1988; 1989; CHECK-MVEFP-LABEL: vcmp_r_ord_v4f32: 1990; CHECK-MVEFP: @ %bb.0: @ %entry 1991; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr 1992; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, zr 1993; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 1994; CHECK-MVEFP-NEXT: bx lr 1995entry: 1996 %c = fcmp ord <4 x float> zeroinitializer, %src 1997 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1998 ret <4 x float> %s 1999} 2000 2001define arm_aapcs_vfpcc <4 x float> @vcmp_r_uno_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { 2002; CHECK-MVE-LABEL: vcmp_r_uno_v4f32: 2003; CHECK-MVE: @ %bb.0: @ %entry 2004; CHECK-MVE-NEXT: vcmp.f32 s0, s0 2005; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2006; CHECK-MVE-NEXT: vcmp.f32 s3, s3 2007; CHECK-MVE-NEXT: cset r0, vs 2008; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2009; CHECK-MVE-NEXT: vcmp.f32 s1, s1 2010; CHECK-MVE-NEXT: cset r1, vs 2011; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2012; CHECK-MVE-NEXT: vcmp.f32 s2, s2 2013; CHECK-MVE-NEXT: cset r2, vs 2014; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2015; CHECK-MVE-NEXT: cset r3, vs 2016; CHECK-MVE-NEXT: cmp r3, #0 2017; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 2018; CHECK-MVE-NEXT: cmp r2, #0 2019; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 2020; CHECK-MVE-NEXT: cmp r1, #0 2021; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 2022; CHECK-MVE-NEXT: cmp r0, #0 2023; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 2024; CHECK-MVE-NEXT: bx lr 2025; 2026; CHECK-MVEFP-LABEL: vcmp_r_uno_v4f32: 2027; CHECK-MVEFP: @ %bb.0: @ %entry 2028; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr 2029; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, zr 2030; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 2031; CHECK-MVEFP-NEXT: bx lr 2032entry: 2033 %c = fcmp uno <4 x float> zeroinitializer, %src 2034 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 2035 ret <4 x float> %s 2036} 2037 2038 2039 2040define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 2041; CHECK-MVE-LABEL: vcmp_r_oeq_v8f16: 2042; CHECK-MVE: @ %bb.0: @ %entry 2043; CHECK-MVE-NEXT: vmovx.f16 s12, s0 2044; CHECK-MVE-NEXT: vmovx.f16 s14, s8 2045; CHECK-MVE-NEXT: vcmp.f16 s12, #0 2046; CHECK-MVE-NEXT: vmovx.f16 s12, s4 2047; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2048; CHECK-MVE-NEXT: vcmp.f16 s0, #0 2049; CHECK-MVE-NEXT: cset r0, eq 2050; CHECK-MVE-NEXT: cmp r0, #0 2051; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 2052; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2053; CHECK-MVE-NEXT: cset r0, eq 2054; CHECK-MVE-NEXT: cmp r0, #0 2055; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 2056; CHECK-MVE-NEXT: vmovx.f16 s4, s1 2057; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2058; CHECK-MVE-NEXT: vmovx.f16 s4, s5 2059; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2060; CHECK-MVE-NEXT: vmovx.f16 s8, s9 2061; CHECK-MVE-NEXT: vcmp.f16 s1, #0 2062; CHECK-MVE-NEXT: vins.f16 s0, s12 2063; CHECK-MVE-NEXT: cset r0, eq 2064; CHECK-MVE-NEXT: cmp r0, #0 2065; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2066; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2067; CHECK-MVE-NEXT: vmovx.f16 s8, s10 2068; CHECK-MVE-NEXT: cset r0, eq 2069; CHECK-MVE-NEXT: cmp r0, #0 2070; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 2071; CHECK-MVE-NEXT: vins.f16 s1, s4 2072; CHECK-MVE-NEXT: vmovx.f16 s4, s2 2073; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2074; CHECK-MVE-NEXT: vmovx.f16 s4, s6 2075; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2076; CHECK-MVE-NEXT: vcmp.f16 s2, #0 2077; CHECK-MVE-NEXT: cset r0, eq 2078; CHECK-MVE-NEXT: cmp r0, #0 2079; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2080; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2081; CHECK-MVE-NEXT: cset r0, eq 2082; CHECK-MVE-NEXT: cmp r0, #0 2083; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 2084; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2085; CHECK-MVE-NEXT: vins.f16 s2, s4 2086; CHECK-MVE-NEXT: vmovx.f16 s4, s3 2087; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2088; CHECK-MVE-NEXT: vmovx.f16 s4, s7 2089; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2090; CHECK-MVE-NEXT: vcmp.f16 s3, #0 2091; CHECK-MVE-NEXT: cset r0, eq 2092; CHECK-MVE-NEXT: cmp r0, #0 2093; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 2094; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2095; CHECK-MVE-NEXT: cset r0, eq 2096; CHECK-MVE-NEXT: cmp r0, #0 2097; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 2098; CHECK-MVE-NEXT: vins.f16 s3, s4 2099; CHECK-MVE-NEXT: bx lr 2100; 2101; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16: 2102; CHECK-MVEFP: @ %bb.0: @ %entry 2103; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr 2104; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 2105; CHECK-MVEFP-NEXT: bx lr 2106entry: 2107 %c = fcmp oeq <8 x half> zeroinitializer, %src 2108 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2109 ret <8 x half> %s 2110} 2111 2112define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 2113; CHECK-MVE-LABEL: vcmp_r_one_v8f16: 2114; CHECK-MVE: @ %bb.0: @ %entry 2115; CHECK-MVE-NEXT: vmovx.f16 s12, s0 2116; CHECK-MVE-NEXT: vmovx.f16 s14, s8 2117; CHECK-MVE-NEXT: vcmp.f16 s12, #0 2118; CHECK-MVE-NEXT: vmovx.f16 s12, s4 2119; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2120; CHECK-MVE-NEXT: vcmp.f16 s0, #0 2121; CHECK-MVE-NEXT: cset r0, mi 2122; CHECK-MVE-NEXT: csinc r0, r0, zr, le 2123; CHECK-MVE-NEXT: cmp r0, #0 2124; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 2125; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2126; CHECK-MVE-NEXT: cset r0, mi 2127; CHECK-MVE-NEXT: csinc r0, r0, zr, le 2128; CHECK-MVE-NEXT: cmp r0, #0 2129; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 2130; CHECK-MVE-NEXT: vmovx.f16 s4, s1 2131; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2132; CHECK-MVE-NEXT: vmovx.f16 s4, s5 2133; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2134; CHECK-MVE-NEXT: vmovx.f16 s8, s9 2135; CHECK-MVE-NEXT: vcmp.f16 s1, #0 2136; CHECK-MVE-NEXT: vins.f16 s0, s12 2137; CHECK-MVE-NEXT: cset r0, mi 2138; CHECK-MVE-NEXT: csinc r0, r0, zr, le 2139; CHECK-MVE-NEXT: cmp r0, #0 2140; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2141; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2142; CHECK-MVE-NEXT: vmovx.f16 s8, s10 2143; CHECK-MVE-NEXT: cset r0, mi 2144; CHECK-MVE-NEXT: csinc r0, r0, zr, le 2145; CHECK-MVE-NEXT: cmp r0, #0 2146; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 2147; CHECK-MVE-NEXT: vins.f16 s1, s4 2148; CHECK-MVE-NEXT: vmovx.f16 s4, s2 2149; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2150; CHECK-MVE-NEXT: vmovx.f16 s4, s6 2151; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2152; CHECK-MVE-NEXT: vcmp.f16 s2, #0 2153; CHECK-MVE-NEXT: cset r0, mi 2154; CHECK-MVE-NEXT: csinc r0, r0, zr, le 2155; CHECK-MVE-NEXT: cmp r0, #0 2156; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2157; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2158; CHECK-MVE-NEXT: cset r0, mi 2159; CHECK-MVE-NEXT: csinc r0, r0, zr, le 2160; CHECK-MVE-NEXT: cmp r0, #0 2161; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 2162; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2163; CHECK-MVE-NEXT: vins.f16 s2, s4 2164; CHECK-MVE-NEXT: vmovx.f16 s4, s3 2165; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2166; CHECK-MVE-NEXT: vmovx.f16 s4, s7 2167; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2168; CHECK-MVE-NEXT: vcmp.f16 s3, #0 2169; CHECK-MVE-NEXT: cset r0, mi 2170; CHECK-MVE-NEXT: csinc r0, r0, zr, le 2171; CHECK-MVE-NEXT: cmp r0, #0 2172; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 2173; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2174; CHECK-MVE-NEXT: cset r0, mi 2175; CHECK-MVE-NEXT: csinc r0, r0, zr, le 2176; CHECK-MVE-NEXT: cmp r0, #0 2177; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 2178; CHECK-MVE-NEXT: vins.f16 s3, s4 2179; CHECK-MVE-NEXT: bx lr 2180; 2181; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16: 2182; CHECK-MVEFP: @ %bb.0: @ %entry 2183; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr 2184; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr 2185; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 2186; CHECK-MVEFP-NEXT: bx lr 2187entry: 2188 %c = fcmp one <8 x half> zeroinitializer, %src 2189 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2190 ret <8 x half> %s 2191} 2192 2193define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 2194; CHECK-MVE-LABEL: vcmp_r_ogt_v8f16: 2195; CHECK-MVE: @ %bb.0: @ %entry 2196; CHECK-MVE-NEXT: vmovx.f16 s12, s0 2197; CHECK-MVE-NEXT: vmovx.f16 s14, s8 2198; CHECK-MVE-NEXT: vcmp.f16 s12, #0 2199; CHECK-MVE-NEXT: vmovx.f16 s12, s4 2200; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2201; CHECK-MVE-NEXT: vcmp.f16 s0, #0 2202; CHECK-MVE-NEXT: cset r0, mi 2203; CHECK-MVE-NEXT: cmp r0, #0 2204; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 2205; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2206; CHECK-MVE-NEXT: cset r0, mi 2207; CHECK-MVE-NEXT: cmp r0, #0 2208; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 2209; CHECK-MVE-NEXT: vmovx.f16 s4, s1 2210; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2211; CHECK-MVE-NEXT: vmovx.f16 s4, s5 2212; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2213; CHECK-MVE-NEXT: vmovx.f16 s8, s9 2214; CHECK-MVE-NEXT: vcmp.f16 s1, #0 2215; CHECK-MVE-NEXT: vins.f16 s0, s12 2216; CHECK-MVE-NEXT: cset r0, mi 2217; CHECK-MVE-NEXT: cmp r0, #0 2218; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2219; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2220; CHECK-MVE-NEXT: vmovx.f16 s8, s10 2221; CHECK-MVE-NEXT: cset r0, mi 2222; CHECK-MVE-NEXT: cmp r0, #0 2223; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 2224; CHECK-MVE-NEXT: vins.f16 s1, s4 2225; CHECK-MVE-NEXT: vmovx.f16 s4, s2 2226; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2227; CHECK-MVE-NEXT: vmovx.f16 s4, s6 2228; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2229; CHECK-MVE-NEXT: vcmp.f16 s2, #0 2230; CHECK-MVE-NEXT: cset r0, mi 2231; CHECK-MVE-NEXT: cmp r0, #0 2232; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2233; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2234; CHECK-MVE-NEXT: cset r0, mi 2235; CHECK-MVE-NEXT: cmp r0, #0 2236; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 2237; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2238; CHECK-MVE-NEXT: vins.f16 s2, s4 2239; CHECK-MVE-NEXT: vmovx.f16 s4, s3 2240; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2241; CHECK-MVE-NEXT: vmovx.f16 s4, s7 2242; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2243; CHECK-MVE-NEXT: vcmp.f16 s3, #0 2244; CHECK-MVE-NEXT: cset r0, mi 2245; CHECK-MVE-NEXT: cmp r0, #0 2246; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 2247; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2248; CHECK-MVE-NEXT: cset r0, mi 2249; CHECK-MVE-NEXT: cmp r0, #0 2250; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 2251; CHECK-MVE-NEXT: vins.f16 s3, s4 2252; CHECK-MVE-NEXT: bx lr 2253; 2254; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16: 2255; CHECK-MVEFP: @ %bb.0: @ %entry 2256; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr 2257; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 2258; CHECK-MVEFP-NEXT: bx lr 2259entry: 2260 %c = fcmp ogt <8 x half> zeroinitializer, %src 2261 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2262 ret <8 x half> %s 2263} 2264 2265define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 2266; CHECK-MVE-LABEL: vcmp_r_oge_v8f16: 2267; CHECK-MVE: @ %bb.0: @ %entry 2268; CHECK-MVE-NEXT: vmovx.f16 s12, s0 2269; CHECK-MVE-NEXT: vmovx.f16 s14, s8 2270; CHECK-MVE-NEXT: vcmp.f16 s12, #0 2271; CHECK-MVE-NEXT: vmovx.f16 s12, s4 2272; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2273; CHECK-MVE-NEXT: vcmp.f16 s0, #0 2274; CHECK-MVE-NEXT: cset r0, ls 2275; CHECK-MVE-NEXT: cmp r0, #0 2276; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 2277; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2278; CHECK-MVE-NEXT: cset r0, ls 2279; CHECK-MVE-NEXT: cmp r0, #0 2280; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 2281; CHECK-MVE-NEXT: vmovx.f16 s4, s1 2282; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2283; CHECK-MVE-NEXT: vmovx.f16 s4, s5 2284; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2285; CHECK-MVE-NEXT: vmovx.f16 s8, s9 2286; CHECK-MVE-NEXT: vcmp.f16 s1, #0 2287; CHECK-MVE-NEXT: vins.f16 s0, s12 2288; CHECK-MVE-NEXT: cset r0, ls 2289; CHECK-MVE-NEXT: cmp r0, #0 2290; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2291; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2292; CHECK-MVE-NEXT: vmovx.f16 s8, s10 2293; CHECK-MVE-NEXT: cset r0, ls 2294; CHECK-MVE-NEXT: cmp r0, #0 2295; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 2296; CHECK-MVE-NEXT: vins.f16 s1, s4 2297; CHECK-MVE-NEXT: vmovx.f16 s4, s2 2298; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2299; CHECK-MVE-NEXT: vmovx.f16 s4, s6 2300; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2301; CHECK-MVE-NEXT: vcmp.f16 s2, #0 2302; CHECK-MVE-NEXT: cset r0, ls 2303; CHECK-MVE-NEXT: cmp r0, #0 2304; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2305; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2306; CHECK-MVE-NEXT: cset r0, ls 2307; CHECK-MVE-NEXT: cmp r0, #0 2308; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 2309; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2310; CHECK-MVE-NEXT: vins.f16 s2, s4 2311; CHECK-MVE-NEXT: vmovx.f16 s4, s3 2312; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2313; CHECK-MVE-NEXT: vmovx.f16 s4, s7 2314; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2315; CHECK-MVE-NEXT: vcmp.f16 s3, #0 2316; CHECK-MVE-NEXT: cset r0, ls 2317; CHECK-MVE-NEXT: cmp r0, #0 2318; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 2319; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2320; CHECK-MVE-NEXT: cset r0, ls 2321; CHECK-MVE-NEXT: cmp r0, #0 2322; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 2323; CHECK-MVE-NEXT: vins.f16 s3, s4 2324; CHECK-MVE-NEXT: bx lr 2325; 2326; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16: 2327; CHECK-MVEFP: @ %bb.0: @ %entry 2328; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr 2329; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 2330; CHECK-MVEFP-NEXT: bx lr 2331entry: 2332 %c = fcmp oge <8 x half> zeroinitializer, %src 2333 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2334 ret <8 x half> %s 2335} 2336 2337define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 2338; CHECK-MVE-LABEL: vcmp_r_olt_v8f16: 2339; CHECK-MVE: @ %bb.0: @ %entry 2340; CHECK-MVE-NEXT: vmovx.f16 s12, s0 2341; CHECK-MVE-NEXT: vmovx.f16 s14, s8 2342; CHECK-MVE-NEXT: vcmp.f16 s12, #0 2343; CHECK-MVE-NEXT: vmovx.f16 s12, s4 2344; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2345; CHECK-MVE-NEXT: vcmp.f16 s0, #0 2346; CHECK-MVE-NEXT: cset r0, gt 2347; CHECK-MVE-NEXT: cmp r0, #0 2348; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 2349; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2350; CHECK-MVE-NEXT: cset r0, gt 2351; CHECK-MVE-NEXT: cmp r0, #0 2352; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 2353; CHECK-MVE-NEXT: vmovx.f16 s4, s1 2354; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2355; CHECK-MVE-NEXT: vmovx.f16 s4, s5 2356; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2357; CHECK-MVE-NEXT: vmovx.f16 s8, s9 2358; CHECK-MVE-NEXT: vcmp.f16 s1, #0 2359; CHECK-MVE-NEXT: vins.f16 s0, s12 2360; CHECK-MVE-NEXT: cset r0, gt 2361; CHECK-MVE-NEXT: cmp r0, #0 2362; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2363; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2364; CHECK-MVE-NEXT: vmovx.f16 s8, s10 2365; CHECK-MVE-NEXT: cset r0, gt 2366; CHECK-MVE-NEXT: cmp r0, #0 2367; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 2368; CHECK-MVE-NEXT: vins.f16 s1, s4 2369; CHECK-MVE-NEXT: vmovx.f16 s4, s2 2370; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2371; CHECK-MVE-NEXT: vmovx.f16 s4, s6 2372; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2373; CHECK-MVE-NEXT: vcmp.f16 s2, #0 2374; CHECK-MVE-NEXT: cset r0, gt 2375; CHECK-MVE-NEXT: cmp r0, #0 2376; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2377; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2378; CHECK-MVE-NEXT: cset r0, gt 2379; CHECK-MVE-NEXT: cmp r0, #0 2380; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 2381; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2382; CHECK-MVE-NEXT: vins.f16 s2, s4 2383; CHECK-MVE-NEXT: vmovx.f16 s4, s3 2384; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2385; CHECK-MVE-NEXT: vmovx.f16 s4, s7 2386; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2387; CHECK-MVE-NEXT: vcmp.f16 s3, #0 2388; CHECK-MVE-NEXT: cset r0, gt 2389; CHECK-MVE-NEXT: cmp r0, #0 2390; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 2391; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2392; CHECK-MVE-NEXT: cset r0, gt 2393; CHECK-MVE-NEXT: cmp r0, #0 2394; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 2395; CHECK-MVE-NEXT: vins.f16 s3, s4 2396; CHECK-MVE-NEXT: bx lr 2397; 2398; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16: 2399; CHECK-MVEFP: @ %bb.0: @ %entry 2400; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr 2401; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 2402; CHECK-MVEFP-NEXT: bx lr 2403entry: 2404 %c = fcmp olt <8 x half> zeroinitializer, %src 2405 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2406 ret <8 x half> %s 2407} 2408 2409define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 2410; CHECK-MVE-LABEL: vcmp_r_ole_v8f16: 2411; CHECK-MVE: @ %bb.0: @ %entry 2412; CHECK-MVE-NEXT: vmovx.f16 s12, s0 2413; CHECK-MVE-NEXT: vmovx.f16 s14, s8 2414; CHECK-MVE-NEXT: vcmp.f16 s12, #0 2415; CHECK-MVE-NEXT: vmovx.f16 s12, s4 2416; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2417; CHECK-MVE-NEXT: vcmp.f16 s0, #0 2418; CHECK-MVE-NEXT: cset r0, ge 2419; CHECK-MVE-NEXT: cmp r0, #0 2420; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 2421; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2422; CHECK-MVE-NEXT: cset r0, ge 2423; CHECK-MVE-NEXT: cmp r0, #0 2424; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 2425; CHECK-MVE-NEXT: vmovx.f16 s4, s1 2426; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2427; CHECK-MVE-NEXT: vmovx.f16 s4, s5 2428; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2429; CHECK-MVE-NEXT: vmovx.f16 s8, s9 2430; CHECK-MVE-NEXT: vcmp.f16 s1, #0 2431; CHECK-MVE-NEXT: vins.f16 s0, s12 2432; CHECK-MVE-NEXT: cset r0, ge 2433; CHECK-MVE-NEXT: cmp r0, #0 2434; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2435; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2436; CHECK-MVE-NEXT: vmovx.f16 s8, s10 2437; CHECK-MVE-NEXT: cset r0, ge 2438; CHECK-MVE-NEXT: cmp r0, #0 2439; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 2440; CHECK-MVE-NEXT: vins.f16 s1, s4 2441; CHECK-MVE-NEXT: vmovx.f16 s4, s2 2442; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2443; CHECK-MVE-NEXT: vmovx.f16 s4, s6 2444; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2445; CHECK-MVE-NEXT: vcmp.f16 s2, #0 2446; CHECK-MVE-NEXT: cset r0, ge 2447; CHECK-MVE-NEXT: cmp r0, #0 2448; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2449; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2450; CHECK-MVE-NEXT: cset r0, ge 2451; CHECK-MVE-NEXT: cmp r0, #0 2452; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 2453; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2454; CHECK-MVE-NEXT: vins.f16 s2, s4 2455; CHECK-MVE-NEXT: vmovx.f16 s4, s3 2456; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2457; CHECK-MVE-NEXT: vmovx.f16 s4, s7 2458; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2459; CHECK-MVE-NEXT: vcmp.f16 s3, #0 2460; CHECK-MVE-NEXT: cset r0, ge 2461; CHECK-MVE-NEXT: cmp r0, #0 2462; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 2463; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2464; CHECK-MVE-NEXT: cset r0, ge 2465; CHECK-MVE-NEXT: cmp r0, #0 2466; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 2467; CHECK-MVE-NEXT: vins.f16 s3, s4 2468; CHECK-MVE-NEXT: bx lr 2469; 2470; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16: 2471; CHECK-MVEFP: @ %bb.0: @ %entry 2472; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr 2473; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 2474; CHECK-MVEFP-NEXT: bx lr 2475entry: 2476 %c = fcmp ole <8 x half> zeroinitializer, %src 2477 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2478 ret <8 x half> %s 2479} 2480 2481define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 2482; CHECK-MVE-LABEL: vcmp_r_ueq_v8f16: 2483; CHECK-MVE: @ %bb.0: @ %entry 2484; CHECK-MVE-NEXT: vmovx.f16 s12, s0 2485; CHECK-MVE-NEXT: vmovx.f16 s14, s8 2486; CHECK-MVE-NEXT: vcmp.f16 s12, #0 2487; CHECK-MVE-NEXT: vmovx.f16 s12, s4 2488; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2489; CHECK-MVE-NEXT: vcmp.f16 s0, #0 2490; CHECK-MVE-NEXT: cset r0, eq 2491; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 2492; CHECK-MVE-NEXT: cmp r0, #0 2493; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 2494; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2495; CHECK-MVE-NEXT: cset r0, eq 2496; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 2497; CHECK-MVE-NEXT: cmp r0, #0 2498; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 2499; CHECK-MVE-NEXT: vmovx.f16 s4, s1 2500; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2501; CHECK-MVE-NEXT: vmovx.f16 s4, s5 2502; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2503; CHECK-MVE-NEXT: vmovx.f16 s8, s9 2504; CHECK-MVE-NEXT: vcmp.f16 s1, #0 2505; CHECK-MVE-NEXT: vins.f16 s0, s12 2506; CHECK-MVE-NEXT: cset r0, eq 2507; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 2508; CHECK-MVE-NEXT: cmp r0, #0 2509; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2510; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2511; CHECK-MVE-NEXT: vmovx.f16 s8, s10 2512; CHECK-MVE-NEXT: cset r0, eq 2513; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 2514; CHECK-MVE-NEXT: cmp r0, #0 2515; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 2516; CHECK-MVE-NEXT: vins.f16 s1, s4 2517; CHECK-MVE-NEXT: vmovx.f16 s4, s2 2518; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2519; CHECK-MVE-NEXT: vmovx.f16 s4, s6 2520; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2521; CHECK-MVE-NEXT: vcmp.f16 s2, #0 2522; CHECK-MVE-NEXT: cset r0, eq 2523; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 2524; CHECK-MVE-NEXT: cmp r0, #0 2525; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2526; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2527; CHECK-MVE-NEXT: cset r0, eq 2528; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 2529; CHECK-MVE-NEXT: cmp r0, #0 2530; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 2531; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2532; CHECK-MVE-NEXT: vins.f16 s2, s4 2533; CHECK-MVE-NEXT: vmovx.f16 s4, s3 2534; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2535; CHECK-MVE-NEXT: vmovx.f16 s4, s7 2536; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2537; CHECK-MVE-NEXT: vcmp.f16 s3, #0 2538; CHECK-MVE-NEXT: cset r0, eq 2539; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 2540; CHECK-MVE-NEXT: cmp r0, #0 2541; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 2542; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2543; CHECK-MVE-NEXT: cset r0, eq 2544; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 2545; CHECK-MVE-NEXT: cmp r0, #0 2546; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 2547; CHECK-MVE-NEXT: vins.f16 s3, s4 2548; CHECK-MVE-NEXT: bx lr 2549; 2550; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16: 2551; CHECK-MVEFP: @ %bb.0: @ %entry 2552; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr 2553; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr 2554; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 2555; CHECK-MVEFP-NEXT: bx lr 2556entry: 2557 %c = fcmp ueq <8 x half> zeroinitializer, %src 2558 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2559 ret <8 x half> %s 2560} 2561 2562define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 2563; CHECK-MVE-LABEL: vcmp_r_une_v8f16: 2564; CHECK-MVE: @ %bb.0: @ %entry 2565; CHECK-MVE-NEXT: vmovx.f16 s12, s0 2566; CHECK-MVE-NEXT: vmovx.f16 s14, s8 2567; CHECK-MVE-NEXT: vcmp.f16 s12, #0 2568; CHECK-MVE-NEXT: vmovx.f16 s12, s4 2569; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2570; CHECK-MVE-NEXT: vcmp.f16 s0, #0 2571; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 2572; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2573; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 2574; CHECK-MVE-NEXT: vmovx.f16 s4, s1 2575; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2576; CHECK-MVE-NEXT: vmovx.f16 s4, s5 2577; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2578; CHECK-MVE-NEXT: vmovx.f16 s8, s9 2579; CHECK-MVE-NEXT: vcmp.f16 s1, #0 2580; CHECK-MVE-NEXT: vins.f16 s0, s12 2581; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2582; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2583; CHECK-MVE-NEXT: vmovx.f16 s8, s10 2584; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 2585; CHECK-MVE-NEXT: vins.f16 s1, s4 2586; CHECK-MVE-NEXT: vmovx.f16 s4, s2 2587; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2588; CHECK-MVE-NEXT: vmovx.f16 s4, s6 2589; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2590; CHECK-MVE-NEXT: vcmp.f16 s2, #0 2591; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2592; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2593; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 2594; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2595; CHECK-MVE-NEXT: vins.f16 s2, s4 2596; CHECK-MVE-NEXT: vmovx.f16 s4, s3 2597; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2598; CHECK-MVE-NEXT: vmovx.f16 s4, s7 2599; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2600; CHECK-MVE-NEXT: vcmp.f16 s3, #0 2601; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 2602; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2603; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 2604; CHECK-MVE-NEXT: vins.f16 s3, s4 2605; CHECK-MVE-NEXT: bx lr 2606; 2607; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16: 2608; CHECK-MVEFP: @ %bb.0: @ %entry 2609; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr 2610; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 2611; CHECK-MVEFP-NEXT: bx lr 2612entry: 2613 %c = fcmp une <8 x half> zeroinitializer, %src 2614 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2615 ret <8 x half> %s 2616} 2617 2618define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 2619; CHECK-MVE-LABEL: vcmp_r_ugt_v8f16: 2620; CHECK-MVE: @ %bb.0: @ %entry 2621; CHECK-MVE-NEXT: vmovx.f16 s12, s0 2622; CHECK-MVE-NEXT: vmovx.f16 s14, s8 2623; CHECK-MVE-NEXT: vcmp.f16 s12, #0 2624; CHECK-MVE-NEXT: vmovx.f16 s12, s4 2625; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2626; CHECK-MVE-NEXT: vcmp.f16 s0, #0 2627; CHECK-MVE-NEXT: cset r0, lt 2628; CHECK-MVE-NEXT: cmp r0, #0 2629; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 2630; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2631; CHECK-MVE-NEXT: cset r0, lt 2632; CHECK-MVE-NEXT: cmp r0, #0 2633; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 2634; CHECK-MVE-NEXT: vmovx.f16 s4, s1 2635; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2636; CHECK-MVE-NEXT: vmovx.f16 s4, s5 2637; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2638; CHECK-MVE-NEXT: vmovx.f16 s8, s9 2639; CHECK-MVE-NEXT: vcmp.f16 s1, #0 2640; CHECK-MVE-NEXT: vins.f16 s0, s12 2641; CHECK-MVE-NEXT: cset r0, lt 2642; CHECK-MVE-NEXT: cmp r0, #0 2643; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2644; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2645; CHECK-MVE-NEXT: vmovx.f16 s8, s10 2646; CHECK-MVE-NEXT: cset r0, lt 2647; CHECK-MVE-NEXT: cmp r0, #0 2648; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 2649; CHECK-MVE-NEXT: vins.f16 s1, s4 2650; CHECK-MVE-NEXT: vmovx.f16 s4, s2 2651; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2652; CHECK-MVE-NEXT: vmovx.f16 s4, s6 2653; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2654; CHECK-MVE-NEXT: vcmp.f16 s2, #0 2655; CHECK-MVE-NEXT: cset r0, lt 2656; CHECK-MVE-NEXT: cmp r0, #0 2657; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2658; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2659; CHECK-MVE-NEXT: cset r0, lt 2660; CHECK-MVE-NEXT: cmp r0, #0 2661; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 2662; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2663; CHECK-MVE-NEXT: vins.f16 s2, s4 2664; CHECK-MVE-NEXT: vmovx.f16 s4, s3 2665; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2666; CHECK-MVE-NEXT: vmovx.f16 s4, s7 2667; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2668; CHECK-MVE-NEXT: vcmp.f16 s3, #0 2669; CHECK-MVE-NEXT: cset r0, lt 2670; CHECK-MVE-NEXT: cmp r0, #0 2671; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 2672; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2673; CHECK-MVE-NEXT: cset r0, lt 2674; CHECK-MVE-NEXT: cmp r0, #0 2675; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 2676; CHECK-MVE-NEXT: vins.f16 s3, s4 2677; CHECK-MVE-NEXT: bx lr 2678; 2679; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16: 2680; CHECK-MVEFP: @ %bb.0: @ %entry 2681; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr 2682; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 2683; CHECK-MVEFP-NEXT: bx lr 2684entry: 2685 %c = fcmp ugt <8 x half> zeroinitializer, %src 2686 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2687 ret <8 x half> %s 2688} 2689 2690define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 2691; CHECK-MVE-LABEL: vcmp_r_uge_v8f16: 2692; CHECK-MVE: @ %bb.0: @ %entry 2693; CHECK-MVE-NEXT: vmovx.f16 s12, s0 2694; CHECK-MVE-NEXT: vmovx.f16 s14, s8 2695; CHECK-MVE-NEXT: vcmp.f16 s12, #0 2696; CHECK-MVE-NEXT: vmovx.f16 s12, s4 2697; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2698; CHECK-MVE-NEXT: vcmp.f16 s0, #0 2699; CHECK-MVE-NEXT: cset r0, le 2700; CHECK-MVE-NEXT: cmp r0, #0 2701; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 2702; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2703; CHECK-MVE-NEXT: cset r0, le 2704; CHECK-MVE-NEXT: cmp r0, #0 2705; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 2706; CHECK-MVE-NEXT: vmovx.f16 s4, s1 2707; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2708; CHECK-MVE-NEXT: vmovx.f16 s4, s5 2709; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2710; CHECK-MVE-NEXT: vmovx.f16 s8, s9 2711; CHECK-MVE-NEXT: vcmp.f16 s1, #0 2712; CHECK-MVE-NEXT: vins.f16 s0, s12 2713; CHECK-MVE-NEXT: cset r0, le 2714; CHECK-MVE-NEXT: cmp r0, #0 2715; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2716; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2717; CHECK-MVE-NEXT: vmovx.f16 s8, s10 2718; CHECK-MVE-NEXT: cset r0, le 2719; CHECK-MVE-NEXT: cmp r0, #0 2720; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 2721; CHECK-MVE-NEXT: vins.f16 s1, s4 2722; CHECK-MVE-NEXT: vmovx.f16 s4, s2 2723; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2724; CHECK-MVE-NEXT: vmovx.f16 s4, s6 2725; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2726; CHECK-MVE-NEXT: vcmp.f16 s2, #0 2727; CHECK-MVE-NEXT: cset r0, le 2728; CHECK-MVE-NEXT: cmp r0, #0 2729; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2730; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2731; CHECK-MVE-NEXT: cset r0, le 2732; CHECK-MVE-NEXT: cmp r0, #0 2733; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 2734; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2735; CHECK-MVE-NEXT: vins.f16 s2, s4 2736; CHECK-MVE-NEXT: vmovx.f16 s4, s3 2737; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2738; CHECK-MVE-NEXT: vmovx.f16 s4, s7 2739; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2740; CHECK-MVE-NEXT: vcmp.f16 s3, #0 2741; CHECK-MVE-NEXT: cset r0, le 2742; CHECK-MVE-NEXT: cmp r0, #0 2743; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 2744; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2745; CHECK-MVE-NEXT: cset r0, le 2746; CHECK-MVE-NEXT: cmp r0, #0 2747; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 2748; CHECK-MVE-NEXT: vins.f16 s3, s4 2749; CHECK-MVE-NEXT: bx lr 2750; 2751; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16: 2752; CHECK-MVEFP: @ %bb.0: @ %entry 2753; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr 2754; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 2755; CHECK-MVEFP-NEXT: bx lr 2756entry: 2757 %c = fcmp uge <8 x half> zeroinitializer, %src 2758 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2759 ret <8 x half> %s 2760} 2761 2762define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 2763; CHECK-MVE-LABEL: vcmp_r_ult_v8f16: 2764; CHECK-MVE: @ %bb.0: @ %entry 2765; CHECK-MVE-NEXT: vmovx.f16 s12, s0 2766; CHECK-MVE-NEXT: vmovx.f16 s14, s8 2767; CHECK-MVE-NEXT: vcmp.f16 s12, #0 2768; CHECK-MVE-NEXT: vmovx.f16 s12, s4 2769; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2770; CHECK-MVE-NEXT: vcmp.f16 s0, #0 2771; CHECK-MVE-NEXT: cset r0, hi 2772; CHECK-MVE-NEXT: cmp r0, #0 2773; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 2774; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2775; CHECK-MVE-NEXT: cset r0, hi 2776; CHECK-MVE-NEXT: cmp r0, #0 2777; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 2778; CHECK-MVE-NEXT: vmovx.f16 s4, s1 2779; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2780; CHECK-MVE-NEXT: vmovx.f16 s4, s5 2781; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2782; CHECK-MVE-NEXT: vmovx.f16 s8, s9 2783; CHECK-MVE-NEXT: vcmp.f16 s1, #0 2784; CHECK-MVE-NEXT: vins.f16 s0, s12 2785; CHECK-MVE-NEXT: cset r0, hi 2786; CHECK-MVE-NEXT: cmp r0, #0 2787; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2788; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2789; CHECK-MVE-NEXT: vmovx.f16 s8, s10 2790; CHECK-MVE-NEXT: cset r0, hi 2791; CHECK-MVE-NEXT: cmp r0, #0 2792; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 2793; CHECK-MVE-NEXT: vins.f16 s1, s4 2794; CHECK-MVE-NEXT: vmovx.f16 s4, s2 2795; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2796; CHECK-MVE-NEXT: vmovx.f16 s4, s6 2797; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2798; CHECK-MVE-NEXT: vcmp.f16 s2, #0 2799; CHECK-MVE-NEXT: cset r0, hi 2800; CHECK-MVE-NEXT: cmp r0, #0 2801; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2802; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2803; CHECK-MVE-NEXT: cset r0, hi 2804; CHECK-MVE-NEXT: cmp r0, #0 2805; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 2806; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2807; CHECK-MVE-NEXT: vins.f16 s2, s4 2808; CHECK-MVE-NEXT: vmovx.f16 s4, s3 2809; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2810; CHECK-MVE-NEXT: vmovx.f16 s4, s7 2811; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2812; CHECK-MVE-NEXT: vcmp.f16 s3, #0 2813; CHECK-MVE-NEXT: cset r0, hi 2814; CHECK-MVE-NEXT: cmp r0, #0 2815; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 2816; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2817; CHECK-MVE-NEXT: cset r0, hi 2818; CHECK-MVE-NEXT: cmp r0, #0 2819; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 2820; CHECK-MVE-NEXT: vins.f16 s3, s4 2821; CHECK-MVE-NEXT: bx lr 2822; 2823; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16: 2824; CHECK-MVEFP: @ %bb.0: @ %entry 2825; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr 2826; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 2827; CHECK-MVEFP-NEXT: bx lr 2828entry: 2829 %c = fcmp ult <8 x half> zeroinitializer, %src 2830 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2831 ret <8 x half> %s 2832} 2833 2834define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 2835; CHECK-MVE-LABEL: vcmp_r_ule_v8f16: 2836; CHECK-MVE: @ %bb.0: @ %entry 2837; CHECK-MVE-NEXT: vmovx.f16 s12, s0 2838; CHECK-MVE-NEXT: vmovx.f16 s14, s8 2839; CHECK-MVE-NEXT: vcmp.f16 s12, #0 2840; CHECK-MVE-NEXT: vmovx.f16 s12, s4 2841; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2842; CHECK-MVE-NEXT: vcmp.f16 s0, #0 2843; CHECK-MVE-NEXT: cset r0, pl 2844; CHECK-MVE-NEXT: cmp r0, #0 2845; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 2846; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2847; CHECK-MVE-NEXT: cset r0, pl 2848; CHECK-MVE-NEXT: cmp r0, #0 2849; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 2850; CHECK-MVE-NEXT: vmovx.f16 s4, s1 2851; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2852; CHECK-MVE-NEXT: vmovx.f16 s4, s5 2853; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2854; CHECK-MVE-NEXT: vmovx.f16 s8, s9 2855; CHECK-MVE-NEXT: vcmp.f16 s1, #0 2856; CHECK-MVE-NEXT: vins.f16 s0, s12 2857; CHECK-MVE-NEXT: cset r0, pl 2858; CHECK-MVE-NEXT: cmp r0, #0 2859; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2860; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2861; CHECK-MVE-NEXT: vmovx.f16 s8, s10 2862; CHECK-MVE-NEXT: cset r0, pl 2863; CHECK-MVE-NEXT: cmp r0, #0 2864; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 2865; CHECK-MVE-NEXT: vins.f16 s1, s4 2866; CHECK-MVE-NEXT: vmovx.f16 s4, s2 2867; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2868; CHECK-MVE-NEXT: vmovx.f16 s4, s6 2869; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2870; CHECK-MVE-NEXT: vcmp.f16 s2, #0 2871; CHECK-MVE-NEXT: cset r0, pl 2872; CHECK-MVE-NEXT: cmp r0, #0 2873; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2874; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2875; CHECK-MVE-NEXT: cset r0, pl 2876; CHECK-MVE-NEXT: cmp r0, #0 2877; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 2878; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2879; CHECK-MVE-NEXT: vins.f16 s2, s4 2880; CHECK-MVE-NEXT: vmovx.f16 s4, s3 2881; CHECK-MVE-NEXT: vcmp.f16 s4, #0 2882; CHECK-MVE-NEXT: vmovx.f16 s4, s7 2883; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2884; CHECK-MVE-NEXT: vcmp.f16 s3, #0 2885; CHECK-MVE-NEXT: cset r0, pl 2886; CHECK-MVE-NEXT: cmp r0, #0 2887; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 2888; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2889; CHECK-MVE-NEXT: cset r0, pl 2890; CHECK-MVE-NEXT: cmp r0, #0 2891; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 2892; CHECK-MVE-NEXT: vins.f16 s3, s4 2893; CHECK-MVE-NEXT: bx lr 2894; 2895; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16: 2896; CHECK-MVEFP: @ %bb.0: @ %entry 2897; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr 2898; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 2899; CHECK-MVEFP-NEXT: bx lr 2900entry: 2901 %c = fcmp ule <8 x half> zeroinitializer, %src 2902 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2903 ret <8 x half> %s 2904} 2905 2906define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 2907; CHECK-MVE-LABEL: vcmp_r_ord_v8f16: 2908; CHECK-MVE: @ %bb.0: @ %entry 2909; CHECK-MVE-NEXT: vmovx.f16 s12, s0 2910; CHECK-MVE-NEXT: vmovx.f16 s14, s8 2911; CHECK-MVE-NEXT: vcmp.f16 s12, s12 2912; CHECK-MVE-NEXT: vmovx.f16 s12, s4 2913; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2914; CHECK-MVE-NEXT: vcmp.f16 s0, s0 2915; CHECK-MVE-NEXT: cset r0, vc 2916; CHECK-MVE-NEXT: cmp r0, #0 2917; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 2918; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2919; CHECK-MVE-NEXT: cset r0, vc 2920; CHECK-MVE-NEXT: cmp r0, #0 2921; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 2922; CHECK-MVE-NEXT: vmovx.f16 s4, s1 2923; CHECK-MVE-NEXT: vcmp.f16 s4, s4 2924; CHECK-MVE-NEXT: vmovx.f16 s4, s5 2925; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2926; CHECK-MVE-NEXT: vmovx.f16 s8, s9 2927; CHECK-MVE-NEXT: vcmp.f16 s1, s1 2928; CHECK-MVE-NEXT: vins.f16 s0, s12 2929; CHECK-MVE-NEXT: cset r0, vc 2930; CHECK-MVE-NEXT: cmp r0, #0 2931; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2932; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2933; CHECK-MVE-NEXT: vmovx.f16 s8, s10 2934; CHECK-MVE-NEXT: cset r0, vc 2935; CHECK-MVE-NEXT: cmp r0, #0 2936; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 2937; CHECK-MVE-NEXT: vins.f16 s1, s4 2938; CHECK-MVE-NEXT: vmovx.f16 s4, s2 2939; CHECK-MVE-NEXT: vcmp.f16 s4, s4 2940; CHECK-MVE-NEXT: vmovx.f16 s4, s6 2941; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2942; CHECK-MVE-NEXT: vcmp.f16 s2, s2 2943; CHECK-MVE-NEXT: cset r0, vc 2944; CHECK-MVE-NEXT: cmp r0, #0 2945; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 2946; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2947; CHECK-MVE-NEXT: cset r0, vc 2948; CHECK-MVE-NEXT: cmp r0, #0 2949; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 2950; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2951; CHECK-MVE-NEXT: vins.f16 s2, s4 2952; CHECK-MVE-NEXT: vmovx.f16 s4, s3 2953; CHECK-MVE-NEXT: vcmp.f16 s4, s4 2954; CHECK-MVE-NEXT: vmovx.f16 s4, s7 2955; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2956; CHECK-MVE-NEXT: vcmp.f16 s3, s3 2957; CHECK-MVE-NEXT: cset r0, vc 2958; CHECK-MVE-NEXT: cmp r0, #0 2959; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 2960; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2961; CHECK-MVE-NEXT: cset r0, vc 2962; CHECK-MVE-NEXT: cmp r0, #0 2963; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 2964; CHECK-MVE-NEXT: vins.f16 s3, s4 2965; CHECK-MVE-NEXT: bx lr 2966; 2967; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16: 2968; CHECK-MVEFP: @ %bb.0: @ %entry 2969; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr 2970; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr 2971; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 2972; CHECK-MVEFP-NEXT: bx lr 2973entry: 2974 %c = fcmp ord <8 x half> zeroinitializer, %src 2975 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2976 ret <8 x half> %s 2977} 2978 2979define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { 2980; CHECK-MVE-LABEL: vcmp_r_uno_v8f16: 2981; CHECK-MVE: @ %bb.0: @ %entry 2982; CHECK-MVE-NEXT: vmovx.f16 s12, s0 2983; CHECK-MVE-NEXT: vmovx.f16 s14, s8 2984; CHECK-MVE-NEXT: vcmp.f16 s12, s12 2985; CHECK-MVE-NEXT: vmovx.f16 s12, s4 2986; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2987; CHECK-MVE-NEXT: vcmp.f16 s0, s0 2988; CHECK-MVE-NEXT: cset r0, vs 2989; CHECK-MVE-NEXT: cmp r0, #0 2990; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 2991; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2992; CHECK-MVE-NEXT: cset r0, vs 2993; CHECK-MVE-NEXT: cmp r0, #0 2994; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 2995; CHECK-MVE-NEXT: vmovx.f16 s4, s1 2996; CHECK-MVE-NEXT: vcmp.f16 s4, s4 2997; CHECK-MVE-NEXT: vmovx.f16 s4, s5 2998; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2999; CHECK-MVE-NEXT: vmovx.f16 s8, s9 3000; CHECK-MVE-NEXT: vcmp.f16 s1, s1 3001; CHECK-MVE-NEXT: vins.f16 s0, s12 3002; CHECK-MVE-NEXT: cset r0, vs 3003; CHECK-MVE-NEXT: cmp r0, #0 3004; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 3005; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3006; CHECK-MVE-NEXT: vmovx.f16 s8, s10 3007; CHECK-MVE-NEXT: cset r0, vs 3008; CHECK-MVE-NEXT: cmp r0, #0 3009; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 3010; CHECK-MVE-NEXT: vins.f16 s1, s4 3011; CHECK-MVE-NEXT: vmovx.f16 s4, s2 3012; CHECK-MVE-NEXT: vcmp.f16 s4, s4 3013; CHECK-MVE-NEXT: vmovx.f16 s4, s6 3014; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3015; CHECK-MVE-NEXT: vcmp.f16 s2, s2 3016; CHECK-MVE-NEXT: cset r0, vs 3017; CHECK-MVE-NEXT: cmp r0, #0 3018; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 3019; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3020; CHECK-MVE-NEXT: cset r0, vs 3021; CHECK-MVE-NEXT: cmp r0, #0 3022; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 3023; CHECK-MVE-NEXT: vmovx.f16 s6, s11 3024; CHECK-MVE-NEXT: vins.f16 s2, s4 3025; CHECK-MVE-NEXT: vmovx.f16 s4, s3 3026; CHECK-MVE-NEXT: vcmp.f16 s4, s4 3027; CHECK-MVE-NEXT: vmovx.f16 s4, s7 3028; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3029; CHECK-MVE-NEXT: vcmp.f16 s3, s3 3030; CHECK-MVE-NEXT: cset r0, vs 3031; CHECK-MVE-NEXT: cmp r0, #0 3032; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 3033; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3034; CHECK-MVE-NEXT: cset r0, vs 3035; CHECK-MVE-NEXT: cmp r0, #0 3036; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 3037; CHECK-MVE-NEXT: vins.f16 s3, s4 3038; CHECK-MVE-NEXT: bx lr 3039; 3040; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16: 3041; CHECK-MVEFP: @ %bb.0: @ %entry 3042; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr 3043; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr 3044; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 3045; CHECK-MVEFP-NEXT: bx lr 3046entry: 3047 %c = fcmp uno <8 x half> zeroinitializer, %src 3048 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 3049 ret <8 x half> %s 3050} 3051