1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE 3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP 4 5define arm_aapcs_vfpcc <8 x half> @fneg_float16_t(<8 x half> %src) { 6; CHECK-MVE-LABEL: fneg_float16_t: 7; CHECK-MVE: @ %bb.0: @ %entry 8; CHECK-MVE-NEXT: vmovx.f16 s4, s0 9; CHECK-MVE-NEXT: vneg.f16 s0, s0 10; CHECK-MVE-NEXT: vneg.f16 s4, s4 11; CHECK-MVE-NEXT: vins.f16 s0, s4 12; CHECK-MVE-NEXT: vmovx.f16 s4, s1 13; CHECK-MVE-NEXT: vneg.f16 s4, s4 14; CHECK-MVE-NEXT: vneg.f16 s1, s1 15; CHECK-MVE-NEXT: vins.f16 s1, s4 16; CHECK-MVE-NEXT: vmovx.f16 s4, s2 17; CHECK-MVE-NEXT: vneg.f16 s4, s4 18; CHECK-MVE-NEXT: vneg.f16 s2, s2 19; CHECK-MVE-NEXT: vins.f16 s2, s4 20; CHECK-MVE-NEXT: vmovx.f16 s4, s3 21; CHECK-MVE-NEXT: vneg.f16 s4, s4 22; CHECK-MVE-NEXT: vneg.f16 s3, s3 23; CHECK-MVE-NEXT: vins.f16 s3, s4 24; CHECK-MVE-NEXT: bx lr 25; 26; CHECK-MVEFP-LABEL: fneg_float16_t: 27; CHECK-MVEFP: @ %bb.0: @ %entry 28; CHECK-MVEFP-NEXT: vneg.f16 q0, q0 29; CHECK-MVEFP-NEXT: bx lr 30entry: 31 %0 = fsub nnan ninf nsz <8 x half> <half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0>, %src 32 ret <8 x half> %0 33} 34 35define arm_aapcs_vfpcc <4 x float> @fneg_float32_t(<4 x float> %src) { 36; CHECK-MVE-LABEL: fneg_float32_t: 37; CHECK-MVE: @ %bb.0: @ %entry 38; CHECK-MVE-NEXT: vneg.f32 s3, s3 39; CHECK-MVE-NEXT: vneg.f32 s2, s2 40; CHECK-MVE-NEXT: vneg.f32 s1, s1 41; CHECK-MVE-NEXT: vneg.f32 s0, s0 42; CHECK-MVE-NEXT: bx lr 43; 44; CHECK-MVEFP-LABEL: fneg_float32_t: 45; CHECK-MVEFP: @ %bb.0: @ %entry 46; CHECK-MVEFP-NEXT: vneg.f32 q0, q0 47; CHECK-MVEFP-NEXT: bx lr 48entry: 49 %0 = fsub nnan ninf nsz <4 x float> <float 0.0e0, float 0.0e0, float 0.0e0, float 0.0e0>, %src 50 ret <4 x float> %0 51} 52 53define arm_aapcs_vfpcc <2 x double> @fneg_float64_t(<2 x double> %src) { 54; CHECK-LABEL: fneg_float64_t: 55; CHECK: @ %bb.0: @ %entry 56; CHECK-NEXT: .pad #16 57; CHECK-NEXT: sub sp, #16 58; CHECK-NEXT: vstr d1, [sp] 59; CHECK-NEXT: ldrb.w r0, [sp, #7] 60; CHECK-NEXT: vstr d0, [sp, #8] 61; CHECK-NEXT: ldrb.w r1, [sp, #15] 62; CHECK-NEXT: eor r0, r0, #128 63; CHECK-NEXT: strb.w r0, [sp, #7] 64; CHECK-NEXT: vldr d1, [sp] 65; CHECK-NEXT: eor r0, r1, #128 66; CHECK-NEXT: strb.w r0, [sp, #15] 67; CHECK-NEXT: vldr d0, [sp, #8] 68; CHECK-NEXT: add sp, #16 69; CHECK-NEXT: bx lr 70entry: 71 %0 = fsub nnan ninf nsz <2 x double> <double 0.0e0, double 0.0e0>, %src 72 ret <2 x double> %0 73} 74 75define arm_aapcs_vfpcc <8 x half> @fabs_float16_t(<8 x half> %src) { 76; CHECK-MVE-LABEL: fabs_float16_t: 77; CHECK-MVE: @ %bb.0: @ %entry 78; CHECK-MVE-NEXT: vmovx.f16 s4, s0 79; CHECK-MVE-NEXT: vabs.f16 s0, s0 80; CHECK-MVE-NEXT: vabs.f16 s4, s4 81; CHECK-MVE-NEXT: vins.f16 s0, s4 82; CHECK-MVE-NEXT: vmovx.f16 s4, s1 83; CHECK-MVE-NEXT: vabs.f16 s4, s4 84; CHECK-MVE-NEXT: vabs.f16 s1, s1 85; CHECK-MVE-NEXT: vins.f16 s1, s4 86; CHECK-MVE-NEXT: vmovx.f16 s4, s2 87; CHECK-MVE-NEXT: vabs.f16 s4, s4 88; CHECK-MVE-NEXT: vabs.f16 s2, s2 89; CHECK-MVE-NEXT: vins.f16 s2, s4 90; CHECK-MVE-NEXT: vmovx.f16 s4, s3 91; CHECK-MVE-NEXT: vabs.f16 s4, s4 92; CHECK-MVE-NEXT: vabs.f16 s3, s3 93; CHECK-MVE-NEXT: vins.f16 s3, s4 94; CHECK-MVE-NEXT: bx lr 95; 96; CHECK-MVEFP-LABEL: fabs_float16_t: 97; CHECK-MVEFP: @ %bb.0: @ %entry 98; CHECK-MVEFP-NEXT: vabs.f16 q0, q0 99; CHECK-MVEFP-NEXT: bx lr 100entry: 101 %0 = call nnan ninf nsz <8 x half> @llvm.fabs.v8f16(<8 x half> %src) 102 ret <8 x half> %0 103} 104 105define arm_aapcs_vfpcc <4 x float> @fabs_float32_t(<4 x float> %src) { 106; CHECK-MVE-LABEL: fabs_float32_t: 107; CHECK-MVE: @ %bb.0: @ %entry 108; CHECK-MVE-NEXT: vabs.f32 s3, s3 109; CHECK-MVE-NEXT: vabs.f32 s2, s2 110; CHECK-MVE-NEXT: vabs.f32 s1, s1 111; CHECK-MVE-NEXT: vabs.f32 s0, s0 112; CHECK-MVE-NEXT: bx lr 113; 114; CHECK-MVEFP-LABEL: fabs_float32_t: 115; CHECK-MVEFP: @ %bb.0: @ %entry 116; CHECK-MVEFP-NEXT: vabs.f32 q0, q0 117; CHECK-MVEFP-NEXT: bx lr 118entry: 119 %0 = call nnan ninf nsz <4 x float> @llvm.fabs.v4f32(<4 x float> %src) 120 ret <4 x float> %0 121} 122 123define arm_aapcs_vfpcc <2 x double> @fabs_float64_t(<2 x double> %src) { 124; CHECK-LABEL: fabs_float64_t: 125; CHECK: @ %bb.0: @ %entry 126; CHECK-NEXT: vldr d2, .LCPI5_0 127; CHECK-NEXT: vmov r12, r3, d0 128; CHECK-NEXT: vmov r0, r1, d2 129; CHECK-NEXT: vmov r0, r2, d1 130; CHECK-NEXT: lsrs r1, r1, #31 131; CHECK-NEXT: bfi r2, r1, #31, #1 132; CHECK-NEXT: bfi r3, r1, #31, #1 133; CHECK-NEXT: vmov d1, r0, r2 134; CHECK-NEXT: vmov d0, r12, r3 135; CHECK-NEXT: bx lr 136; CHECK-NEXT: .p2align 3 137; CHECK-NEXT: @ %bb.1: 138; CHECK-NEXT: .LCPI5_0: 139; CHECK-NEXT: .long 0 @ double 0 140; CHECK-NEXT: .long 0 141entry: 142 %0 = call nnan ninf nsz <2 x double> @llvm.fabs.v2f64(<2 x double> %src) 143 ret <2 x double> %0 144} 145 146declare <4 x float> @llvm.fabs.v4f32(<4 x float>) 147declare <8 x half> @llvm.fabs.v8f16(<8 x half>) 148declare <2 x double> @llvm.fabs.v2f64(<2 x double>) 149 150