Lines Matching full:s4
22 ; GFX7CHECK-NEXT: s_and_b32 s4, s6, 0x7fff
23 ; GFX7CHECK-NEXT: s_cmpk_gt_i32 s4, 0x7f80
164 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7fc0
165 ; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
166 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
167 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e64 s[4:5], s4, v0
176 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7fc0
177 ; GFX8CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
178 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
179 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e64 s[4:5], s4, v0
188 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7fc0
189 ; GFX9CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
190 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
191 ; GFX9CHECK-NEXT: v_cmp_lt_i16_e64 s[4:5], s4, v0
201 ; GFX10CHECK-NEXT: v_cmp_lt_i16_e64 s4, 0x7f80, v0
202 ; GFX10CHECK-NEXT: s_and_b32 s4, s4, vcc_lo
203 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
225 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7fbf
226 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
234 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7fbf
235 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
243 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7fbf
244 ; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
273 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
274 ; GFX7CHECK-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
281 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
282 ; GFX8CHECK-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0
289 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
290 ; GFX9CHECK-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0
317 ; GFX7CHECK-NEXT: s_mov_b32 s4, 0xff80
318 ; GFX7CHECK-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
325 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0xff80
326 ; GFX8CHECK-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0
333 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0xff80
334 ; GFX9CHECK-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0
377 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f00
378 ; GFX8CHECK-NEXT: v_cmp_gt_u16_e64 s[4:5], s4, v0
389 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f00
390 ; GFX9CHECK-NEXT: v_cmp_gt_u16_e64 s[4:5], s4, v0
401 ; GFX10CHECK-NEXT: v_cmp_gt_u16_e64 s4, 0x7f00, v1
402 ; GFX10CHECK-NEXT: s_and_b32 s4, s4, vcc_lo
403 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
442 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f00
443 ; GFX8CHECK-NEXT: v_cmp_gt_u16_e64 s[4:5], s4, v0
454 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f00
455 ; GFX9CHECK-NEXT: v_cmp_gt_u16_e64 s[4:5], s4, v0
466 ; GFX10CHECK-NEXT: v_cmp_gt_u16_e64 s4, 0x7f00, v1
467 ; GFX10CHECK-NEXT: s_and_b32 s4, s4, vcc_lo
468 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
493 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f
494 ; GFX7CHECK-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
502 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f
503 ; GFX8CHECK-NEXT: v_cmp_gt_u16_e32 vcc, s4, v0
511 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f
512 ; GFX9CHECK-NEXT: v_cmp_gt_u16_e32 vcc, s4, v0
543 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f
545 ; GFX7CHECK-NEXT: v_cmp_gt_u32_e64 s[4:5], s4, v0
556 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f
557 ; GFX8CHECK-NEXT: v_cmp_gt_u16_e64 s[4:5], s4, v0
568 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f
569 ; GFX9CHECK-NEXT: v_cmp_gt_u16_e64 s[4:5], s4, v0
580 ; GFX10CHECK-NEXT: v_cmp_gt_u16_e64 s4, 0x7f, v1
581 ; GFX10CHECK-NEXT: s_and_b32 s4, s4, vcc_lo
582 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
646 ; GFX7CHECK-NEXT: s_mov_b32 s4, 0x8000
647 ; GFX7CHECK-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
654 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x8000
655 ; GFX8CHECK-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0
662 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x8000
663 ; GFX9CHECK-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0
690 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
691 ; GFX7CHECK-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
698 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
699 ; GFX8CHECK-NEXT: v_cmp_gt_u16_e32 vcc, s4, v0
706 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
707 ; GFX9CHECK-NEXT: v_cmp_gt_u16_e32 vcc, s4, v0
735 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
737 ; GFX7CHECK-NEXT: v_cmp_gt_i32_e64 s[4:5], s4, v0
747 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
748 ; GFX8CHECK-NEXT: v_cmp_gt_i16_e64 s[4:5], s4, v0
758 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
759 ; GFX9CHECK-NEXT: v_cmp_gt_i16_e64 s[4:5], s4, v0
769 ; GFX10CHECK-NEXT: v_cmp_gt_i16_e64 s4, 0x7f80, v1
770 ; GFX10CHECK-NEXT: s_and_b32 s4, s4, vcc_lo
771 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
793 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
794 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
802 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
803 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
811 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
812 ; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
841 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f81
842 ; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
850 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f81
851 ; GFX8CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
859 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f81
860 ; GFX9CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
889 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
892 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
894 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v1
902 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
904 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
906 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v1
914 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
915 ; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v1
916 ; GFX9CHECK-NEXT: v_cmp_gt_i16_sdwa s[4:5], v1, s4 src0_sel:WORD_1 src1_sel:DWORD
927 ; GFX10CHECK-NEXT: v_cmp_gt_i16_sdwa s4, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
929 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
952 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
956 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
959 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v1
961 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v2
969 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
972 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
974 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v1
976 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v2
984 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
986 ; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v3
988 ; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v1
989 ; GFX9CHECK-NEXT: v_cmp_gt_i16_sdwa s[4:5], v3, s4 src0_sel:WORD_1 src1_sel:DWORD
1001 ; GFX10CHECK-NEXT: v_cmp_gt_i16_sdwa s4, v2, v3 src0_sel:WORD_1 src1_sel:DWORD
1004 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
1031 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
1035 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
1039 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v1
1042 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v2
1044 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v3
1052 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
1056 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
1058 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v1
1060 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v2
1062 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v3
1089 ; GFX10CHECK-NEXT: v_cmp_gt_i16_sdwa s4, v3, v5 src0_sel:WORD_1 src1_sel:DWORD
1092 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
1093 ; GFX10CHECK-NEXT: v_cmp_gt_i16_sdwa s4, v4, v5 src0_sel:WORD_1 src1_sel:DWORD
1095 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
1130 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
1131 ; GFX7CHECK-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
1139 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
1140 ; GFX8CHECK-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0
1148 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
1149 ; GFX9CHECK-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0
1178 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
1179 ; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
1187 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
1188 ; GFX8CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
1196 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
1197 ; GFX9CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
1322 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f00
1323 ; GFX7CHECK-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
1332 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f00
1333 ; GFX8CHECK-NEXT: v_cmp_gt_u16_e32 vcc, s4, v0
1342 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f00
1343 ; GFX9CHECK-NEXT: v_cmp_gt_u16_e32 vcc, s4, v0
1376 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7eff
1377 ; GFX7CHECK-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
1386 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7eff
1387 ; GFX8CHECK-NEXT: v_cmp_lt_u16_e32 vcc, s4, v0
1396 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7eff
1397 ; GFX9CHECK-NEXT: v_cmp_lt_u16_e32 vcc, s4, v0
1444 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7eff
1445 ; GFX8CHECK-NEXT: v_cmp_lt_u16_e64 s[4:5], s4, v0
1456 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7eff
1457 ; GFX9CHECK-NEXT: v_cmp_lt_u16_e64 s[4:5], s4, v0
1468 ; GFX10CHECK-NEXT: v_cmp_lt_u16_e64 s4, 0x7eff, v1
1469 ; GFX10CHECK-NEXT: s_or_b32 s4, s4, vcc_lo
1470 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
1509 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7eff
1510 ; GFX8CHECK-NEXT: v_cmp_lt_u16_e64 s[4:5], s4, v0
1521 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7eff
1522 ; GFX9CHECK-NEXT: v_cmp_lt_u16_e64 s[4:5], s4, v0
1533 ; GFX10CHECK-NEXT: v_cmp_lt_u16_e64 s4, 0x7eff, v1
1534 ; GFX10CHECK-NEXT: s_or_b32 s4, s4, vcc_lo
1535 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
1559 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f
1560 ; GFX7CHECK-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
1569 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f
1570 ; GFX8CHECK-NEXT: v_cmp_gt_u16_e32 vcc, s4, v0
1579 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f
1580 ; GFX9CHECK-NEXT: v_cmp_gt_u16_e32 vcc, s4, v0
1612 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7e
1613 ; GFX7CHECK-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
1622 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7e
1623 ; GFX8CHECK-NEXT: v_cmp_lt_u16_e32 vcc, s4, v0
1632 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7e
1633 ; GFX9CHECK-NEXT: v_cmp_lt_u16_e32 vcc, s4, v0
1754 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f81
1755 ; GFX7CHECK-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
1762 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f81
1763 ; GFX8CHECK-NEXT: v_cmp_gt_u16_e32 vcc, s4, v0
1770 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f81
1771 ; GFX9CHECK-NEXT: v_cmp_gt_u16_e32 vcc, s4, v0
1850 ; GFX10CHECK-NEXT: v_cmp_gt_i16_e64 s4, 0x7f80, v1
1852 ; GFX10CHECK-NEXT: s_and_b32 s4, s4, vcc_lo
1853 ; GFX10CHECK-NEXT: s_or_b32 s4, s4, s5
1854 ; GFX10CHECK-NEXT: s_or_b32 s4, s4, s6
1855 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
1883 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
1885 ; GFX7CHECK-NEXT: v_cmp_gt_i32_e64 s[4:5], s4, v0
1897 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
1899 ; GFX8CHECK-NEXT: v_cmp_gt_i16_e64 s[4:5], s4, v1
1911 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
1913 ; GFX9CHECK-NEXT: v_cmp_gt_i16_e64 s[4:5], s4, v1
1927 ; GFX10CHECK-NEXT: v_cmp_gt_i16_e64 s4, 0x7f80, v1
1928 ; GFX10CHECK-NEXT: s_and_b32 s4, s4, vcc_lo
1929 ; GFX10CHECK-NEXT: s_or_b32 s4, s4, s5
1930 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
1955 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
1956 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
1957 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f81
1958 ; GFX7CHECK-NEXT: v_cmp_gt_u32_e64 s[4:5], s4, v1
1966 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f81
1967 ; GFX8CHECK-NEXT: v_cmp_gt_u16_e32 vcc, s4, v0
1969 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
1970 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e64 s[4:5], s4, v0
1978 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f81
1979 ; GFX9CHECK-NEXT: v_cmp_gt_u16_e32 vcc, s4, v0
1981 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
1982 ; GFX9CHECK-NEXT: v_cmp_lt_i16_e64 s[4:5], s4, v0
1992 ; GFX10CHECK-NEXT: v_cmp_lt_i16_e64 s4, 0x7f80, v1
1993 ; GFX10CHECK-NEXT: s_or_b32 s4, vcc_lo, s4
1994 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2016 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
2017 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
2027 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
2028 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
2038 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
2039 ; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
2050 ; GFX10CHECK-NEXT: v_cmp_eq_u16_e64 s4, 0, v0
2051 ; GFX10CHECK-NEXT: s_or_b32 s4, s4, vcc_lo
2052 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2075 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
2076 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
2086 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
2087 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
2097 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
2098 ; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
2109 ; GFX10CHECK-NEXT: v_cmp_eq_u16_e64 s4, 0, v0
2110 ; GFX10CHECK-NEXT: s_or_b32 s4, s4, vcc_lo
2111 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2134 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
2135 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
2145 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
2146 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
2156 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
2157 ; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
2168 ; GFX10CHECK-NEXT: v_cmp_eq_u16_e64 s4, 0, v0
2169 ; GFX10CHECK-NEXT: s_or_b32 s4, s4, vcc_lo
2170 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2193 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f81
2194 ; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
2204 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f81
2205 ; GFX8CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
2215 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f81
2216 ; GFX9CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
2227 ; GFX10CHECK-NEXT: v_cmp_ne_u16_e64 s4, 0, v0
2228 ; GFX10CHECK-NEXT: s_and_b32 s4, s4, vcc_lo
2229 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2252 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f81
2253 ; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
2263 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f81
2264 ; GFX8CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
2274 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f81
2275 ; GFX9CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
2286 ; GFX10CHECK-NEXT: v_cmp_ne_u16_e64 s4, 0, v0
2287 ; GFX10CHECK-NEXT: s_and_b32 s4, s4, vcc_lo
2288 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2311 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f81
2312 ; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
2322 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f81
2323 ; GFX8CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
2333 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f81
2334 ; GFX9CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
2345 ; GFX10CHECK-NEXT: v_cmp_ne_u16_e64 s4, 0, v0
2346 ; GFX10CHECK-NEXT: s_and_b32 s4, s4, vcc_lo
2347 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2370 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7fbf
2371 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
2381 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7fbf
2382 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
2392 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7fbf
2393 ; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
2404 ; GFX10CHECK-NEXT: v_cmp_eq_u16_e64 s4, 0, v0
2405 ; GFX10CHECK-NEXT: s_or_b32 s4, s4, vcc_lo
2406 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2429 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7fc0
2430 ; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
2431 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
2432 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e64 s[4:5], s4, v0
2443 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7fc0
2444 ; GFX8CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
2445 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
2446 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e64 s[4:5], s4, v0
2457 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7fc0
2458 ; GFX9CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
2459 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
2460 ; GFX9CHECK-NEXT: v_cmp_lt_i16_e64 s[4:5], s4, v0
2472 ; GFX10CHECK-NEXT: v_cmp_lt_i16_e64 s4, 0x7f80, v0
2474 ; GFX10CHECK-NEXT: s_and_b32 s4, s4, vcc_lo
2475 ; GFX10CHECK-NEXT: s_or_b32 s4, s5, s4
2476 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2501 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7fc0
2503 ; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
2507 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f
2509 ; GFX7CHECK-NEXT: v_cmp_gt_u32_e64 s[4:5], s4, v1
2524 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7fc0
2526 ; GFX8CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
2530 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f
2532 ; GFX8CHECK-NEXT: v_cmp_gt_u16_e64 s[4:5], s4, v1
2546 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7fc0
2548 ; GFX9CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
2552 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f
2554 ; GFX9CHECK-NEXT: v_cmp_gt_u16_e64 s[4:5], s4, v1
2570 ; GFX10CHECK-NEXT: v_cmp_lt_i16_e64 s4, 0x7f80, v0
2574 ; GFX10CHECK-NEXT: s_and_b32 s4, s4, vcc_lo
2577 ; GFX10CHECK-NEXT: s_or_b32 s4, s5, s4
2578 ; GFX10CHECK-NEXT: s_or_b32 s4, s4, vcc_lo
2579 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2610 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
2611 ; GFX7CHECK-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
2613 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f
2614 ; GFX7CHECK-NEXT: v_cmp_gt_u32_e64 s[4:5], s4, v1
2631 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
2632 ; GFX8CHECK-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0
2634 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f
2635 ; GFX8CHECK-NEXT: v_cmp_gt_u16_e64 s[4:5], s4, v1
2651 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
2652 ; GFX9CHECK-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0
2654 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f
2655 ; GFX9CHECK-NEXT: v_cmp_gt_u16_e64 s[4:5], s4, v1
2675 ; GFX10CHECK-NEXT: v_cmp_gt_u16_e64 s4, 0x7f, v1
2677 ; GFX10CHECK-NEXT: s_or_b32 s4, s4, vcc_lo
2678 ; GFX10CHECK-NEXT: s_or_b32 s4, s4, s5
2679 ; GFX10CHECK-NEXT: s_or_b32 s4, s4, s6
2680 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2709 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f7f
2710 ; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
2718 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f7f
2719 ; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
2727 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f7f
2728 ; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
2758 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
2759 ; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
2767 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
2768 ; GFX8CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
2776 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
2777 ; GFX9CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
2807 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
2808 ; GFX7CHECK-NEXT: v_cmp_ne_u32_e32 vcc, s4, v0
2816 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
2817 ; GFX8CHECK-NEXT: v_cmp_ne_u16_e32 vcc, s4, v0
2825 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
2826 ; GFX9CHECK-NEXT: v_cmp_ne_u16_e32 vcc, s4, v0
2856 ; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
2857 ; GFX7CHECK-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
2865 ; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
2866 ; GFX8CHECK-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0
2874 ; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
2875 ; GFX9CHECK-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0