xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll (revision e0ed0333f0fed2e73f805afd58b61176a87aa3ad) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE
3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVEFP
4
5define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
6; CHECK-MVE-LABEL: vcmp_oeq_v4f32:
7; CHECK-MVE:       @ %bb.0: @ %entry
8; CHECK-MVE-NEXT:    vcmp.f32 s0, s4
9; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
10; CHECK-MVE-NEXT:    vcmp.f32 s3, s7
11; CHECK-MVE-NEXT:    cset r0, eq
12; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
13; CHECK-MVE-NEXT:    vcmp.f32 s1, s5
14; CHECK-MVE-NEXT:    cset r1, eq
15; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
16; CHECK-MVE-NEXT:    vcmp.f32 s2, s6
17; CHECK-MVE-NEXT:    cset r2, eq
18; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
19; CHECK-MVE-NEXT:    cset r3, eq
20; CHECK-MVE-NEXT:    cmp r3, #0
21; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10
22; CHECK-MVE-NEXT:    cmp r2, #0
23; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9
24; CHECK-MVE-NEXT:    cmp r1, #0
25; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11
26; CHECK-MVE-NEXT:    cmp r0, #0
27; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8
28; CHECK-MVE-NEXT:    bx lr
29;
30; CHECK-MVEFP-LABEL: vcmp_oeq_v4f32:
31; CHECK-MVEFP:       @ %bb.0: @ %entry
32; CHECK-MVEFP-NEXT:    vcmp.f32 eq, q0, q1
33; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
34; CHECK-MVEFP-NEXT:    bx lr
35entry:
36  %c = fcmp oeq <4 x float> %src, %src2
37  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
38  ret <4 x float> %s
39}
40
41define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
42; CHECK-MVE-LABEL: vcmp_one_v4f32:
43; CHECK-MVE:       @ %bb.0: @ %entry
44; CHECK-MVE-NEXT:    vcmp.f32 s0, s4
45; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
46; CHECK-MVE-NEXT:    vcmp.f32 s3, s7
47; CHECK-MVE-NEXT:    cset r0, mi
48; CHECK-MVE-NEXT:    csinc r0, r0, zr, le
49; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
50; CHECK-MVE-NEXT:    vcmp.f32 s1, s5
51; CHECK-MVE-NEXT:    cset r1, mi
52; CHECK-MVE-NEXT:    csinc r1, r1, zr, le
53; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
54; CHECK-MVE-NEXT:    vcmp.f32 s2, s6
55; CHECK-MVE-NEXT:    cset r2, mi
56; CHECK-MVE-NEXT:    csinc r2, r2, zr, le
57; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
58; CHECK-MVE-NEXT:    cset r3, mi
59; CHECK-MVE-NEXT:    csinc r3, r3, zr, le
60; CHECK-MVE-NEXT:    cmp r3, #0
61; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10
62; CHECK-MVE-NEXT:    cmp r2, #0
63; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9
64; CHECK-MVE-NEXT:    cmp r1, #0
65; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11
66; CHECK-MVE-NEXT:    cmp r0, #0
67; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8
68; CHECK-MVE-NEXT:    bx lr
69;
70; CHECK-MVEFP-LABEL: vcmp_one_v4f32:
71; CHECK-MVEFP:       @ %bb.0: @ %entry
72; CHECK-MVEFP-NEXT:    vpt.f32 le, q1, q0
73; CHECK-MVEFP-NEXT:    vcmpt.f32 le, q0, q1
74; CHECK-MVEFP-NEXT:    vpsel q0, q3, q2
75; CHECK-MVEFP-NEXT:    bx lr
76entry:
77  %c = fcmp one <4 x float> %src, %src2
78  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
79  ret <4 x float> %s
80}
81
82define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
83; CHECK-MVE-LABEL: vcmp_ogt_v4f32:
84; CHECK-MVE:       @ %bb.0: @ %entry
85; CHECK-MVE-NEXT:    vcmp.f32 s0, s4
86; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
87; CHECK-MVE-NEXT:    vcmp.f32 s3, s7
88; CHECK-MVE-NEXT:    cset r0, gt
89; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
90; CHECK-MVE-NEXT:    vcmp.f32 s1, s5
91; CHECK-MVE-NEXT:    cset r1, gt
92; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
93; CHECK-MVE-NEXT:    vcmp.f32 s2, s6
94; CHECK-MVE-NEXT:    cset r2, gt
95; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
96; CHECK-MVE-NEXT:    cset r3, gt
97; CHECK-MVE-NEXT:    cmp r3, #0
98; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10
99; CHECK-MVE-NEXT:    cmp r2, #0
100; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9
101; CHECK-MVE-NEXT:    cmp r1, #0
102; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11
103; CHECK-MVE-NEXT:    cmp r0, #0
104; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8
105; CHECK-MVE-NEXT:    bx lr
106;
107; CHECK-MVEFP-LABEL: vcmp_ogt_v4f32:
108; CHECK-MVEFP:       @ %bb.0: @ %entry
109; CHECK-MVEFP-NEXT:    vcmp.f32 gt, q0, q1
110; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
111; CHECK-MVEFP-NEXT:    bx lr
112entry:
113  %c = fcmp ogt <4 x float> %src, %src2
114  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
115  ret <4 x float> %s
116}
117
118define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
119; CHECK-MVE-LABEL: vcmp_oge_v4f32:
120; CHECK-MVE:       @ %bb.0: @ %entry
121; CHECK-MVE-NEXT:    vcmp.f32 s0, s4
122; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
123; CHECK-MVE-NEXT:    vcmp.f32 s3, s7
124; CHECK-MVE-NEXT:    cset r0, ge
125; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
126; CHECK-MVE-NEXT:    vcmp.f32 s1, s5
127; CHECK-MVE-NEXT:    cset r1, ge
128; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
129; CHECK-MVE-NEXT:    vcmp.f32 s2, s6
130; CHECK-MVE-NEXT:    cset r2, ge
131; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
132; CHECK-MVE-NEXT:    cset r3, ge
133; CHECK-MVE-NEXT:    cmp r3, #0
134; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10
135; CHECK-MVE-NEXT:    cmp r2, #0
136; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9
137; CHECK-MVE-NEXT:    cmp r1, #0
138; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11
139; CHECK-MVE-NEXT:    cmp r0, #0
140; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8
141; CHECK-MVE-NEXT:    bx lr
142;
143; CHECK-MVEFP-LABEL: vcmp_oge_v4f32:
144; CHECK-MVEFP:       @ %bb.0: @ %entry
145; CHECK-MVEFP-NEXT:    vcmp.f32 ge, q0, q1
146; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
147; CHECK-MVEFP-NEXT:    bx lr
148entry:
149  %c = fcmp oge <4 x float> %src, %src2
150  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
151  ret <4 x float> %s
152}
153
154define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
155; CHECK-MVE-LABEL: vcmp_olt_v4f32:
156; CHECK-MVE:       @ %bb.0: @ %entry
157; CHECK-MVE-NEXT:    vcmp.f32 s0, s4
158; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
159; CHECK-MVE-NEXT:    vcmp.f32 s3, s7
160; CHECK-MVE-NEXT:    cset r0, mi
161; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
162; CHECK-MVE-NEXT:    vcmp.f32 s1, s5
163; CHECK-MVE-NEXT:    cset r1, mi
164; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
165; CHECK-MVE-NEXT:    vcmp.f32 s2, s6
166; CHECK-MVE-NEXT:    cset r2, mi
167; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
168; CHECK-MVE-NEXT:    cset r3, mi
169; CHECK-MVE-NEXT:    cmp r3, #0
170; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10
171; CHECK-MVE-NEXT:    cmp r2, #0
172; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9
173; CHECK-MVE-NEXT:    cmp r1, #0
174; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11
175; CHECK-MVE-NEXT:    cmp r0, #0
176; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8
177; CHECK-MVE-NEXT:    bx lr
178;
179; CHECK-MVEFP-LABEL: vcmp_olt_v4f32:
180; CHECK-MVEFP:       @ %bb.0: @ %entry
181; CHECK-MVEFP-NEXT:    vcmp.f32 gt, q1, q0
182; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
183; CHECK-MVEFP-NEXT:    bx lr
184entry:
185  %c = fcmp olt <4 x float> %src, %src2
186  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
187  ret <4 x float> %s
188}
189
190define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
191; CHECK-MVE-LABEL: vcmp_ole_v4f32:
192; CHECK-MVE:       @ %bb.0: @ %entry
193; CHECK-MVE-NEXT:    vcmp.f32 s0, s4
194; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
195; CHECK-MVE-NEXT:    vcmp.f32 s3, s7
196; CHECK-MVE-NEXT:    cset r0, ls
197; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
198; CHECK-MVE-NEXT:    vcmp.f32 s1, s5
199; CHECK-MVE-NEXT:    cset r1, ls
200; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
201; CHECK-MVE-NEXT:    vcmp.f32 s2, s6
202; CHECK-MVE-NEXT:    cset r2, ls
203; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
204; CHECK-MVE-NEXT:    cset r3, ls
205; CHECK-MVE-NEXT:    cmp r3, #0
206; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10
207; CHECK-MVE-NEXT:    cmp r2, #0
208; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9
209; CHECK-MVE-NEXT:    cmp r1, #0
210; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11
211; CHECK-MVE-NEXT:    cmp r0, #0
212; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8
213; CHECK-MVE-NEXT:    bx lr
214;
215; CHECK-MVEFP-LABEL: vcmp_ole_v4f32:
216; CHECK-MVEFP:       @ %bb.0: @ %entry
217; CHECK-MVEFP-NEXT:    vcmp.f32 ge, q1, q0
218; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
219; CHECK-MVEFP-NEXT:    bx lr
220entry:
221  %c = fcmp ole <4 x float> %src, %src2
222  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
223  ret <4 x float> %s
224}
225
226define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
227; CHECK-MVE-LABEL: vcmp_ueq_v4f32:
228; CHECK-MVE:       @ %bb.0: @ %entry
229; CHECK-MVE-NEXT:    vcmp.f32 s0, s4
230; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
231; CHECK-MVE-NEXT:    vcmp.f32 s3, s7
232; CHECK-MVE-NEXT:    cset r0, eq
233; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc
234; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
235; CHECK-MVE-NEXT:    vcmp.f32 s1, s5
236; CHECK-MVE-NEXT:    cset r1, eq
237; CHECK-MVE-NEXT:    csinc r1, r1, zr, vc
238; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
239; CHECK-MVE-NEXT:    vcmp.f32 s2, s6
240; CHECK-MVE-NEXT:    cset r2, eq
241; CHECK-MVE-NEXT:    csinc r2, r2, zr, vc
242; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
243; CHECK-MVE-NEXT:    cset r3, eq
244; CHECK-MVE-NEXT:    csinc r3, r3, zr, vc
245; CHECK-MVE-NEXT:    cmp r3, #0
246; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10
247; CHECK-MVE-NEXT:    cmp r2, #0
248; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9
249; CHECK-MVE-NEXT:    cmp r1, #0
250; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11
251; CHECK-MVE-NEXT:    cmp r0, #0
252; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8
253; CHECK-MVE-NEXT:    bx lr
254;
255; CHECK-MVEFP-LABEL: vcmp_ueq_v4f32:
256; CHECK-MVEFP:       @ %bb.0: @ %entry
257; CHECK-MVEFP-NEXT:    vpt.f32 le, q1, q0
258; CHECK-MVEFP-NEXT:    vcmpt.f32 le, q0, q1
259; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
260; CHECK-MVEFP-NEXT:    bx lr
261entry:
262  %c = fcmp ueq <4 x float> %src, %src2
263  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
264  ret <4 x float> %s
265}
266
267define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
268; CHECK-MVE-LABEL: vcmp_une_v4f32:
269; CHECK-MVE:       @ %bb.0: @ %entry
270; CHECK-MVE-NEXT:    vcmp.f32 s2, s6
271; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
272; CHECK-MVE-NEXT:    vcmp.f32 s1, s5
273; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10
274; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
275; CHECK-MVE-NEXT:    vcmp.f32 s3, s7
276; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9
277; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
278; CHECK-MVE-NEXT:    vcmp.f32 s0, s4
279; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11
280; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
281; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8
282; CHECK-MVE-NEXT:    bx lr
283;
284; CHECK-MVEFP-LABEL: vcmp_une_v4f32:
285; CHECK-MVEFP:       @ %bb.0: @ %entry
286; CHECK-MVEFP-NEXT:    vcmp.f32 ne, q0, q1
287; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
288; CHECK-MVEFP-NEXT:    bx lr
289entry:
290  %c = fcmp une <4 x float> %src, %src2
291  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
292  ret <4 x float> %s
293}
294
295define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
296; CHECK-MVE-LABEL: vcmp_ugt_v4f32:
297; CHECK-MVE:       @ %bb.0: @ %entry
298; CHECK-MVE-NEXT:    vcmp.f32 s0, s4
299; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
300; CHECK-MVE-NEXT:    vcmp.f32 s3, s7
301; CHECK-MVE-NEXT:    cset r0, hi
302; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
303; CHECK-MVE-NEXT:    vcmp.f32 s1, s5
304; CHECK-MVE-NEXT:    cset r1, hi
305; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
306; CHECK-MVE-NEXT:    vcmp.f32 s2, s6
307; CHECK-MVE-NEXT:    cset r2, hi
308; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
309; CHECK-MVE-NEXT:    cset r3, hi
310; CHECK-MVE-NEXT:    cmp r3, #0
311; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10
312; CHECK-MVE-NEXT:    cmp r2, #0
313; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9
314; CHECK-MVE-NEXT:    cmp r1, #0
315; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11
316; CHECK-MVE-NEXT:    cmp r0, #0
317; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8
318; CHECK-MVE-NEXT:    bx lr
319;
320; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32:
321; CHECK-MVEFP:       @ %bb.0: @ %entry
322; CHECK-MVEFP-NEXT:    vcmp.f32 lt, q1, q0
323; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
324; CHECK-MVEFP-NEXT:    bx lr
325entry:
326  %c = fcmp ugt <4 x float> %src, %src2
327  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
328  ret <4 x float> %s
329}
330
331define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
332; CHECK-MVE-LABEL: vcmp_uge_v4f32:
333; CHECK-MVE:       @ %bb.0: @ %entry
334; CHECK-MVE-NEXT:    vcmp.f32 s0, s4
335; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
336; CHECK-MVE-NEXT:    vcmp.f32 s3, s7
337; CHECK-MVE-NEXT:    cset r0, pl
338; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
339; CHECK-MVE-NEXT:    vcmp.f32 s1, s5
340; CHECK-MVE-NEXT:    cset r1, pl
341; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
342; CHECK-MVE-NEXT:    vcmp.f32 s2, s6
343; CHECK-MVE-NEXT:    cset r2, pl
344; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
345; CHECK-MVE-NEXT:    cset r3, pl
346; CHECK-MVE-NEXT:    cmp r3, #0
347; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10
348; CHECK-MVE-NEXT:    cmp r2, #0
349; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9
350; CHECK-MVE-NEXT:    cmp r1, #0
351; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11
352; CHECK-MVE-NEXT:    cmp r0, #0
353; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8
354; CHECK-MVE-NEXT:    bx lr
355;
356; CHECK-MVEFP-LABEL: vcmp_uge_v4f32:
357; CHECK-MVEFP:       @ %bb.0: @ %entry
358; CHECK-MVEFP-NEXT:    vcmp.f32 le, q1, q0
359; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
360; CHECK-MVEFP-NEXT:    bx lr
361entry:
362  %c = fcmp uge <4 x float> %src, %src2
363  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
364  ret <4 x float> %s
365}
366
367define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
368; CHECK-MVE-LABEL: vcmp_ult_v4f32:
369; CHECK-MVE:       @ %bb.0: @ %entry
370; CHECK-MVE-NEXT:    vcmp.f32 s0, s4
371; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
372; CHECK-MVE-NEXT:    vcmp.f32 s3, s7
373; CHECK-MVE-NEXT:    cset r0, lt
374; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
375; CHECK-MVE-NEXT:    vcmp.f32 s1, s5
376; CHECK-MVE-NEXT:    cset r1, lt
377; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
378; CHECK-MVE-NEXT:    vcmp.f32 s2, s6
379; CHECK-MVE-NEXT:    cset r2, lt
380; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
381; CHECK-MVE-NEXT:    cset r3, lt
382; CHECK-MVE-NEXT:    cmp r3, #0
383; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10
384; CHECK-MVE-NEXT:    cmp r2, #0
385; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9
386; CHECK-MVE-NEXT:    cmp r1, #0
387; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11
388; CHECK-MVE-NEXT:    cmp r0, #0
389; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8
390; CHECK-MVE-NEXT:    bx lr
391;
392; CHECK-MVEFP-LABEL: vcmp_ult_v4f32:
393; CHECK-MVEFP:       @ %bb.0: @ %entry
394; CHECK-MVEFP-NEXT:    vcmp.f32 lt, q0, q1
395; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
396; CHECK-MVEFP-NEXT:    bx lr
397entry:
398  %c = fcmp ult <4 x float> %src, %src2
399  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
400  ret <4 x float> %s
401}
402
403define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
404; CHECK-MVE-LABEL: vcmp_ule_v4f32:
405; CHECK-MVE:       @ %bb.0: @ %entry
406; CHECK-MVE-NEXT:    vcmp.f32 s0, s4
407; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
408; CHECK-MVE-NEXT:    vcmp.f32 s3, s7
409; CHECK-MVE-NEXT:    cset r0, le
410; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
411; CHECK-MVE-NEXT:    vcmp.f32 s1, s5
412; CHECK-MVE-NEXT:    cset r1, le
413; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
414; CHECK-MVE-NEXT:    vcmp.f32 s2, s6
415; CHECK-MVE-NEXT:    cset r2, le
416; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
417; CHECK-MVE-NEXT:    cset r3, le
418; CHECK-MVE-NEXT:    cmp r3, #0
419; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10
420; CHECK-MVE-NEXT:    cmp r2, #0
421; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9
422; CHECK-MVE-NEXT:    cmp r1, #0
423; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11
424; CHECK-MVE-NEXT:    cmp r0, #0
425; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8
426; CHECK-MVE-NEXT:    bx lr
427;
428; CHECK-MVEFP-LABEL: vcmp_ule_v4f32:
429; CHECK-MVEFP:       @ %bb.0: @ %entry
430; CHECK-MVEFP-NEXT:    vcmp.f32 le, q0, q1
431; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
432; CHECK-MVEFP-NEXT:    bx lr
433entry:
434  %c = fcmp ule <4 x float> %src, %src2
435  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
436  ret <4 x float> %s
437}
438
439define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
440; CHECK-MVE-LABEL: vcmp_ord_v4f32:
441; CHECK-MVE:       @ %bb.0: @ %entry
442; CHECK-MVE-NEXT:    vcmp.f32 s0, s4
443; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
444; CHECK-MVE-NEXT:    vcmp.f32 s3, s7
445; CHECK-MVE-NEXT:    cset r0, vc
446; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
447; CHECK-MVE-NEXT:    vcmp.f32 s1, s5
448; CHECK-MVE-NEXT:    cset r1, vc
449; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
450; CHECK-MVE-NEXT:    vcmp.f32 s2, s6
451; CHECK-MVE-NEXT:    cset r2, vc
452; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
453; CHECK-MVE-NEXT:    cset r3, vc
454; CHECK-MVE-NEXT:    cmp r3, #0
455; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10
456; CHECK-MVE-NEXT:    cmp r2, #0
457; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9
458; CHECK-MVE-NEXT:    cmp r1, #0
459; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11
460; CHECK-MVE-NEXT:    cmp r0, #0
461; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8
462; CHECK-MVE-NEXT:    bx lr
463;
464; CHECK-MVEFP-LABEL: vcmp_ord_v4f32:
465; CHECK-MVEFP:       @ %bb.0: @ %entry
466; CHECK-MVEFP-NEXT:    vpt.f32 le, q1, q0
467; CHECK-MVEFP-NEXT:    vcmpt.f32 lt, q0, q1
468; CHECK-MVEFP-NEXT:    vpsel q0, q3, q2
469; CHECK-MVEFP-NEXT:    bx lr
470entry:
471  %c = fcmp ord <4 x float> %src, %src2
472  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
473  ret <4 x float> %s
474}
475
476define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
477; CHECK-MVE-LABEL: vcmp_uno_v4f32:
478; CHECK-MVE:       @ %bb.0: @ %entry
479; CHECK-MVE-NEXT:    vcmp.f32 s0, s4
480; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
481; CHECK-MVE-NEXT:    vcmp.f32 s3, s7
482; CHECK-MVE-NEXT:    cset r0, vs
483; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
484; CHECK-MVE-NEXT:    vcmp.f32 s1, s5
485; CHECK-MVE-NEXT:    cset r1, vs
486; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
487; CHECK-MVE-NEXT:    vcmp.f32 s2, s6
488; CHECK-MVE-NEXT:    cset r2, vs
489; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
490; CHECK-MVE-NEXT:    cset r3, vs
491; CHECK-MVE-NEXT:    cmp r3, #0
492; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10
493; CHECK-MVE-NEXT:    cmp r2, #0
494; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9
495; CHECK-MVE-NEXT:    cmp r1, #0
496; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11
497; CHECK-MVE-NEXT:    cmp r0, #0
498; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8
499; CHECK-MVE-NEXT:    bx lr
500;
501; CHECK-MVEFP-LABEL: vcmp_uno_v4f32:
502; CHECK-MVEFP:       @ %bb.0: @ %entry
503; CHECK-MVEFP-NEXT:    vpt.f32 le, q1, q0
504; CHECK-MVEFP-NEXT:    vcmpt.f32 lt, q0, q1
505; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
506; CHECK-MVEFP-NEXT:    bx lr
507entry:
508  %c = fcmp uno <4 x float> %src, %src2
509  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
510  ret <4 x float> %s
511}
512
513
514
515define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
516; CHECK-MVE-LABEL: vcmp_oeq_v8f16:
517; CHECK-MVE:       @ %bb.0: @ %entry
518; CHECK-MVE-NEXT:    .vsave {d8, d9}
519; CHECK-MVE-NEXT:    vpush {d8, d9}
520; CHECK-MVE-NEXT:    vmovx.f16 s16, s4
521; CHECK-MVE-NEXT:    vmovx.f16 s18, s0
522; CHECK-MVE-NEXT:    vcmp.f16 s18, s16
523; CHECK-MVE-NEXT:    vmovx.f16 s16, s8
524; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
525; CHECK-MVE-NEXT:    vcmp.f16 s0, s4
526; CHECK-MVE-NEXT:    vmovx.f16 s18, s12
527; CHECK-MVE-NEXT:    vmovx.f16 s4, s5
528; CHECK-MVE-NEXT:    cset r0, eq
529; CHECK-MVE-NEXT:    cmp r0, #0
530; CHECK-MVE-NEXT:    vseleq.f16 s16, s18, s16
531; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
532; CHECK-MVE-NEXT:    cset r0, eq
533; CHECK-MVE-NEXT:    cmp r0, #0
534; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8
535; CHECK-MVE-NEXT:    vmovx.f16 s8, s1
536; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
537; CHECK-MVE-NEXT:    vmovx.f16 s4, s9
538; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
539; CHECK-MVE-NEXT:    vmovx.f16 s8, s13
540; CHECK-MVE-NEXT:    vcmp.f16 s1, s5
541; CHECK-MVE-NEXT:    vins.f16 s0, s16
542; CHECK-MVE-NEXT:    cset r0, eq
543; CHECK-MVE-NEXT:    cmp r0, #0
544; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
545; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
546; CHECK-MVE-NEXT:    vmovx.f16 s8, s2
547; CHECK-MVE-NEXT:    cset r0, eq
548; CHECK-MVE-NEXT:    cmp r0, #0
549; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9
550; CHECK-MVE-NEXT:    vins.f16 s1, s4
551; CHECK-MVE-NEXT:    vmovx.f16 s4, s6
552; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
553; CHECK-MVE-NEXT:    vmovx.f16 s4, s10
554; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
555; CHECK-MVE-NEXT:    vcmp.f16 s2, s6
556; CHECK-MVE-NEXT:    vmovx.f16 s8, s14
557; CHECK-MVE-NEXT:    vmovx.f16 s6, s3
558; CHECK-MVE-NEXT:    cset r0, eq
559; CHECK-MVE-NEXT:    cmp r0, #0
560; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
561; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
562; CHECK-MVE-NEXT:    cset r0, eq
563; CHECK-MVE-NEXT:    cmp r0, #0
564; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10
565; CHECK-MVE-NEXT:    vins.f16 s2, s4
566; CHECK-MVE-NEXT:    vmovx.f16 s4, s7
567; CHECK-MVE-NEXT:    vcmp.f16 s6, s4
568; CHECK-MVE-NEXT:    vmovx.f16 s4, s11
569; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
570; CHECK-MVE-NEXT:    vmovx.f16 s6, s15
571; CHECK-MVE-NEXT:    vcmp.f16 s3, s7
572; CHECK-MVE-NEXT:    cset r0, eq
573; CHECK-MVE-NEXT:    cmp r0, #0
574; CHECK-MVE-NEXT:    vseleq.f16 s4, s6, s4
575; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
576; CHECK-MVE-NEXT:    cset r0, eq
577; CHECK-MVE-NEXT:    cmp r0, #0
578; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11
579; CHECK-MVE-NEXT:    vins.f16 s3, s4
580; CHECK-MVE-NEXT:    vpop {d8, d9}
581; CHECK-MVE-NEXT:    bx lr
582;
583; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16:
584; CHECK-MVEFP:       @ %bb.0: @ %entry
585; CHECK-MVEFP-NEXT:    vcmp.f16 eq, q0, q1
586; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
587; CHECK-MVEFP-NEXT:    bx lr
588entry:
589  %c = fcmp oeq <8 x half> %src, %src2
590  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
591  ret <8 x half> %s
592}
593
594define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
595; CHECK-MVE-LABEL: vcmp_one_v8f16:
596; CHECK-MVE:       @ %bb.0: @ %entry
597; CHECK-MVE-NEXT:    .vsave {d8, d9}
598; CHECK-MVE-NEXT:    vpush {d8, d9}
599; CHECK-MVE-NEXT:    vmovx.f16 s16, s4
600; CHECK-MVE-NEXT:    vmovx.f16 s18, s0
601; CHECK-MVE-NEXT:    vcmp.f16 s18, s16
602; CHECK-MVE-NEXT:    vmovx.f16 s16, s8
603; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
604; CHECK-MVE-NEXT:    vcmp.f16 s0, s4
605; CHECK-MVE-NEXT:    vmovx.f16 s18, s12
606; CHECK-MVE-NEXT:    vmovx.f16 s4, s5
607; CHECK-MVE-NEXT:    cset r0, mi
608; CHECK-MVE-NEXT:    csinc r0, r0, zr, le
609; CHECK-MVE-NEXT:    cmp r0, #0
610; CHECK-MVE-NEXT:    vseleq.f16 s16, s18, s16
611; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
612; CHECK-MVE-NEXT:    cset r0, mi
613; CHECK-MVE-NEXT:    csinc r0, r0, zr, le
614; CHECK-MVE-NEXT:    cmp r0, #0
615; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8
616; CHECK-MVE-NEXT:    vmovx.f16 s8, s1
617; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
618; CHECK-MVE-NEXT:    vmovx.f16 s4, s9
619; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
620; CHECK-MVE-NEXT:    vmovx.f16 s8, s13
621; CHECK-MVE-NEXT:    vcmp.f16 s1, s5
622; CHECK-MVE-NEXT:    vins.f16 s0, s16
623; CHECK-MVE-NEXT:    cset r0, mi
624; CHECK-MVE-NEXT:    csinc r0, r0, zr, le
625; CHECK-MVE-NEXT:    cmp r0, #0
626; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
627; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
628; CHECK-MVE-NEXT:    vmovx.f16 s8, s2
629; CHECK-MVE-NEXT:    cset r0, mi
630; CHECK-MVE-NEXT:    csinc r0, r0, zr, le
631; CHECK-MVE-NEXT:    cmp r0, #0
632; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9
633; CHECK-MVE-NEXT:    vins.f16 s1, s4
634; CHECK-MVE-NEXT:    vmovx.f16 s4, s6
635; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
636; CHECK-MVE-NEXT:    vmovx.f16 s4, s10
637; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
638; CHECK-MVE-NEXT:    vcmp.f16 s2, s6
639; CHECK-MVE-NEXT:    vmovx.f16 s8, s14
640; CHECK-MVE-NEXT:    vmovx.f16 s6, s3
641; CHECK-MVE-NEXT:    cset r0, mi
642; CHECK-MVE-NEXT:    csinc r0, r0, zr, le
643; CHECK-MVE-NEXT:    cmp r0, #0
644; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
645; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
646; CHECK-MVE-NEXT:    cset r0, mi
647; CHECK-MVE-NEXT:    csinc r0, r0, zr, le
648; CHECK-MVE-NEXT:    cmp r0, #0
649; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10
650; CHECK-MVE-NEXT:    vins.f16 s2, s4
651; CHECK-MVE-NEXT:    vmovx.f16 s4, s7
652; CHECK-MVE-NEXT:    vcmp.f16 s6, s4
653; CHECK-MVE-NEXT:    vmovx.f16 s4, s11
654; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
655; CHECK-MVE-NEXT:    vmovx.f16 s6, s15
656; CHECK-MVE-NEXT:    vcmp.f16 s3, s7
657; CHECK-MVE-NEXT:    cset r0, mi
658; CHECK-MVE-NEXT:    csinc r0, r0, zr, le
659; CHECK-MVE-NEXT:    cmp r0, #0
660; CHECK-MVE-NEXT:    vseleq.f16 s4, s6, s4
661; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
662; CHECK-MVE-NEXT:    cset r0, mi
663; CHECK-MVE-NEXT:    csinc r0, r0, zr, le
664; CHECK-MVE-NEXT:    cmp r0, #0
665; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11
666; CHECK-MVE-NEXT:    vins.f16 s3, s4
667; CHECK-MVE-NEXT:    vpop {d8, d9}
668; CHECK-MVE-NEXT:    bx lr
669;
670; CHECK-MVEFP-LABEL: vcmp_one_v8f16:
671; CHECK-MVEFP:       @ %bb.0: @ %entry
672; CHECK-MVEFP-NEXT:    vpt.f16 le, q1, q0
673; CHECK-MVEFP-NEXT:    vcmpt.f16 le, q0, q1
674; CHECK-MVEFP-NEXT:    vpsel q0, q3, q2
675; CHECK-MVEFP-NEXT:    bx lr
676entry:
677  %c = fcmp one <8 x half> %src, %src2
678  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
679  ret <8 x half> %s
680}
681
682define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
683; CHECK-MVE-LABEL: vcmp_ogt_v8f16:
684; CHECK-MVE:       @ %bb.0: @ %entry
685; CHECK-MVE-NEXT:    .vsave {d8, d9}
686; CHECK-MVE-NEXT:    vpush {d8, d9}
687; CHECK-MVE-NEXT:    vmovx.f16 s16, s4
688; CHECK-MVE-NEXT:    vmovx.f16 s18, s0
689; CHECK-MVE-NEXT:    vcmp.f16 s18, s16
690; CHECK-MVE-NEXT:    vmovx.f16 s16, s8
691; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
692; CHECK-MVE-NEXT:    vcmp.f16 s0, s4
693; CHECK-MVE-NEXT:    vmovx.f16 s18, s12
694; CHECK-MVE-NEXT:    vmovx.f16 s4, s5
695; CHECK-MVE-NEXT:    cset r0, gt
696; CHECK-MVE-NEXT:    cmp r0, #0
697; CHECK-MVE-NEXT:    vseleq.f16 s16, s18, s16
698; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
699; CHECK-MVE-NEXT:    cset r0, gt
700; CHECK-MVE-NEXT:    cmp r0, #0
701; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8
702; CHECK-MVE-NEXT:    vmovx.f16 s8, s1
703; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
704; CHECK-MVE-NEXT:    vmovx.f16 s4, s9
705; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
706; CHECK-MVE-NEXT:    vmovx.f16 s8, s13
707; CHECK-MVE-NEXT:    vcmp.f16 s1, s5
708; CHECK-MVE-NEXT:    vins.f16 s0, s16
709; CHECK-MVE-NEXT:    cset r0, gt
710; CHECK-MVE-NEXT:    cmp r0, #0
711; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
712; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
713; CHECK-MVE-NEXT:    vmovx.f16 s8, s2
714; CHECK-MVE-NEXT:    cset r0, gt
715; CHECK-MVE-NEXT:    cmp r0, #0
716; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9
717; CHECK-MVE-NEXT:    vins.f16 s1, s4
718; CHECK-MVE-NEXT:    vmovx.f16 s4, s6
719; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
720; CHECK-MVE-NEXT:    vmovx.f16 s4, s10
721; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
722; CHECK-MVE-NEXT:    vcmp.f16 s2, s6
723; CHECK-MVE-NEXT:    vmovx.f16 s8, s14
724; CHECK-MVE-NEXT:    vmovx.f16 s6, s3
725; CHECK-MVE-NEXT:    cset r0, gt
726; CHECK-MVE-NEXT:    cmp r0, #0
727; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
728; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
729; CHECK-MVE-NEXT:    cset r0, gt
730; CHECK-MVE-NEXT:    cmp r0, #0
731; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10
732; CHECK-MVE-NEXT:    vins.f16 s2, s4
733; CHECK-MVE-NEXT:    vmovx.f16 s4, s7
734; CHECK-MVE-NEXT:    vcmp.f16 s6, s4
735; CHECK-MVE-NEXT:    vmovx.f16 s4, s11
736; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
737; CHECK-MVE-NEXT:    vmovx.f16 s6, s15
738; CHECK-MVE-NEXT:    vcmp.f16 s3, s7
739; CHECK-MVE-NEXT:    cset r0, gt
740; CHECK-MVE-NEXT:    cmp r0, #0
741; CHECK-MVE-NEXT:    vseleq.f16 s4, s6, s4
742; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
743; CHECK-MVE-NEXT:    cset r0, gt
744; CHECK-MVE-NEXT:    cmp r0, #0
745; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11
746; CHECK-MVE-NEXT:    vins.f16 s3, s4
747; CHECK-MVE-NEXT:    vpop {d8, d9}
748; CHECK-MVE-NEXT:    bx lr
749;
750; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16:
751; CHECK-MVEFP:       @ %bb.0: @ %entry
752; CHECK-MVEFP-NEXT:    vcmp.f16 gt, q0, q1
753; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
754; CHECK-MVEFP-NEXT:    bx lr
755entry:
756  %c = fcmp ogt <8 x half> %src, %src2
757  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
758  ret <8 x half> %s
759}
760
761define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
762; CHECK-MVE-LABEL: vcmp_oge_v8f16:
763; CHECK-MVE:       @ %bb.0: @ %entry
764; CHECK-MVE-NEXT:    .vsave {d8, d9}
765; CHECK-MVE-NEXT:    vpush {d8, d9}
766; CHECK-MVE-NEXT:    vmovx.f16 s16, s4
767; CHECK-MVE-NEXT:    vmovx.f16 s18, s0
768; CHECK-MVE-NEXT:    vcmp.f16 s18, s16
769; CHECK-MVE-NEXT:    vmovx.f16 s16, s8
770; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
771; CHECK-MVE-NEXT:    vcmp.f16 s0, s4
772; CHECK-MVE-NEXT:    vmovx.f16 s18, s12
773; CHECK-MVE-NEXT:    vmovx.f16 s4, s5
774; CHECK-MVE-NEXT:    cset r0, ge
775; CHECK-MVE-NEXT:    cmp r0, #0
776; CHECK-MVE-NEXT:    vseleq.f16 s16, s18, s16
777; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
778; CHECK-MVE-NEXT:    cset r0, ge
779; CHECK-MVE-NEXT:    cmp r0, #0
780; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8
781; CHECK-MVE-NEXT:    vmovx.f16 s8, s1
782; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
783; CHECK-MVE-NEXT:    vmovx.f16 s4, s9
784; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
785; CHECK-MVE-NEXT:    vmovx.f16 s8, s13
786; CHECK-MVE-NEXT:    vcmp.f16 s1, s5
787; CHECK-MVE-NEXT:    vins.f16 s0, s16
788; CHECK-MVE-NEXT:    cset r0, ge
789; CHECK-MVE-NEXT:    cmp r0, #0
790; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
791; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
792; CHECK-MVE-NEXT:    vmovx.f16 s8, s2
793; CHECK-MVE-NEXT:    cset r0, ge
794; CHECK-MVE-NEXT:    cmp r0, #0
795; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9
796; CHECK-MVE-NEXT:    vins.f16 s1, s4
797; CHECK-MVE-NEXT:    vmovx.f16 s4, s6
798; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
799; CHECK-MVE-NEXT:    vmovx.f16 s4, s10
800; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
801; CHECK-MVE-NEXT:    vcmp.f16 s2, s6
802; CHECK-MVE-NEXT:    vmovx.f16 s8, s14
803; CHECK-MVE-NEXT:    vmovx.f16 s6, s3
804; CHECK-MVE-NEXT:    cset r0, ge
805; CHECK-MVE-NEXT:    cmp r0, #0
806; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
807; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
808; CHECK-MVE-NEXT:    cset r0, ge
809; CHECK-MVE-NEXT:    cmp r0, #0
810; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10
811; CHECK-MVE-NEXT:    vins.f16 s2, s4
812; CHECK-MVE-NEXT:    vmovx.f16 s4, s7
813; CHECK-MVE-NEXT:    vcmp.f16 s6, s4
814; CHECK-MVE-NEXT:    vmovx.f16 s4, s11
815; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
816; CHECK-MVE-NEXT:    vmovx.f16 s6, s15
817; CHECK-MVE-NEXT:    vcmp.f16 s3, s7
818; CHECK-MVE-NEXT:    cset r0, ge
819; CHECK-MVE-NEXT:    cmp r0, #0
820; CHECK-MVE-NEXT:    vseleq.f16 s4, s6, s4
821; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
822; CHECK-MVE-NEXT:    cset r0, ge
823; CHECK-MVE-NEXT:    cmp r0, #0
824; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11
825; CHECK-MVE-NEXT:    vins.f16 s3, s4
826; CHECK-MVE-NEXT:    vpop {d8, d9}
827; CHECK-MVE-NEXT:    bx lr
828;
829; CHECK-MVEFP-LABEL: vcmp_oge_v8f16:
830; CHECK-MVEFP:       @ %bb.0: @ %entry
831; CHECK-MVEFP-NEXT:    vcmp.f16 ge, q0, q1
832; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
833; CHECK-MVEFP-NEXT:    bx lr
834entry:
835  %c = fcmp oge <8 x half> %src, %src2
836  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
837  ret <8 x half> %s
838}
839
840define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
841; CHECK-MVE-LABEL: vcmp_olt_v8f16:
842; CHECK-MVE:       @ %bb.0: @ %entry
843; CHECK-MVE-NEXT:    .vsave {d8, d9}
844; CHECK-MVE-NEXT:    vpush {d8, d9}
845; CHECK-MVE-NEXT:    vmovx.f16 s16, s4
846; CHECK-MVE-NEXT:    vmovx.f16 s18, s0
847; CHECK-MVE-NEXT:    vcmp.f16 s18, s16
848; CHECK-MVE-NEXT:    vmovx.f16 s16, s8
849; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
850; CHECK-MVE-NEXT:    vcmp.f16 s0, s4
851; CHECK-MVE-NEXT:    vmovx.f16 s18, s12
852; CHECK-MVE-NEXT:    vmovx.f16 s4, s5
853; CHECK-MVE-NEXT:    cset r0, mi
854; CHECK-MVE-NEXT:    cmp r0, #0
855; CHECK-MVE-NEXT:    vseleq.f16 s16, s18, s16
856; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
857; CHECK-MVE-NEXT:    cset r0, mi
858; CHECK-MVE-NEXT:    cmp r0, #0
859; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8
860; CHECK-MVE-NEXT:    vmovx.f16 s8, s1
861; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
862; CHECK-MVE-NEXT:    vmovx.f16 s4, s9
863; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
864; CHECK-MVE-NEXT:    vmovx.f16 s8, s13
865; CHECK-MVE-NEXT:    vcmp.f16 s1, s5
866; CHECK-MVE-NEXT:    vins.f16 s0, s16
867; CHECK-MVE-NEXT:    cset r0, mi
868; CHECK-MVE-NEXT:    cmp r0, #0
869; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
870; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
871; CHECK-MVE-NEXT:    vmovx.f16 s8, s2
872; CHECK-MVE-NEXT:    cset r0, mi
873; CHECK-MVE-NEXT:    cmp r0, #0
874; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9
875; CHECK-MVE-NEXT:    vins.f16 s1, s4
876; CHECK-MVE-NEXT:    vmovx.f16 s4, s6
877; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
878; CHECK-MVE-NEXT:    vmovx.f16 s4, s10
879; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
880; CHECK-MVE-NEXT:    vcmp.f16 s2, s6
881; CHECK-MVE-NEXT:    vmovx.f16 s8, s14
882; CHECK-MVE-NEXT:    vmovx.f16 s6, s3
883; CHECK-MVE-NEXT:    cset r0, mi
884; CHECK-MVE-NEXT:    cmp r0, #0
885; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
886; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
887; CHECK-MVE-NEXT:    cset r0, mi
888; CHECK-MVE-NEXT:    cmp r0, #0
889; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10
890; CHECK-MVE-NEXT:    vins.f16 s2, s4
891; CHECK-MVE-NEXT:    vmovx.f16 s4, s7
892; CHECK-MVE-NEXT:    vcmp.f16 s6, s4
893; CHECK-MVE-NEXT:    vmovx.f16 s4, s11
894; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
895; CHECK-MVE-NEXT:    vmovx.f16 s6, s15
896; CHECK-MVE-NEXT:    vcmp.f16 s3, s7
897; CHECK-MVE-NEXT:    cset r0, mi
898; CHECK-MVE-NEXT:    cmp r0, #0
899; CHECK-MVE-NEXT:    vseleq.f16 s4, s6, s4
900; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
901; CHECK-MVE-NEXT:    cset r0, mi
902; CHECK-MVE-NEXT:    cmp r0, #0
903; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11
904; CHECK-MVE-NEXT:    vins.f16 s3, s4
905; CHECK-MVE-NEXT:    vpop {d8, d9}
906; CHECK-MVE-NEXT:    bx lr
907;
908; CHECK-MVEFP-LABEL: vcmp_olt_v8f16:
909; CHECK-MVEFP:       @ %bb.0: @ %entry
910; CHECK-MVEFP-NEXT:    vcmp.f16 gt, q1, q0
911; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
912; CHECK-MVEFP-NEXT:    bx lr
913entry:
914  %c = fcmp olt <8 x half> %src, %src2
915  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
916  ret <8 x half> %s
917}
918
919define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
920; CHECK-MVE-LABEL: vcmp_ole_v8f16:
921; CHECK-MVE:       @ %bb.0: @ %entry
922; CHECK-MVE-NEXT:    .vsave {d8, d9}
923; CHECK-MVE-NEXT:    vpush {d8, d9}
924; CHECK-MVE-NEXT:    vmovx.f16 s16, s4
925; CHECK-MVE-NEXT:    vmovx.f16 s18, s0
926; CHECK-MVE-NEXT:    vcmp.f16 s18, s16
927; CHECK-MVE-NEXT:    vmovx.f16 s16, s8
928; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
929; CHECK-MVE-NEXT:    vcmp.f16 s0, s4
930; CHECK-MVE-NEXT:    vmovx.f16 s18, s12
931; CHECK-MVE-NEXT:    vmovx.f16 s4, s5
932; CHECK-MVE-NEXT:    cset r0, ls
933; CHECK-MVE-NEXT:    cmp r0, #0
934; CHECK-MVE-NEXT:    vseleq.f16 s16, s18, s16
935; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
936; CHECK-MVE-NEXT:    cset r0, ls
937; CHECK-MVE-NEXT:    cmp r0, #0
938; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8
939; CHECK-MVE-NEXT:    vmovx.f16 s8, s1
940; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
941; CHECK-MVE-NEXT:    vmovx.f16 s4, s9
942; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
943; CHECK-MVE-NEXT:    vmovx.f16 s8, s13
944; CHECK-MVE-NEXT:    vcmp.f16 s1, s5
945; CHECK-MVE-NEXT:    vins.f16 s0, s16
946; CHECK-MVE-NEXT:    cset r0, ls
947; CHECK-MVE-NEXT:    cmp r0, #0
948; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
949; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
950; CHECK-MVE-NEXT:    vmovx.f16 s8, s2
951; CHECK-MVE-NEXT:    cset r0, ls
952; CHECK-MVE-NEXT:    cmp r0, #0
953; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9
954; CHECK-MVE-NEXT:    vins.f16 s1, s4
955; CHECK-MVE-NEXT:    vmovx.f16 s4, s6
956; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
957; CHECK-MVE-NEXT:    vmovx.f16 s4, s10
958; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
959; CHECK-MVE-NEXT:    vcmp.f16 s2, s6
960; CHECK-MVE-NEXT:    vmovx.f16 s8, s14
961; CHECK-MVE-NEXT:    vmovx.f16 s6, s3
962; CHECK-MVE-NEXT:    cset r0, ls
963; CHECK-MVE-NEXT:    cmp r0, #0
964; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
965; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
966; CHECK-MVE-NEXT:    cset r0, ls
967; CHECK-MVE-NEXT:    cmp r0, #0
968; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10
969; CHECK-MVE-NEXT:    vins.f16 s2, s4
970; CHECK-MVE-NEXT:    vmovx.f16 s4, s7
971; CHECK-MVE-NEXT:    vcmp.f16 s6, s4
972; CHECK-MVE-NEXT:    vmovx.f16 s4, s11
973; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
974; CHECK-MVE-NEXT:    vmovx.f16 s6, s15
975; CHECK-MVE-NEXT:    vcmp.f16 s3, s7
976; CHECK-MVE-NEXT:    cset r0, ls
977; CHECK-MVE-NEXT:    cmp r0, #0
978; CHECK-MVE-NEXT:    vseleq.f16 s4, s6, s4
979; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
980; CHECK-MVE-NEXT:    cset r0, ls
981; CHECK-MVE-NEXT:    cmp r0, #0
982; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11
983; CHECK-MVE-NEXT:    vins.f16 s3, s4
984; CHECK-MVE-NEXT:    vpop {d8, d9}
985; CHECK-MVE-NEXT:    bx lr
986;
987; CHECK-MVEFP-LABEL: vcmp_ole_v8f16:
988; CHECK-MVEFP:       @ %bb.0: @ %entry
989; CHECK-MVEFP-NEXT:    vcmp.f16 ge, q1, q0
990; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
991; CHECK-MVEFP-NEXT:    bx lr
992entry:
993  %c = fcmp ole <8 x half> %src, %src2
994  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
995  ret <8 x half> %s
996}
997
998define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
999; CHECK-MVE-LABEL: vcmp_ueq_v8f16:
1000; CHECK-MVE:       @ %bb.0: @ %entry
1001; CHECK-MVE-NEXT:    .vsave {d8, d9}
1002; CHECK-MVE-NEXT:    vpush {d8, d9}
1003; CHECK-MVE-NEXT:    vmovx.f16 s16, s4
1004; CHECK-MVE-NEXT:    vmovx.f16 s18, s0
1005; CHECK-MVE-NEXT:    vcmp.f16 s18, s16
1006; CHECK-MVE-NEXT:    vmovx.f16 s16, s8
1007; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1008; CHECK-MVE-NEXT:    vcmp.f16 s0, s4
1009; CHECK-MVE-NEXT:    vmovx.f16 s18, s12
1010; CHECK-MVE-NEXT:    vmovx.f16 s4, s5
1011; CHECK-MVE-NEXT:    cset r0, eq
1012; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc
1013; CHECK-MVE-NEXT:    cmp r0, #0
1014; CHECK-MVE-NEXT:    vseleq.f16 s16, s18, s16
1015; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1016; CHECK-MVE-NEXT:    cset r0, eq
1017; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc
1018; CHECK-MVE-NEXT:    cmp r0, #0
1019; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8
1020; CHECK-MVE-NEXT:    vmovx.f16 s8, s1
1021; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
1022; CHECK-MVE-NEXT:    vmovx.f16 s4, s9
1023; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1024; CHECK-MVE-NEXT:    vmovx.f16 s8, s13
1025; CHECK-MVE-NEXT:    vcmp.f16 s1, s5
1026; CHECK-MVE-NEXT:    vins.f16 s0, s16
1027; CHECK-MVE-NEXT:    cset r0, eq
1028; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc
1029; CHECK-MVE-NEXT:    cmp r0, #0
1030; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
1031; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1032; CHECK-MVE-NEXT:    vmovx.f16 s8, s2
1033; CHECK-MVE-NEXT:    cset r0, eq
1034; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc
1035; CHECK-MVE-NEXT:    cmp r0, #0
1036; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9
1037; CHECK-MVE-NEXT:    vins.f16 s1, s4
1038; CHECK-MVE-NEXT:    vmovx.f16 s4, s6
1039; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
1040; CHECK-MVE-NEXT:    vmovx.f16 s4, s10
1041; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1042; CHECK-MVE-NEXT:    vcmp.f16 s2, s6
1043; CHECK-MVE-NEXT:    vmovx.f16 s8, s14
1044; CHECK-MVE-NEXT:    vmovx.f16 s6, s3
1045; CHECK-MVE-NEXT:    cset r0, eq
1046; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc
1047; CHECK-MVE-NEXT:    cmp r0, #0
1048; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
1049; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1050; CHECK-MVE-NEXT:    cset r0, eq
1051; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc
1052; CHECK-MVE-NEXT:    cmp r0, #0
1053; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10
1054; CHECK-MVE-NEXT:    vins.f16 s2, s4
1055; CHECK-MVE-NEXT:    vmovx.f16 s4, s7
1056; CHECK-MVE-NEXT:    vcmp.f16 s6, s4
1057; CHECK-MVE-NEXT:    vmovx.f16 s4, s11
1058; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1059; CHECK-MVE-NEXT:    vmovx.f16 s6, s15
1060; CHECK-MVE-NEXT:    vcmp.f16 s3, s7
1061; CHECK-MVE-NEXT:    cset r0, eq
1062; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc
1063; CHECK-MVE-NEXT:    cmp r0, #0
1064; CHECK-MVE-NEXT:    vseleq.f16 s4, s6, s4
1065; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1066; CHECK-MVE-NEXT:    cset r0, eq
1067; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc
1068; CHECK-MVE-NEXT:    cmp r0, #0
1069; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11
1070; CHECK-MVE-NEXT:    vins.f16 s3, s4
1071; CHECK-MVE-NEXT:    vpop {d8, d9}
1072; CHECK-MVE-NEXT:    bx lr
1073;
1074; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16:
1075; CHECK-MVEFP:       @ %bb.0: @ %entry
1076; CHECK-MVEFP-NEXT:    vpt.f16 le, q1, q0
1077; CHECK-MVEFP-NEXT:    vcmpt.f16 le, q0, q1
1078; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
1079; CHECK-MVEFP-NEXT:    bx lr
1080entry:
1081  %c = fcmp ueq <8 x half> %src, %src2
1082  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
1083  ret <8 x half> %s
1084}
1085
1086define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
1087; CHECK-MVE-LABEL: vcmp_une_v8f16:
1088; CHECK-MVE:       @ %bb.0: @ %entry
1089; CHECK-MVE-NEXT:    .vsave {d8, d9}
1090; CHECK-MVE-NEXT:    vpush {d8, d9}
1091; CHECK-MVE-NEXT:    vmovx.f16 s16, s4
1092; CHECK-MVE-NEXT:    vmovx.f16 s18, s0
1093; CHECK-MVE-NEXT:    vcmp.f16 s18, s16
1094; CHECK-MVE-NEXT:    vmovx.f16 s16, s8
1095; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1096; CHECK-MVE-NEXT:    vmovx.f16 s18, s12
1097; CHECK-MVE-NEXT:    vcmp.f16 s0, s4
1098; CHECK-MVE-NEXT:    vmovx.f16 s4, s5
1099; CHECK-MVE-NEXT:    vseleq.f16 s16, s18, s16
1100; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1101; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8
1102; CHECK-MVE-NEXT:    vmovx.f16 s8, s1
1103; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
1104; CHECK-MVE-NEXT:    vmovx.f16 s4, s9
1105; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1106; CHECK-MVE-NEXT:    vmovx.f16 s8, s13
1107; CHECK-MVE-NEXT:    vcmp.f16 s1, s5
1108; CHECK-MVE-NEXT:    vins.f16 s0, s16
1109; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
1110; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1111; CHECK-MVE-NEXT:    vmovx.f16 s8, s2
1112; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9
1113; CHECK-MVE-NEXT:    vins.f16 s1, s4
1114; CHECK-MVE-NEXT:    vmovx.f16 s4, s6
1115; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
1116; CHECK-MVE-NEXT:    vmovx.f16 s4, s10
1117; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1118; CHECK-MVE-NEXT:    vmovx.f16 s8, s14
1119; CHECK-MVE-NEXT:    vcmp.f16 s2, s6
1120; CHECK-MVE-NEXT:    vmovx.f16 s6, s3
1121; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
1122; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1123; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10
1124; CHECK-MVE-NEXT:    vins.f16 s2, s4
1125; CHECK-MVE-NEXT:    vmovx.f16 s4, s7
1126; CHECK-MVE-NEXT:    vcmp.f16 s6, s4
1127; CHECK-MVE-NEXT:    vmovx.f16 s4, s11
1128; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1129; CHECK-MVE-NEXT:    vmovx.f16 s6, s15
1130; CHECK-MVE-NEXT:    vcmp.f16 s3, s7
1131; CHECK-MVE-NEXT:    vseleq.f16 s4, s6, s4
1132; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1133; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11
1134; CHECK-MVE-NEXT:    vins.f16 s3, s4
1135; CHECK-MVE-NEXT:    vpop {d8, d9}
1136; CHECK-MVE-NEXT:    bx lr
1137;
1138; CHECK-MVEFP-LABEL: vcmp_une_v8f16:
1139; CHECK-MVEFP:       @ %bb.0: @ %entry
1140; CHECK-MVEFP-NEXT:    vcmp.f16 ne, q0, q1
1141; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
1142; CHECK-MVEFP-NEXT:    bx lr
1143entry:
1144  %c = fcmp une <8 x half> %src, %src2
1145  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
1146  ret <8 x half> %s
1147}
1148
1149define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
1150; CHECK-MVE-LABEL: vcmp_ugt_v8f16:
1151; CHECK-MVE:       @ %bb.0: @ %entry
1152; CHECK-MVE-NEXT:    .vsave {d8, d9}
1153; CHECK-MVE-NEXT:    vpush {d8, d9}
1154; CHECK-MVE-NEXT:    vmovx.f16 s16, s4
1155; CHECK-MVE-NEXT:    vmovx.f16 s18, s0
1156; CHECK-MVE-NEXT:    vcmp.f16 s18, s16
1157; CHECK-MVE-NEXT:    vmovx.f16 s16, s8
1158; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1159; CHECK-MVE-NEXT:    vcmp.f16 s0, s4
1160; CHECK-MVE-NEXT:    vmovx.f16 s18, s12
1161; CHECK-MVE-NEXT:    vmovx.f16 s4, s5
1162; CHECK-MVE-NEXT:    cset r0, hi
1163; CHECK-MVE-NEXT:    cmp r0, #0
1164; CHECK-MVE-NEXT:    vseleq.f16 s16, s18, s16
1165; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1166; CHECK-MVE-NEXT:    cset r0, hi
1167; CHECK-MVE-NEXT:    cmp r0, #0
1168; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8
1169; CHECK-MVE-NEXT:    vmovx.f16 s8, s1
1170; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
1171; CHECK-MVE-NEXT:    vmovx.f16 s4, s9
1172; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1173; CHECK-MVE-NEXT:    vmovx.f16 s8, s13
1174; CHECK-MVE-NEXT:    vcmp.f16 s1, s5
1175; CHECK-MVE-NEXT:    vins.f16 s0, s16
1176; CHECK-MVE-NEXT:    cset r0, hi
1177; CHECK-MVE-NEXT:    cmp r0, #0
1178; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
1179; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1180; CHECK-MVE-NEXT:    vmovx.f16 s8, s2
1181; CHECK-MVE-NEXT:    cset r0, hi
1182; CHECK-MVE-NEXT:    cmp r0, #0
1183; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9
1184; CHECK-MVE-NEXT:    vins.f16 s1, s4
1185; CHECK-MVE-NEXT:    vmovx.f16 s4, s6
1186; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
1187; CHECK-MVE-NEXT:    vmovx.f16 s4, s10
1188; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1189; CHECK-MVE-NEXT:    vcmp.f16 s2, s6
1190; CHECK-MVE-NEXT:    vmovx.f16 s8, s14
1191; CHECK-MVE-NEXT:    vmovx.f16 s6, s3
1192; CHECK-MVE-NEXT:    cset r0, hi
1193; CHECK-MVE-NEXT:    cmp r0, #0
1194; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
1195; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1196; CHECK-MVE-NEXT:    cset r0, hi
1197; CHECK-MVE-NEXT:    cmp r0, #0
1198; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10
1199; CHECK-MVE-NEXT:    vins.f16 s2, s4
1200; CHECK-MVE-NEXT:    vmovx.f16 s4, s7
1201; CHECK-MVE-NEXT:    vcmp.f16 s6, s4
1202; CHECK-MVE-NEXT:    vmovx.f16 s4, s11
1203; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1204; CHECK-MVE-NEXT:    vmovx.f16 s6, s15
1205; CHECK-MVE-NEXT:    vcmp.f16 s3, s7
1206; CHECK-MVE-NEXT:    cset r0, hi
1207; CHECK-MVE-NEXT:    cmp r0, #0
1208; CHECK-MVE-NEXT:    vseleq.f16 s4, s6, s4
1209; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1210; CHECK-MVE-NEXT:    cset r0, hi
1211; CHECK-MVE-NEXT:    cmp r0, #0
1212; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11
1213; CHECK-MVE-NEXT:    vins.f16 s3, s4
1214; CHECK-MVE-NEXT:    vpop {d8, d9}
1215; CHECK-MVE-NEXT:    bx lr
1216;
1217; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16:
1218; CHECK-MVEFP:       @ %bb.0: @ %entry
1219; CHECK-MVEFP-NEXT:    vcmp.f16 lt, q1, q0
1220; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
1221; CHECK-MVEFP-NEXT:    bx lr
1222entry:
1223  %c = fcmp ugt <8 x half> %src, %src2
1224  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
1225  ret <8 x half> %s
1226}
1227
1228define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
1229; CHECK-MVE-LABEL: vcmp_uge_v8f16:
1230; CHECK-MVE:       @ %bb.0: @ %entry
1231; CHECK-MVE-NEXT:    .vsave {d8, d9}
1232; CHECK-MVE-NEXT:    vpush {d8, d9}
1233; CHECK-MVE-NEXT:    vmovx.f16 s16, s4
1234; CHECK-MVE-NEXT:    vmovx.f16 s18, s0
1235; CHECK-MVE-NEXT:    vcmp.f16 s18, s16
1236; CHECK-MVE-NEXT:    vmovx.f16 s16, s8
1237; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1238; CHECK-MVE-NEXT:    vcmp.f16 s0, s4
1239; CHECK-MVE-NEXT:    vmovx.f16 s18, s12
1240; CHECK-MVE-NEXT:    vmovx.f16 s4, s5
1241; CHECK-MVE-NEXT:    cset r0, pl
1242; CHECK-MVE-NEXT:    cmp r0, #0
1243; CHECK-MVE-NEXT:    vseleq.f16 s16, s18, s16
1244; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1245; CHECK-MVE-NEXT:    cset r0, pl
1246; CHECK-MVE-NEXT:    cmp r0, #0
1247; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8
1248; CHECK-MVE-NEXT:    vmovx.f16 s8, s1
1249; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
1250; CHECK-MVE-NEXT:    vmovx.f16 s4, s9
1251; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1252; CHECK-MVE-NEXT:    vmovx.f16 s8, s13
1253; CHECK-MVE-NEXT:    vcmp.f16 s1, s5
1254; CHECK-MVE-NEXT:    vins.f16 s0, s16
1255; CHECK-MVE-NEXT:    cset r0, pl
1256; CHECK-MVE-NEXT:    cmp r0, #0
1257; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
1258; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1259; CHECK-MVE-NEXT:    vmovx.f16 s8, s2
1260; CHECK-MVE-NEXT:    cset r0, pl
1261; CHECK-MVE-NEXT:    cmp r0, #0
1262; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9
1263; CHECK-MVE-NEXT:    vins.f16 s1, s4
1264; CHECK-MVE-NEXT:    vmovx.f16 s4, s6
1265; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
1266; CHECK-MVE-NEXT:    vmovx.f16 s4, s10
1267; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1268; CHECK-MVE-NEXT:    vcmp.f16 s2, s6
1269; CHECK-MVE-NEXT:    vmovx.f16 s8, s14
1270; CHECK-MVE-NEXT:    vmovx.f16 s6, s3
1271; CHECK-MVE-NEXT:    cset r0, pl
1272; CHECK-MVE-NEXT:    cmp r0, #0
1273; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
1274; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1275; CHECK-MVE-NEXT:    cset r0, pl
1276; CHECK-MVE-NEXT:    cmp r0, #0
1277; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10
1278; CHECK-MVE-NEXT:    vins.f16 s2, s4
1279; CHECK-MVE-NEXT:    vmovx.f16 s4, s7
1280; CHECK-MVE-NEXT:    vcmp.f16 s6, s4
1281; CHECK-MVE-NEXT:    vmovx.f16 s4, s11
1282; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1283; CHECK-MVE-NEXT:    vmovx.f16 s6, s15
1284; CHECK-MVE-NEXT:    vcmp.f16 s3, s7
1285; CHECK-MVE-NEXT:    cset r0, pl
1286; CHECK-MVE-NEXT:    cmp r0, #0
1287; CHECK-MVE-NEXT:    vseleq.f16 s4, s6, s4
1288; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1289; CHECK-MVE-NEXT:    cset r0, pl
1290; CHECK-MVE-NEXT:    cmp r0, #0
1291; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11
1292; CHECK-MVE-NEXT:    vins.f16 s3, s4
1293; CHECK-MVE-NEXT:    vpop {d8, d9}
1294; CHECK-MVE-NEXT:    bx lr
1295;
1296; CHECK-MVEFP-LABEL: vcmp_uge_v8f16:
1297; CHECK-MVEFP:       @ %bb.0: @ %entry
1298; CHECK-MVEFP-NEXT:    vcmp.f16 le, q1, q0
1299; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
1300; CHECK-MVEFP-NEXT:    bx lr
1301entry:
1302  %c = fcmp uge <8 x half> %src, %src2
1303  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
1304  ret <8 x half> %s
1305}
1306
1307define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
1308; CHECK-MVE-LABEL: vcmp_ult_v8f16:
1309; CHECK-MVE:       @ %bb.0: @ %entry
1310; CHECK-MVE-NEXT:    .vsave {d8, d9}
1311; CHECK-MVE-NEXT:    vpush {d8, d9}
1312; CHECK-MVE-NEXT:    vmovx.f16 s16, s4
1313; CHECK-MVE-NEXT:    vmovx.f16 s18, s0
1314; CHECK-MVE-NEXT:    vcmp.f16 s18, s16
1315; CHECK-MVE-NEXT:    vmovx.f16 s16, s8
1316; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1317; CHECK-MVE-NEXT:    vcmp.f16 s0, s4
1318; CHECK-MVE-NEXT:    vmovx.f16 s18, s12
1319; CHECK-MVE-NEXT:    vmovx.f16 s4, s5
1320; CHECK-MVE-NEXT:    cset r0, lt
1321; CHECK-MVE-NEXT:    cmp r0, #0
1322; CHECK-MVE-NEXT:    vseleq.f16 s16, s18, s16
1323; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1324; CHECK-MVE-NEXT:    cset r0, lt
1325; CHECK-MVE-NEXT:    cmp r0, #0
1326; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8
1327; CHECK-MVE-NEXT:    vmovx.f16 s8, s1
1328; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
1329; CHECK-MVE-NEXT:    vmovx.f16 s4, s9
1330; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1331; CHECK-MVE-NEXT:    vmovx.f16 s8, s13
1332; CHECK-MVE-NEXT:    vcmp.f16 s1, s5
1333; CHECK-MVE-NEXT:    vins.f16 s0, s16
1334; CHECK-MVE-NEXT:    cset r0, lt
1335; CHECK-MVE-NEXT:    cmp r0, #0
1336; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
1337; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1338; CHECK-MVE-NEXT:    vmovx.f16 s8, s2
1339; CHECK-MVE-NEXT:    cset r0, lt
1340; CHECK-MVE-NEXT:    cmp r0, #0
1341; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9
1342; CHECK-MVE-NEXT:    vins.f16 s1, s4
1343; CHECK-MVE-NEXT:    vmovx.f16 s4, s6
1344; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
1345; CHECK-MVE-NEXT:    vmovx.f16 s4, s10
1346; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1347; CHECK-MVE-NEXT:    vcmp.f16 s2, s6
1348; CHECK-MVE-NEXT:    vmovx.f16 s8, s14
1349; CHECK-MVE-NEXT:    vmovx.f16 s6, s3
1350; CHECK-MVE-NEXT:    cset r0, lt
1351; CHECK-MVE-NEXT:    cmp r0, #0
1352; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
1353; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1354; CHECK-MVE-NEXT:    cset r0, lt
1355; CHECK-MVE-NEXT:    cmp r0, #0
1356; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10
1357; CHECK-MVE-NEXT:    vins.f16 s2, s4
1358; CHECK-MVE-NEXT:    vmovx.f16 s4, s7
1359; CHECK-MVE-NEXT:    vcmp.f16 s6, s4
1360; CHECK-MVE-NEXT:    vmovx.f16 s4, s11
1361; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1362; CHECK-MVE-NEXT:    vmovx.f16 s6, s15
1363; CHECK-MVE-NEXT:    vcmp.f16 s3, s7
1364; CHECK-MVE-NEXT:    cset r0, lt
1365; CHECK-MVE-NEXT:    cmp r0, #0
1366; CHECK-MVE-NEXT:    vseleq.f16 s4, s6, s4
1367; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1368; CHECK-MVE-NEXT:    cset r0, lt
1369; CHECK-MVE-NEXT:    cmp r0, #0
1370; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11
1371; CHECK-MVE-NEXT:    vins.f16 s3, s4
1372; CHECK-MVE-NEXT:    vpop {d8, d9}
1373; CHECK-MVE-NEXT:    bx lr
1374;
1375; CHECK-MVEFP-LABEL: vcmp_ult_v8f16:
1376; CHECK-MVEFP:       @ %bb.0: @ %entry
1377; CHECK-MVEFP-NEXT:    vcmp.f16 lt, q0, q1
1378; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
1379; CHECK-MVEFP-NEXT:    bx lr
1380entry:
1381  %c = fcmp ult <8 x half> %src, %src2
1382  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
1383  ret <8 x half> %s
1384}
1385
1386define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
1387; CHECK-MVE-LABEL: vcmp_ule_v8f16:
1388; CHECK-MVE:       @ %bb.0: @ %entry
1389; CHECK-MVE-NEXT:    .vsave {d8, d9}
1390; CHECK-MVE-NEXT:    vpush {d8, d9}
1391; CHECK-MVE-NEXT:    vmovx.f16 s16, s4
1392; CHECK-MVE-NEXT:    vmovx.f16 s18, s0
1393; CHECK-MVE-NEXT:    vcmp.f16 s18, s16
1394; CHECK-MVE-NEXT:    vmovx.f16 s16, s8
1395; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1396; CHECK-MVE-NEXT:    vcmp.f16 s0, s4
1397; CHECK-MVE-NEXT:    vmovx.f16 s18, s12
1398; CHECK-MVE-NEXT:    vmovx.f16 s4, s5
1399; CHECK-MVE-NEXT:    cset r0, le
1400; CHECK-MVE-NEXT:    cmp r0, #0
1401; CHECK-MVE-NEXT:    vseleq.f16 s16, s18, s16
1402; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1403; CHECK-MVE-NEXT:    cset r0, le
1404; CHECK-MVE-NEXT:    cmp r0, #0
1405; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8
1406; CHECK-MVE-NEXT:    vmovx.f16 s8, s1
1407; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
1408; CHECK-MVE-NEXT:    vmovx.f16 s4, s9
1409; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1410; CHECK-MVE-NEXT:    vmovx.f16 s8, s13
1411; CHECK-MVE-NEXT:    vcmp.f16 s1, s5
1412; CHECK-MVE-NEXT:    vins.f16 s0, s16
1413; CHECK-MVE-NEXT:    cset r0, le
1414; CHECK-MVE-NEXT:    cmp r0, #0
1415; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
1416; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1417; CHECK-MVE-NEXT:    vmovx.f16 s8, s2
1418; CHECK-MVE-NEXT:    cset r0, le
1419; CHECK-MVE-NEXT:    cmp r0, #0
1420; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9
1421; CHECK-MVE-NEXT:    vins.f16 s1, s4
1422; CHECK-MVE-NEXT:    vmovx.f16 s4, s6
1423; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
1424; CHECK-MVE-NEXT:    vmovx.f16 s4, s10
1425; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1426; CHECK-MVE-NEXT:    vcmp.f16 s2, s6
1427; CHECK-MVE-NEXT:    vmovx.f16 s8, s14
1428; CHECK-MVE-NEXT:    vmovx.f16 s6, s3
1429; CHECK-MVE-NEXT:    cset r0, le
1430; CHECK-MVE-NEXT:    cmp r0, #0
1431; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
1432; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1433; CHECK-MVE-NEXT:    cset r0, le
1434; CHECK-MVE-NEXT:    cmp r0, #0
1435; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10
1436; CHECK-MVE-NEXT:    vins.f16 s2, s4
1437; CHECK-MVE-NEXT:    vmovx.f16 s4, s7
1438; CHECK-MVE-NEXT:    vcmp.f16 s6, s4
1439; CHECK-MVE-NEXT:    vmovx.f16 s4, s11
1440; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1441; CHECK-MVE-NEXT:    vmovx.f16 s6, s15
1442; CHECK-MVE-NEXT:    vcmp.f16 s3, s7
1443; CHECK-MVE-NEXT:    cset r0, le
1444; CHECK-MVE-NEXT:    cmp r0, #0
1445; CHECK-MVE-NEXT:    vseleq.f16 s4, s6, s4
1446; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1447; CHECK-MVE-NEXT:    cset r0, le
1448; CHECK-MVE-NEXT:    cmp r0, #0
1449; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11
1450; CHECK-MVE-NEXT:    vins.f16 s3, s4
1451; CHECK-MVE-NEXT:    vpop {d8, d9}
1452; CHECK-MVE-NEXT:    bx lr
1453;
1454; CHECK-MVEFP-LABEL: vcmp_ule_v8f16:
1455; CHECK-MVEFP:       @ %bb.0: @ %entry
1456; CHECK-MVEFP-NEXT:    vcmp.f16 le, q0, q1
1457; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
1458; CHECK-MVEFP-NEXT:    bx lr
1459entry:
1460  %c = fcmp ule <8 x half> %src, %src2
1461  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
1462  ret <8 x half> %s
1463}
1464
1465define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
1466; CHECK-MVE-LABEL: vcmp_ord_v8f16:
1467; CHECK-MVE:       @ %bb.0: @ %entry
1468; CHECK-MVE-NEXT:    .vsave {d8, d9}
1469; CHECK-MVE-NEXT:    vpush {d8, d9}
1470; CHECK-MVE-NEXT:    vmovx.f16 s16, s4
1471; CHECK-MVE-NEXT:    vmovx.f16 s18, s0
1472; CHECK-MVE-NEXT:    vcmp.f16 s18, s16
1473; CHECK-MVE-NEXT:    vmovx.f16 s16, s8
1474; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1475; CHECK-MVE-NEXT:    vcmp.f16 s0, s4
1476; CHECK-MVE-NEXT:    vmovx.f16 s18, s12
1477; CHECK-MVE-NEXT:    vmovx.f16 s4, s5
1478; CHECK-MVE-NEXT:    cset r0, vc
1479; CHECK-MVE-NEXT:    cmp r0, #0
1480; CHECK-MVE-NEXT:    vseleq.f16 s16, s18, s16
1481; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1482; CHECK-MVE-NEXT:    cset r0, vc
1483; CHECK-MVE-NEXT:    cmp r0, #0
1484; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8
1485; CHECK-MVE-NEXT:    vmovx.f16 s8, s1
1486; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
1487; CHECK-MVE-NEXT:    vmovx.f16 s4, s9
1488; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1489; CHECK-MVE-NEXT:    vmovx.f16 s8, s13
1490; CHECK-MVE-NEXT:    vcmp.f16 s1, s5
1491; CHECK-MVE-NEXT:    vins.f16 s0, s16
1492; CHECK-MVE-NEXT:    cset r0, vc
1493; CHECK-MVE-NEXT:    cmp r0, #0
1494; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
1495; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1496; CHECK-MVE-NEXT:    vmovx.f16 s8, s2
1497; CHECK-MVE-NEXT:    cset r0, vc
1498; CHECK-MVE-NEXT:    cmp r0, #0
1499; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9
1500; CHECK-MVE-NEXT:    vins.f16 s1, s4
1501; CHECK-MVE-NEXT:    vmovx.f16 s4, s6
1502; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
1503; CHECK-MVE-NEXT:    vmovx.f16 s4, s10
1504; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1505; CHECK-MVE-NEXT:    vcmp.f16 s2, s6
1506; CHECK-MVE-NEXT:    vmovx.f16 s8, s14
1507; CHECK-MVE-NEXT:    vmovx.f16 s6, s3
1508; CHECK-MVE-NEXT:    cset r0, vc
1509; CHECK-MVE-NEXT:    cmp r0, #0
1510; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
1511; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1512; CHECK-MVE-NEXT:    cset r0, vc
1513; CHECK-MVE-NEXT:    cmp r0, #0
1514; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10
1515; CHECK-MVE-NEXT:    vins.f16 s2, s4
1516; CHECK-MVE-NEXT:    vmovx.f16 s4, s7
1517; CHECK-MVE-NEXT:    vcmp.f16 s6, s4
1518; CHECK-MVE-NEXT:    vmovx.f16 s4, s11
1519; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1520; CHECK-MVE-NEXT:    vmovx.f16 s6, s15
1521; CHECK-MVE-NEXT:    vcmp.f16 s3, s7
1522; CHECK-MVE-NEXT:    cset r0, vc
1523; CHECK-MVE-NEXT:    cmp r0, #0
1524; CHECK-MVE-NEXT:    vseleq.f16 s4, s6, s4
1525; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1526; CHECK-MVE-NEXT:    cset r0, vc
1527; CHECK-MVE-NEXT:    cmp r0, #0
1528; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11
1529; CHECK-MVE-NEXT:    vins.f16 s3, s4
1530; CHECK-MVE-NEXT:    vpop {d8, d9}
1531; CHECK-MVE-NEXT:    bx lr
1532;
1533; CHECK-MVEFP-LABEL: vcmp_ord_v8f16:
1534; CHECK-MVEFP:       @ %bb.0: @ %entry
1535; CHECK-MVEFP-NEXT:    vpt.f16 le, q1, q0
1536; CHECK-MVEFP-NEXT:    vcmpt.f16 lt, q0, q1
1537; CHECK-MVEFP-NEXT:    vpsel q0, q3, q2
1538; CHECK-MVEFP-NEXT:    bx lr
1539entry:
1540  %c = fcmp ord <8 x half> %src, %src2
1541  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
1542  ret <8 x half> %s
1543}
1544
1545define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
1546; CHECK-MVE-LABEL: vcmp_uno_v8f16:
1547; CHECK-MVE:       @ %bb.0: @ %entry
1548; CHECK-MVE-NEXT:    .vsave {d8, d9}
1549; CHECK-MVE-NEXT:    vpush {d8, d9}
1550; CHECK-MVE-NEXT:    vmovx.f16 s16, s4
1551; CHECK-MVE-NEXT:    vmovx.f16 s18, s0
1552; CHECK-MVE-NEXT:    vcmp.f16 s18, s16
1553; CHECK-MVE-NEXT:    vmovx.f16 s16, s8
1554; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1555; CHECK-MVE-NEXT:    vcmp.f16 s0, s4
1556; CHECK-MVE-NEXT:    vmovx.f16 s18, s12
1557; CHECK-MVE-NEXT:    vmovx.f16 s4, s5
1558; CHECK-MVE-NEXT:    cset r0, vs
1559; CHECK-MVE-NEXT:    cmp r0, #0
1560; CHECK-MVE-NEXT:    vseleq.f16 s16, s18, s16
1561; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1562; CHECK-MVE-NEXT:    cset r0, vs
1563; CHECK-MVE-NEXT:    cmp r0, #0
1564; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8
1565; CHECK-MVE-NEXT:    vmovx.f16 s8, s1
1566; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
1567; CHECK-MVE-NEXT:    vmovx.f16 s4, s9
1568; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1569; CHECK-MVE-NEXT:    vmovx.f16 s8, s13
1570; CHECK-MVE-NEXT:    vcmp.f16 s1, s5
1571; CHECK-MVE-NEXT:    vins.f16 s0, s16
1572; CHECK-MVE-NEXT:    cset r0, vs
1573; CHECK-MVE-NEXT:    cmp r0, #0
1574; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
1575; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1576; CHECK-MVE-NEXT:    vmovx.f16 s8, s2
1577; CHECK-MVE-NEXT:    cset r0, vs
1578; CHECK-MVE-NEXT:    cmp r0, #0
1579; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9
1580; CHECK-MVE-NEXT:    vins.f16 s1, s4
1581; CHECK-MVE-NEXT:    vmovx.f16 s4, s6
1582; CHECK-MVE-NEXT:    vcmp.f16 s8, s4
1583; CHECK-MVE-NEXT:    vmovx.f16 s4, s10
1584; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1585; CHECK-MVE-NEXT:    vcmp.f16 s2, s6
1586; CHECK-MVE-NEXT:    vmovx.f16 s8, s14
1587; CHECK-MVE-NEXT:    vmovx.f16 s6, s3
1588; CHECK-MVE-NEXT:    cset r0, vs
1589; CHECK-MVE-NEXT:    cmp r0, #0
1590; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s4
1591; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1592; CHECK-MVE-NEXT:    cset r0, vs
1593; CHECK-MVE-NEXT:    cmp r0, #0
1594; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10
1595; CHECK-MVE-NEXT:    vins.f16 s2, s4
1596; CHECK-MVE-NEXT:    vmovx.f16 s4, s7
1597; CHECK-MVE-NEXT:    vcmp.f16 s6, s4
1598; CHECK-MVE-NEXT:    vmovx.f16 s4, s11
1599; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1600; CHECK-MVE-NEXT:    vmovx.f16 s6, s15
1601; CHECK-MVE-NEXT:    vcmp.f16 s3, s7
1602; CHECK-MVE-NEXT:    cset r0, vs
1603; CHECK-MVE-NEXT:    cmp r0, #0
1604; CHECK-MVE-NEXT:    vseleq.f16 s4, s6, s4
1605; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
1606; CHECK-MVE-NEXT:    cset r0, vs
1607; CHECK-MVE-NEXT:    cmp r0, #0
1608; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11
1609; CHECK-MVE-NEXT:    vins.f16 s3, s4
1610; CHECK-MVE-NEXT:    vpop {d8, d9}
1611; CHECK-MVE-NEXT:    bx lr
1612;
1613; CHECK-MVEFP-LABEL: vcmp_uno_v8f16:
1614; CHECK-MVEFP:       @ %bb.0: @ %entry
1615; CHECK-MVEFP-NEXT:    vpt.f16 le, q1, q0
1616; CHECK-MVEFP-NEXT:    vcmpt.f16 lt, q0, q1
1617; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3
1618; CHECK-MVEFP-NEXT:    bx lr
1619entry:
1620  %c = fcmp uno <8 x half> %src, %src2
1621  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
1622  ret <8 x half> %s
1623}
1624