| 3e4fbc6c | 08-Sep-2021 |
Gagandeep Singh <g.singh@nxp.com> |
crypto/dpaa_sec: support DES-CBC
add DES-CBC support and enable available cipher-only
test cases.
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com> |
| d38febb0 | 07-Sep-2021 |
Archana Muniganti <marchana@marvell.com> |
crypto/cnxk: add feature flag for cn9k lookaside IPsec
Update device feature flag to support lookaside IPsec for
cn9k.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Archana Mun
crypto/cnxk: add feature flag for cn9k lookaside IPsec
Update device feature flag to support lookaside IPsec for
cn9k.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
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|
| d9bf3a41 | 01-Sep-2021 |
Tejasree Kondoj <ktejasree@marvell.com> |
crypto/cnxk: support cn10k transport mode
Adding support for cn10k lookaside IPsec transport mode.
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com> |
| 9b4a4cc0 | 01-Sep-2021 |
Tejasree Kondoj <ktejasree@marvell.com> |
crypto/cnxk: support lookaside IPsec
Added lookaside IPsec AES-CBC-HMAC-SHA1
support to cnxk driver.
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com> |
| 9c30a6f3 | 29-Jul-2021 |
Henry Nadeau <hnadeau@iol.unh.edu> |
doc: fix spelling
Spell checked and corrected documentation.
If there are any errors, or I have changed something that wasn't an error
please reach out to me so I can update the dictionary.
Cc: sta
doc: fix spelling
Spell checked and corrected documentation.
If there are any errors, or I have changed something that wasn't an error
please reach out to me so I can update the dictionary.
Cc: stable@dpdk.org
Signed-off-by: Henry Nadeau <hnadeau@iol.unh.edu>
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|
| 29c875cc | 19-Jul-2021 |
Hemant Agrawal <hemant.agrawal@nxp.com> |
doc: remove SDK info from DPAA2 drivers guides
The prerequisite info is already present in the platform guide.
No need to repeat it in individual dev guides.
Signed-off-by: Hemant Agrawal <hemant.a
doc: remove SDK info from DPAA2 drivers guides
The prerequisite info is already present in the platform guide.
No need to repeat it in individual dev guides.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
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|
| e0f89d5e | 11-Jul-2021 |
Michael Shamis <michaelsh@marvell.com> |
crypto/mvsam: support IPsec offload
This patch provides the support for IPsec protocol
offload to the hardware.
Following security operations are added:
- session_create
- session_destroy
- capabili
crypto/mvsam: support IPsec offload
This patch provides the support for IPsec protocol
offload to the hardware.
Following security operations are added:
- session_create
- session_destroy
- capabilities_get
Signed-off-by: Michael Shamis <michaelsh@marvell.com>
Reviewed-by: Liron Himi <lironh@marvell.com>
Tested-by: Liron Himi <lironh@marvell.com>
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|
| 40e91195 | 20-Jul-2021 |
Shiri Kuzin <shirik@nvidia.com> |
test/crypto: support mlx5 driver
In order to test the new mlx5 crypto PMD, the driver is added to the
crypto test application.
Signed-off-by: Shiri Kuzin <shirik@nvidia.com>
Acked-by: Matan Azrad <
test/crypto: support mlx5 driver
In order to test the new mlx5 crypto PMD, the driver is added to the
crypto test application.
Signed-off-by: Shiri Kuzin <shirik@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
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|
| 8e196c08 | 20-Jul-2021 |
Suanming Mou <suanmingm@nvidia.com> |
crypto/mlx5: support enqueue/dequeue operations
The crypto operations are done with the WQE set which contains
one UMR WQE and one rdma write WQE. Most segments of the WQE
set are initialized proper
crypto/mlx5: support enqueue/dequeue operations
The crypto operations are done with the WQE set which contains
one UMR WQE and one rdma write WQE. Most segments of the WQE
set are initialized properly during queue setup, only limited
segments are initialized according to the crypto detail in the
datapath process.
This commit adds the enqueue and dequeue operations and updates
the WQE set segments accordingly.
Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Signed-off-by: Matan Azrad <matan@nvidia.com>
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
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|
| a1978aa2 | 20-Jul-2021 |
Suanming Mou <suanmingm@nvidia.com> |
crypto/mlx5: add maximum segments configuration
The mlx5 HW crypto operations are done by attaching crypto property
to a memory region. Once done, every access to the memory via the
crypto-enabled m
crypto/mlx5: add maximum segments configuration
The mlx5 HW crypto operations are done by attaching crypto property
to a memory region. Once done, every access to the memory via the
crypto-enabled memory region will result with in-line encryption or
decryption of the data.
As a result, the design choice is to provide two types of WQEs. One
is UMR WQE which sets the crypto property and the other is rdma write
WQE which sends DMA command to copy data from local MR to remote MR.
The size of the WQEs will be defined by a new devarg called
max_segs_num.
This devarg also defines the maximum segments in mbuf chain that will be
supported for crypto operations.
Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
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|
| e8db4413 | 20-Jul-2021 |
Suanming Mou <suanmingm@nvidia.com> |
crypto/mlx5: add keytag configuration
A keytag is a piece of data encrypted together with a DEK.
When a DEK is referenced by an MKEY.bsf through its index, the keytag is
also supplied in the BSF as
crypto/mlx5: add keytag configuration
A keytag is a piece of data encrypted together with a DEK.
When a DEK is referenced by an MKEY.bsf through its index, the keytag is
also supplied in the BSF as plaintext. The HW will decrypt the DEK (and
the attached keytag) and will fail the operation if the keytags don't
match.
This commit adds the configuration of the keytag with devargs.
Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
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|
| debb27ea | 20-Jul-2021 |
Shiri Kuzin <shirik@nvidia.com> |
crypto/mlx5: create login object using DevX
To work with crypto engines that are marked with wrapped_import_method,
a login session is required.
A crypto login object needs to be created using DevX.
crypto/mlx5: create login object using DevX
To work with crypto engines that are marked with wrapped_import_method,
a login session is required.
A crypto login object needs to be created using DevX.
The crypto login object contains:
- The credential pointer.
- The import_KEK pointer to be used for all secured information
communicated in crypto commands (key fields), including the
provided credential in this command.
- The credential secret, wrapped by the import_KEK indicated in
this command. Size includes 8 bytes IV for wrapping.
Added devargs for the required login values:
- wcs_file - path to the file containing the credential.
- import_kek_id - the import KEK pointer.
- credential_id - the credential pointer.
Create the login DevX object in pci_probe function and destroy it in
pci_remove.
Destroying the crypto login object means logout.
Signed-off-by: Shiri Kuzin <shirik@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
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|
| 247ad130 | 20-Jul-2021 |
Shiri Kuzin <shirik@nvidia.com> |
crypto/mlx5: add memory region management
Mellanox user space drivers don't deal with physical addresses as part
of a memory protection mechanism.
The device translates the given virtual address to
crypto/mlx5: add memory region management
Mellanox user space drivers don't deal with physical addresses as part
of a memory protection mechanism.
The device translates the given virtual address to a physical address
using the given memory key as an address space identifier.
That's why any mbuf virtual address is moved directly to the HW
descriptor(WQE).
The mapping between the virtual address to the physical address is saved
in MR configured by the kernel to the HW.
Each MR has a key that should also be moved to the WQE by the SW.
When the SW sees an unmapped address, it extends the address range and
creates a MR using a system call.
Add memory region cache management:
- 2 level cache per queue-pair - no locks.
- 1 shared cache between all the queues using a lock.
Using this way, the MR key search per data-path address is optimized.
Signed-off-by: Shiri Kuzin <shirik@nvidia.com>
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
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|
| 1004be3c | 20-Jul-2021 |
Shiri Kuzin <shirik@nvidia.com> |
crypto/mlx5: support session operations
Sessions are used in symmetric transformations in order to prepare
objects and data for packet processing stage.
A mlx5 session includes iv_offset, pointer t
crypto/mlx5: support session operations
Sessions are used in symmetric transformations in order to prepare
objects and data for packet processing stage.
A mlx5 session includes iv_offset, pointer to mlx5_crypto_dek struct,
bsf_size, bsf_p_type, block size index, encryption_order and encryption
standard.
Implement the next session operations:
mlx5_crypto_sym_session_get_size- returns the size of the mlx5
session struct.
mlx5_crypto_sym_session_configure- prepares the DEK hash-list
and saves all the session data.
mlx5_crypto_sym_session_clear - destroys the DEK hash-list.
Signed-off-by: Shiri Kuzin <shirik@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
show more ...
|
| a7c86884 | 20-Jul-2021 |
Shiri Kuzin <shirik@nvidia.com> |
crypto/mlx5: introduce Mellanox crypto driver
Add a new PMD for Mellanox devices- crypto PMD.
The crypto PMD will be supported starting Nvidia ConnectX6 and
BlueField2.
The crypto PMD will add the
crypto/mlx5: introduce Mellanox crypto driver
Add a new PMD for Mellanox devices- crypto PMD.
The crypto PMD will be supported starting Nvidia ConnectX6 and
BlueField2.
The crypto PMD will add the support of encryption and decryption using
the AES-XTS symmetric algorithm.
The crypto PMD requires rdma-core and uses mlx5 DevX.
This patch adds the PCI probing, basic functions, build files and
log utility.
Signed-off-by: Shiri Kuzin <shirik@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
show more ...
|
| 8f393c4f | 28-Jun-2021 |
Arek Kusztal <arkadiuszx.kusztal@intel.com> |
common/qat: support GEN4 devices
This commit adds support for fourth generation (GEN4) of
Intel QuickAssist (QAT) Technology devices.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acke
common/qat: support GEN4 devices
This commit adds support for fourth generation (GEN4) of
Intel QuickAssist (QAT) Technology devices.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
show more ...
|
| a13de42b | 23-Jun-2021 |
Fan Zhang <roy.fan.zhang@intel.com> |
doc: update dependencies for SW crypto PMDs
This patch updates the dependency requirement information
for aesni-gcm, aesni-mb, snow3g, zuc, and kasumi PMDs. Previously
building these PMDs with Make
doc: update dependencies for SW crypto PMDs
This patch updates the dependency requirement information
for aesni-gcm, aesni-mb, snow3g, zuc, and kasumi PMDs. Previously
building these PMDs with Make will fail when the system is
installed intel-ipsec-mb library version 1.0 or newer.
Since Make build system is deprecated already, instead of fixing
the issue the documentation is updated to state it.
Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com>
show more ...
|
| c7e6ab78 | 29-Jun-2021 |
Kiran Kumar K <kirankumark@marvell.com> |
test/crypto: add cnxk for asymmetric cases
Registered cn9k and cn10k for asymmetric crypto
autotest. Documentation and release notes are also
updated.
Signed-off-by: Kiran Kumar K <kirankumark@marv
test/crypto: add cnxk for asymmetric cases
Registered cn9k and cn10k for asymmetric crypto
autotest. Documentation and release notes are also
updated.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
show more ...
|
| ba57cbd5 | 29-Jun-2021 |
Anoob Joseph <anoobj@marvell.com> |
crypto/cnxk: add asymmetric capabilities
Add asymmetric crypto capabilities supported
by cn9k and cn10k PMDs. Documentation is also
updated for the same.
Signed-off-by: Anoob Joseph <anoobj@marvell
crypto/cnxk: add asymmetric capabilities
Add asymmetric crypto capabilities supported
by cn9k and cn10k PMDs. Documentation is also
updated for the same.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
show more ...
|
| 5a3513ca | 29-Jun-2021 |
Kiran Kumar K <kirankumark@marvell.com> |
crypto/cnxk: add asymmetric session
Add asymmetric crypto session ops for both cn9k
and cn10k PMD.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com> |
| 69407e79 | 29-Jun-2021 |
Anoob Joseph <anoobj@marvell.com> |
crypto/cnxk: add security capabilities
Add security capabilities supported by crypto cn10k PMD.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Srujana Challa <schalla@marvell.com>
crypto/cnxk: add security capabilities
Add security capabilities supported by crypto cn10k PMD.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
show more ...
|
| 5db3d7d0 | 25-Jun-2021 |
Tejasree Kondoj <ktejasree@marvell.com> |
test/crypto: enable cnxk
Enable tests for cn9k & cn10k crypto PMDs.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Archana Munig
test/crypto: enable cnxk
Enable tests for cn9k & cn10k crypto PMDs.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
show more ...
|
| bf662949 | 25-Jun-2021 |
Ankur Dwivedi <adwivedi@marvell.com> |
crypto/cnxk: add symmetric capabilities
Add symmetric crypto capabilities for cn9k & cn10k.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Sign
crypto/cnxk: add symmetric capabilities
Add symmetric crypto capabilities for cn9k & cn10k.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
show more ...
|
| 786963fd | 25-Jun-2021 |
Tejasree Kondoj <ktejasree@marvell.com> |
crypto/cnxk: add digest support
Add support for digest support for various algorithms.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-of
crypto/cnxk: add digest support
Add support for digest support for various algorithms.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
show more ...
|
| 546dff20 | 25-Jun-2021 |
Tejasree Kondoj <ktejasree@marvell.com> |
crypto/cnxk: add KASUMI decryption
Add KASUMI decrypt support.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Archana Muniganti
crypto/cnxk: add KASUMI decryption
Add KASUMI decrypt support.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
show more ...
|