1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_COMMON_H_ 6 #define RTE_PMD_MLX5_COMMON_H_ 7 8 #include <stdio.h> 9 10 #include <rte_pci.h> 11 #include <rte_debug.h> 12 #include <rte_atomic.h> 13 #include <rte_log.h> 14 #include <rte_kvargs.h> 15 #include <rte_devargs.h> 16 #include <rte_bitops.h> 17 #include <rte_lcore.h> 18 #include <rte_spinlock.h> 19 #include <rte_os_shim.h> 20 21 #include "mlx5_prm.h" 22 #include "mlx5_devx_cmds.h" 23 #include "mlx5_common_os.h" 24 25 /* Reported driver name. */ 26 #define MLX5_PCI_DRIVER_NAME "mlx5_pci" 27 28 /* Bit-field manipulation. */ 29 #define BITFIELD_DECLARE(bf, type, size) \ 30 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \ 31 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))] 32 #define BITFIELD_DEFINE(bf, type, size) \ 33 BITFIELD_DECLARE((bf), type, (size)) = { 0 } 34 #define BITFIELD_SET(bf, b) \ 35 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \ 36 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 37 #define BITFIELD_RESET(bf, b) \ 38 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \ 39 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 40 #define BITFIELD_ISSET(bf, b) \ 41 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \ 42 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))) 43 44 /* 45 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant 46 * manner. 47 */ 48 #define PMD_DRV_LOG_STRIP(a, b) a 49 #define PMD_DRV_LOG_OPAREN ( 50 #define PMD_DRV_LOG_CPAREN ) 51 #define PMD_DRV_LOG_COMMA , 52 53 /* Return the file name part of a path. */ 54 static inline const char * 55 pmd_drv_log_basename(const char *s) 56 { 57 const char *n = s; 58 59 while (*n) 60 if (*(n++) == '/') 61 s = n; 62 return s; 63 } 64 65 #define PMD_DRV_LOG___(level, type, name, ...) \ 66 rte_log(RTE_LOG_ ## level, \ 67 type, \ 68 RTE_FMT(name ": " \ 69 RTE_FMT_HEAD(__VA_ARGS__,), \ 70 RTE_FMT_TAIL(__VA_ARGS__,))) 71 72 #ifdef RTE_LIBRTE_MLX5_DEBUG 73 74 #define PMD_DRV_LOG__(level, type, name, ...) \ 75 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__) 76 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 77 PMD_DRV_LOG__(level, type, name,\ 78 s "\n" PMD_DRV_LOG_COMMA \ 79 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \ 80 __LINE__ PMD_DRV_LOG_COMMA \ 81 __func__, \ 82 __VA_ARGS__) 83 84 #else /* RTE_LIBRTE_MLX5_DEBUG */ 85 #define PMD_DRV_LOG__(level, type, name, ...) \ 86 PMD_DRV_LOG___(level, type, name, __VA_ARGS__) 87 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 88 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__) 89 90 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 91 92 /* claim_zero() does not perform any check when debugging is disabled. */ 93 #ifdef RTE_LIBRTE_MLX5_DEBUG 94 95 #define MLX5_ASSERT(exp) RTE_VERIFY(exp) 96 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0) 97 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0) 98 99 #else /* RTE_LIBRTE_MLX5_DEBUG */ 100 101 #define MLX5_ASSERT(exp) RTE_ASSERT(exp) 102 #define claim_zero(...) (__VA_ARGS__) 103 #define claim_nonzero(...) (__VA_ARGS__) 104 105 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 106 107 /* Allocate a buffer on the stack and fill it with a printf format string. */ 108 #define MKSTR(name, ...) \ 109 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \ 110 char name[mkstr_size_##name + 1]; \ 111 \ 112 snprintf(name, sizeof(name), "" __VA_ARGS__) 113 114 enum { 115 PCI_VENDOR_ID_MELLANOX = 0x15b3, 116 }; 117 118 enum { 119 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 120 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 121 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 122 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 123 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 124 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 125 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 126 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 127 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2, 128 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3, 129 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, 130 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, 131 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d, 132 PCI_DEVICE_ID_MELLANOX_CONNECTXVF = 0x101e, 133 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6, 134 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f, 135 PCI_DEVICE_ID_MELLANOX_CONNECTX7 = 0x1021, 136 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF = 0Xa2dc, 137 }; 138 139 /* Maximum number of simultaneous unicast MAC addresses. */ 140 #define MLX5_MAX_UC_MAC_ADDRESSES 128 141 /* Maximum number of simultaneous Multicast MAC addresses. */ 142 #define MLX5_MAX_MC_MAC_ADDRESSES 128 143 /* Maximum number of simultaneous MAC addresses. */ 144 #define MLX5_MAX_MAC_ADDRESSES \ 145 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES) 146 147 /* Recognized Infiniband device physical port name types. */ 148 enum mlx5_nl_phys_port_name_type { 149 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */ 150 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */ 151 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */ 152 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */ 153 MLX5_PHYS_PORT_NAME_TYPE_PFHPF, /* pf0, kernel ver >= 5.7, HPF rep */ 154 MLX5_PHYS_PORT_NAME_TYPE_PFSF, /* pf0sf0, kernel ver >= 5.0 */ 155 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ 156 }; 157 158 /** Switch information returned by mlx5_nl_switch_info(). */ 159 struct mlx5_switch_info { 160 uint32_t master:1; /**< Master device. */ 161 uint32_t representor:1; /**< Representor device. */ 162 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */ 163 int32_t ctrl_num; /**< Controller number (valid for c#pf#vf# format). */ 164 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */ 165 int32_t port_name; /**< Representor port name. */ 166 uint64_t switch_id; /**< Switch identifier. */ 167 }; 168 169 /* CQE status. */ 170 enum mlx5_cqe_status { 171 MLX5_CQE_STATUS_SW_OWN = -1, 172 MLX5_CQE_STATUS_HW_OWN = -2, 173 MLX5_CQE_STATUS_ERR = -3, 174 }; 175 176 /** 177 * Check whether CQE is valid. 178 * 179 * @param cqe 180 * Pointer to CQE. 181 * @param cqes_n 182 * Size of completion queue. 183 * @param ci 184 * Consumer index. 185 * 186 * @return 187 * The CQE status. 188 */ 189 static __rte_always_inline enum mlx5_cqe_status 190 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, 191 const uint16_t ci) 192 { 193 const uint16_t idx = ci & cqes_n; 194 const uint8_t op_own = cqe->op_own; 195 const uint8_t op_owner = MLX5_CQE_OWNER(op_own); 196 const uint8_t op_code = MLX5_CQE_OPCODE(op_own); 197 198 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID))) 199 return MLX5_CQE_STATUS_HW_OWN; 200 rte_io_rmb(); 201 if (unlikely(op_code == MLX5_CQE_RESP_ERR || 202 op_code == MLX5_CQE_REQ_ERR)) 203 return MLX5_CQE_STATUS_ERR; 204 return MLX5_CQE_STATUS_SW_OWN; 205 } 206 207 __rte_internal 208 int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr); 209 __rte_internal 210 int mlx5_get_ifname_sysfs(const char *ibdev_path, char *ifname); 211 212 213 enum mlx5_class { 214 MLX5_CLASS_INVALID, 215 MLX5_CLASS_NET = RTE_BIT64(0), 216 MLX5_CLASS_VDPA = RTE_BIT64(1), 217 MLX5_CLASS_REGEX = RTE_BIT64(2), 218 MLX5_CLASS_COMPRESS = RTE_BIT64(3), 219 }; 220 221 #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE 222 223 /* devX creation object */ 224 struct mlx5_devx_obj { 225 void *obj; /* The DV object. */ 226 int id; /* The object ID. */ 227 }; 228 229 /* UMR memory buffer used to define 1 entry in indirect mkey. */ 230 struct mlx5_klm { 231 uint32_t byte_count; 232 uint32_t mkey; 233 uint64_t address; 234 }; 235 236 __rte_internal 237 void mlx5_translate_port_name(const char *port_name_in, 238 struct mlx5_switch_info *port_info_out); 239 void mlx5_glue_constructor(void); 240 __rte_internal 241 void *mlx5_devx_alloc_uar(void *ctx, int mapping); 242 extern uint8_t haswell_broadwell_cpu; 243 244 __rte_internal 245 void mlx5_common_init(void); 246 247 #endif /* RTE_PMD_MLX5_COMMON_H_ */ 248