1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
3 */
4
5 #ifndef RTE_PMD_MLX5_COMMON_H_
6 #define RTE_PMD_MLX5_COMMON_H_
7
8 #include <stdio.h>
9
10 #include <rte_compat.h>
11 #include <rte_pci.h>
12 #include <bus_pci_driver.h>
13 #include <rte_debug.h>
14 #include <rte_atomic.h>
15 #include <rte_rwlock.h>
16 #include <rte_log.h>
17 #include <rte_kvargs.h>
18 #include <rte_devargs.h>
19 #include <rte_bitops.h>
20 #include <rte_lcore.h>
21 #include <rte_spinlock.h>
22 #include <rte_os_shim.h>
23
24 #include "mlx5_prm.h"
25 #include "mlx5_devx_cmds.h"
26 #include "mlx5_common_os.h"
27 #include "mlx5_common_mr.h"
28
29 /* Reported driver name. */
30 #define MLX5_PCI_DRIVER_NAME "mlx5_pci"
31 #define MLX5_AUXILIARY_DRIVER_NAME "mlx5_auxiliary"
32
33 /* Bit-field manipulation. */
34 #define BITFIELD_DECLARE(bf, type, size) \
35 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \
36 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))]
37 #define BITFIELD_DEFINE(bf, type, size) \
38 BITFIELD_DECLARE((bf), type, (size)) = { 0 }
39 #define BITFIELD_SET(bf, b) \
40 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \
41 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))
42 #define BITFIELD_RESET(bf, b) \
43 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \
44 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))
45 #define BITFIELD_ISSET(bf, b) \
46 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \
47 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))
48
49 /*
50 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant
51 * manner.
52 */
53 #define PMD_DRV_LOG_STRIP(a, b) a
54 #define PMD_DRV_LOG_OPAREN (
55 #define PMD_DRV_LOG_CPAREN )
56 #define PMD_DRV_LOG_COMMA ,
57
58 /* Return the file name part of a path. */
59 static inline const char *
pmd_drv_log_basename(const char * s)60 pmd_drv_log_basename(const char *s)
61 {
62 const char *n = s;
63
64 while (*n)
65 if (*(n++) == '/')
66 s = n;
67 return s;
68 }
69
70 #define PMD_DRV_LOG___(level, type, name, ...) \
71 rte_log(RTE_LOG_ ## level, \
72 type, \
73 RTE_FMT(name ": " \
74 RTE_FMT_HEAD(__VA_ARGS__,), \
75 RTE_FMT_TAIL(__VA_ARGS__,)))
76
77 #ifdef RTE_LIBRTE_MLX5_DEBUG
78
79 #define PMD_DRV_LOG__(level, type, name, ...) \
80 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__)
81 #define PMD_DRV_LOG_(level, type, name, s, ...) \
82 PMD_DRV_LOG__(level, type, name,\
83 s "\n" PMD_DRV_LOG_COMMA \
84 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \
85 __LINE__ PMD_DRV_LOG_COMMA \
86 __func__, \
87 __VA_ARGS__)
88
89 #else /* RTE_LIBRTE_MLX5_DEBUG */
90 #define PMD_DRV_LOG__(level, type, name, ...) \
91 PMD_DRV_LOG___(level, type, name, __VA_ARGS__)
92 #define PMD_DRV_LOG_(level, type, name, s, ...) \
93 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__)
94
95 #endif /* RTE_LIBRTE_MLX5_DEBUG */
96
97 /* claim_zero() does not perform any check when debugging is disabled. */
98 #ifdef RTE_LIBRTE_MLX5_DEBUG
99
100 #define MLX5_ASSERT(exp) RTE_VERIFY(exp)
101 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0)
102 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0)
103
104 #else /* RTE_LIBRTE_MLX5_DEBUG */
105
106 #define MLX5_ASSERT(exp) RTE_ASSERT(exp)
107 #define claim_zero(...) (__VA_ARGS__)
108 #define claim_nonzero(...) (__VA_ARGS__)
109
110 #endif /* RTE_LIBRTE_MLX5_DEBUG */
111
112 /**
113 * Returns true if debug mode is enabled for fast path operations.
114 */
115 static inline bool
mlx5_fp_debug_enabled(void)116 mlx5_fp_debug_enabled(void)
117 {
118 #ifdef RTE_LIBRTE_MLX5_DEBUG
119 return true;
120 #else
121 return false;
122 #endif
123 }
124
125 /* Allocate a buffer on the stack and fill it with a printf format string. */
126 #define MKSTR(name, ...) \
127 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \
128 char name[mkstr_size_##name + 1]; \
129 \
130 memset(name, 0, mkstr_size_##name + 1); \
131 snprintf(name, sizeof(name), "" __VA_ARGS__)
132
133 enum {
134 PCI_VENDOR_ID_MELLANOX = 0x15b3,
135 };
136
137 enum {
138 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
139 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
140 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
141 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
142 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
143 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
144 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
145 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
146 PCI_DEVICE_ID_MELLANOX_BLUEFIELD = 0xa2d2,
147 PCI_DEVICE_ID_MELLANOX_BLUEFIELDVF = 0xa2d3,
148 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
149 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
150 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
151 PCI_DEVICE_ID_MELLANOX_CONNECTXVF = 0x101e,
152 PCI_DEVICE_ID_MELLANOX_BLUEFIELD2 = 0xa2d6,
153 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f,
154 PCI_DEVICE_ID_MELLANOX_CONNECTX7 = 0x1021,
155 PCI_DEVICE_ID_MELLANOX_BLUEFIELD3 = 0Xa2dc,
156 };
157
158 /* Maximum number of simultaneous unicast MAC addresses. */
159 #define MLX5_MAX_UC_MAC_ADDRESSES 128
160 /* Maximum number of simultaneous Multicast MAC addresses. */
161 #define MLX5_MAX_MC_MAC_ADDRESSES 128
162 /* Maximum number of simultaneous MAC addresses. */
163 #define MLX5_MAX_MAC_ADDRESSES \
164 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES)
165
166 /* Recognized Infiniband device physical port name types. */
167 enum mlx5_nl_phys_port_name_type {
168 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
169 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
170 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
171 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
172 MLX5_PHYS_PORT_NAME_TYPE_PFHPF, /* pf0, kernel ver >= 5.7, HPF rep */
173 MLX5_PHYS_PORT_NAME_TYPE_PFSF, /* pf0sf0, kernel ver >= 5.0 */
174 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
175 };
176
177 /** Switch information returned by mlx5_nl_switch_info(). */
178 struct mlx5_switch_info {
179 uint32_t master:1; /**< Master device. */
180 uint32_t representor:1; /**< Representor device. */
181 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */
182 int32_t ctrl_num; /**< Controller number (valid for c#pf#vf# format). */
183 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
184 int32_t port_name; /**< Representor port name. */
185 int32_t mpesw_owner; /**< MPESW owner port number. */
186 uint64_t switch_id; /**< Switch identifier. */
187 };
188
189 /* CQE status. */
190 enum mlx5_cqe_status {
191 MLX5_CQE_STATUS_SW_OWN = -1,
192 MLX5_CQE_STATUS_HW_OWN = -2,
193 MLX5_CQE_STATUS_ERR = -3,
194 };
195
196 /**
197 * Check whether CQE has an error opcode.
198 *
199 * @param op_code
200 * Opcode to check.
201 *
202 * @return
203 * The CQE status.
204 */
205 static __rte_always_inline enum mlx5_cqe_status
check_cqe_error(const uint8_t op_code)206 check_cqe_error(const uint8_t op_code)
207 {
208 /* Prevent speculative reading of other fields in CQE until
209 * CQE is valid.
210 */
211 rte_atomic_thread_fence(rte_memory_order_acquire);
212
213 if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
214 op_code == MLX5_CQE_REQ_ERR))
215 return MLX5_CQE_STATUS_ERR;
216 return MLX5_CQE_STATUS_SW_OWN;
217 }
218
219 /**
220 * Check whether CQE is valid using owner bit.
221 *
222 * @param cqe
223 * Pointer to CQE.
224 * @param cqes_n
225 * Size of completion queue.
226 * @param ci
227 * Consumer index.
228 *
229 * @return
230 * The CQE status.
231 */
232 static __rte_always_inline enum mlx5_cqe_status
check_cqe(volatile struct mlx5_cqe * cqe,const uint16_t cqes_n,const uint16_t ci)233 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
234 const uint16_t ci)
235 {
236 const uint16_t idx = ci & cqes_n;
237 const uint8_t op_own = cqe->op_own;
238 const uint8_t op_owner = MLX5_CQE_OWNER(op_own);
239 const uint8_t op_code = MLX5_CQE_OPCODE(op_own);
240
241 if (unlikely((op_owner != (!!(idx))) ||
242 (op_code == MLX5_CQE_INVALID)))
243 return MLX5_CQE_STATUS_HW_OWN;
244 return check_cqe_error(op_code);
245 }
246
247 /**
248 * Check whether CQE is valid using validity iteration count.
249 *
250 * @param cqe
251 * Pointer to CQE.
252 * @param cqes_n
253 * Log 2 of completion queue size.
254 * @param ci
255 * Consumer index.
256 *
257 * @return
258 * The CQE status.
259 */
260 static __rte_always_inline enum mlx5_cqe_status
check_cqe_iteration(volatile struct mlx5_cqe * cqe,const uint16_t cqes_n,const uint32_t ci)261 check_cqe_iteration(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
262 const uint32_t ci)
263 {
264 const uint8_t op_own = cqe->op_own;
265 const uint8_t op_code = MLX5_CQE_OPCODE(op_own);
266 const uint8_t vic = ci >> cqes_n;
267
268 if (unlikely((cqe->validity_iteration_count != vic) ||
269 (op_code == MLX5_CQE_INVALID)))
270 return MLX5_CQE_STATUS_HW_OWN;
271 return check_cqe_error(op_code);
272 }
273
274 /*
275 * Get PCI address <DBDF> string from EAL device.
276 *
277 * @param[out] addr
278 * The output address buffer string
279 * @param[in] size
280 * The output buffer size
281 * @return
282 * - 0 on success.
283 * - Negative value and rte_errno is set otherwise.
284 */
285 __rte_internal
286 int mlx5_dev_to_pci_str(const struct rte_device *dev, char *addr, size_t size);
287
288 /*
289 * Get PCI address from sysfs of a PCI-related device.
290 *
291 * @param[in] dev_path
292 * The sysfs path should not point to the direct plain PCI device.
293 * Instead, the node "/device/" is used to access the real device.
294 * @param[out] pci_addr
295 * Parsed PCI address.
296 *
297 * @return
298 * - 0 on success.
299 * - Negative value and rte_errno is set otherwise.
300 */
301 __rte_internal
302 int mlx5_get_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr);
303
304 /*
305 * Get kernel network interface name from sysfs IB device path.
306 *
307 * @param[in] ibdev_path
308 * The sysfs path to IB device.
309 * @param[out] ifname
310 * Interface name output of size IF_NAMESIZE.
311 *
312 * @return
313 * - 0 on success.
314 * - Negative value and rte_errno is set otherwise.
315 */
316 __rte_internal
317 int mlx5_get_ifname_sysfs(const char *ibdev_path, char *ifname);
318
319 __rte_internal
320 int mlx5_auxiliary_get_child_name(const char *dev, const char *node,
321 char *child, size_t size);
322
323 enum mlx5_class {
324 MLX5_CLASS_INVALID,
325 MLX5_CLASS_ETH = RTE_BIT64(0),
326 MLX5_CLASS_VDPA = RTE_BIT64(1),
327 MLX5_CLASS_REGEX = RTE_BIT64(2),
328 MLX5_CLASS_COMPRESS = RTE_BIT64(3),
329 MLX5_CLASS_CRYPTO = RTE_BIT64(4),
330 };
331
332 #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE
333
334 /* devX creation object */
335 struct mlx5_devx_obj {
336 void *obj; /* The DV object. */
337 int id; /* The object ID. */
338 };
339
340 /* UMR memory buffer used to define 1 entry in indirect mkey. */
341 struct mlx5_klm {
342 uint32_t byte_count;
343 uint32_t mkey;
344 uint64_t address;
345 };
346
347 /** Control for key/values list. */
348 struct mlx5_kvargs_ctrl {
349 struct rte_kvargs *kvlist; /* Structure containing list of key/values.*/
350 bool is_used[RTE_KVARGS_MAX]; /* Indicator which devargs were used. */
351 };
352
353 /**
354 * Call a handler function for each key/value in the list of keys.
355 *
356 * For each key/value association that matches the given key, calls the
357 * handler function with the for a given arg_name passing the value on the
358 * dictionary for that key and a given extra argument.
359 *
360 * @param mkvlist
361 * The mlx5_kvargs structure.
362 * @param keys
363 * A list of keys to process (table of const char *, the last must be NULL).
364 * @param handler
365 * The function to call for each matching key.
366 * @param opaque_arg
367 * A pointer passed unchanged to the handler.
368 *
369 * @return
370 * - 0 on success
371 * - Negative on error
372 */
373 __rte_internal
374 int
375 mlx5_kvargs_process(struct mlx5_kvargs_ctrl *mkvlist, const char *const keys[],
376 arg_handler_t handler, void *opaque_arg);
377
378 /* All UAR arguments using doorbell register in datapath. */
379 struct mlx5_uar_data {
380 uint64_t *db;
381 /* The doorbell's virtual address mapped to the relevant HW UAR space.*/
382 #ifndef RTE_ARCH_64
383 rte_spinlock_t *sl_p;
384 /* Pointer to UAR access lock required for 32bit implementations. */
385 #endif /* RTE_ARCH_64 */
386 };
387
388 /* DevX UAR control structure. */
389 struct mlx5_uar {
390 struct mlx5_uar_data bf_db; /* UAR data for Blueflame register. */
391 struct mlx5_uar_data cq_db; /* UAR data for CQ arm db register. */
392 void *obj; /* DevX UAR object. */
393 bool dbnc; /* Doorbell mapped to non-cached region. */
394 #ifndef RTE_ARCH_64
395 rte_spinlock_t bf_sl;
396 rte_spinlock_t cq_sl;
397 /* UAR access locks required for 32bit implementations. */
398 #endif /* RTE_ARCH_64 */
399 };
400
401 /**
402 * Ring a doorbell and flush the update if requested.
403 *
404 * @param uar
405 * Pointer to UAR data structure.
406 * @param val
407 * value to write in big endian format.
408 * @param index
409 * Index of doorbell record.
410 * @param db_rec
411 * Address of doorbell record.
412 * @param flash
413 * Decide whether to flush the DB writing using a memory barrier.
414 */
415 static __rte_always_inline void
mlx5_doorbell_ring(struct mlx5_uar_data * uar,uint64_t val,uint32_t index,volatile uint32_t * db_rec,bool flash)416 mlx5_doorbell_ring(struct mlx5_uar_data *uar, uint64_t val, uint32_t index,
417 volatile uint32_t *db_rec, bool flash)
418 {
419 rte_io_wmb();
420 *db_rec = rte_cpu_to_be_32(index);
421 /* Ensure ordering between DB record actual update and UAR access. */
422 rte_wmb();
423 #ifdef RTE_ARCH_64
424 *uar->db = val;
425 #else /* !RTE_ARCH_64 */
426 rte_spinlock_lock(uar->sl_p);
427 *(volatile uint32_t *)uar->db = val;
428 rte_io_wmb();
429 *((volatile uint32_t *)uar->db + 1) = val >> 32;
430 rte_spinlock_unlock(uar->sl_p);
431 #endif
432 if (flash)
433 rte_wmb();
434 }
435
436 /**
437 * Get the doorbell register mapping type.
438 *
439 * @param uar_mmap_offset
440 * Mmap offset of Verbs/DevX UAR.
441 * @param page_size
442 * System page size
443 *
444 * @return
445 * 1 for non-cached, 0 otherwise.
446 */
447 static inline uint16_t
mlx5_db_map_type_get(off_t uar_mmap_offset,size_t page_size)448 mlx5_db_map_type_get(off_t uar_mmap_offset, size_t page_size)
449 {
450 off_t cmd = uar_mmap_offset / page_size;
451
452 cmd >>= MLX5_UAR_MMAP_CMD_SHIFT;
453 cmd &= MLX5_UAR_MMAP_CMD_MASK;
454 if (cmd == MLX5_MMAP_GET_NC_PAGES_CMD)
455 return 1;
456 return 0;
457 }
458
459 __rte_internal
460 void mlx5_translate_port_name(const char *port_name_in,
461 struct mlx5_switch_info *port_info_out);
462 void mlx5_glue_constructor(void);
463 extern uint8_t haswell_broadwell_cpu;
464
465 __rte_internal
466 void mlx5_common_init(void);
467
468 /*
469 * Common Driver Interface
470 *
471 * ConnectX common driver supports multiple classes: net, vDPA, regex, crypto
472 * and compress devices. This layer enables creating such multiple classes
473 * on a single device by allowing to bind multiple class-specific device
474 * drivers to attach to the common driver.
475 *
476 * ------------ ------------- -------------- ----------------- ------------
477 * | mlx5 net | | mlx5 vdpa | | mlx5 regex | | mlx5 compress | | mlx5 ... |
478 * | driver | | driver | | driver | | driver | | drivers |
479 * ------------ ------------- -------------- ----------------- ------------
480 * ||
481 * -----------------
482 * | mlx5 |
483 * | common driver |
484 * -----------------
485 * | |
486 * ----------- -----------------
487 * | mlx5 | | mlx5 |
488 * | pci dev | | auxiliary dev |
489 * ----------- -----------------
490 *
491 * - mlx5 PCI bus driver binds to mlx5 PCI devices defined by PCI ID table
492 * of all related devices.
493 * - mlx5 class driver such as net, vDPA, regex defines its specific
494 * PCI ID table and mlx5 bus driver probes matching class drivers.
495 * - mlx5 common driver is central place that validates supported
496 * class combinations.
497 * - mlx5 common driver hides bus difference by resolving device address
498 * from devargs, locating target RDMA device and probing with it.
499 */
500
501 /*
502 * Device configuration structure.
503 *
504 * Merged configuration from:
505 *
506 * - Device capabilities,
507 * - User device parameters disabled features.
508 */
509 struct mlx5_common_dev_config {
510 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
511 int dbnc; /* Skip doorbell register write barrier. */
512 int device_fd; /* Device file descriptor for importation. */
513 int pd_handle; /* Protection Domain handle for importation. */
514 unsigned int devx:1; /* Whether devx interface is available or not. */
515 unsigned int sys_mem_en:1; /* The default memory allocator. */
516 unsigned int mr_mempool_reg_en:1;
517 /* Allow/prevent implicit mempool memory registration. */
518 unsigned int mr_ext_memseg_en:1;
519 /* Whether memseg should be extended for MR creation. */
520 };
521
522 struct mlx5_common_device {
523 struct rte_device *dev;
524 TAILQ_ENTRY(mlx5_common_device) next;
525 uint32_t classes_loaded;
526 void *ctx; /* Verbs/DV/DevX context. */
527 void *pd; /* Protection Domain. */
528 uint32_t pdn; /* Protection Domain Number. */
529 struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */
530 struct mlx5_common_dev_config config; /* Device configuration. */
531 };
532
533 /**
534 * Indicates whether PD and CTX are imported from another process,
535 * or created by this process.
536 *
537 * @param cdev
538 * Pointer to common device.
539 *
540 * @return
541 * True if PD and CTX are imported from another process, False otherwise.
542 */
543 static inline bool
mlx5_imported_pd_and_ctx(struct mlx5_common_device * cdev)544 mlx5_imported_pd_and_ctx(struct mlx5_common_device *cdev)
545 {
546 return cdev->config.device_fd != MLX5_ARG_UNSET &&
547 cdev->config.pd_handle != MLX5_ARG_UNSET;
548 }
549
550 /**
551 * Initialization function for the driver called during device probing.
552 */
553 typedef int (mlx5_class_driver_probe_t)(struct mlx5_common_device *cdev,
554 struct mlx5_kvargs_ctrl *mkvlist);
555
556 /**
557 * Uninitialization function for the driver called during hot-unplugging.
558 */
559 typedef int (mlx5_class_driver_remove_t)(struct mlx5_common_device *cdev);
560
561 /** Device already probed can be probed again to check for new ports. */
562 #define MLX5_DRV_PROBE_AGAIN 0x0004
563
564 /**
565 * A structure describing a mlx5 common class driver.
566 */
567 struct mlx5_class_driver {
568 TAILQ_ENTRY(mlx5_class_driver) next;
569 enum mlx5_class drv_class; /**< Class of this driver. */
570 const char *name; /**< Driver name. */
571 mlx5_class_driver_probe_t *probe; /**< Device probe function. */
572 mlx5_class_driver_remove_t *remove; /**< Device remove function. */
573 const struct rte_pci_id *id_table; /**< ID table, NULL terminated. */
574 uint32_t probe_again:1;
575 /**< Device already probed can be probed again to check new device. */
576 uint32_t intr_lsc:1; /**< Supports link state interrupt. */
577 uint32_t intr_rmv:1; /**< Supports device remove interrupt. */
578 };
579
580 /**
581 * Register a mlx5 device driver.
582 *
583 * @param driver
584 * A pointer to a mlx5_driver structure describing the driver
585 * to be registered.
586 */
587 __rte_internal
588 void
589 mlx5_class_driver_register(struct mlx5_class_driver *driver);
590
591 /**
592 * Test device is a PCI bus device.
593 *
594 * @param dev
595 * Pointer to device.
596 *
597 * @return
598 * - True on device devargs is a PCI bus device.
599 * - False otherwise.
600 */
601 __rte_internal
602 bool
603 mlx5_dev_is_pci(const struct rte_device *dev);
604
605 /**
606 * Test PCI device is a VF device.
607 *
608 * @param pci_dev
609 * Pointer to PCI device.
610 *
611 * @return
612 * - True on PCI device is a VF device.
613 * - False otherwise.
614 */
615 __rte_internal
616 bool
617 mlx5_dev_is_vf_pci(const struct rte_pci_device *pci_dev);
618
619 __rte_internal
620 int
621 mlx5_dev_mempool_subscribe(struct mlx5_common_device *cdev);
622
623 __rte_internal
624 void
625 mlx5_dev_mempool_unregister(struct mlx5_common_device *cdev,
626 struct rte_mempool *mp);
627
628 __rte_internal
629 int
630 mlx5_devx_uar_prepare(struct mlx5_common_device *cdev, struct mlx5_uar *uar);
631
632 __rte_internal
633 void
634 mlx5_devx_uar_release(struct mlx5_uar *uar);
635
636 /* mlx5_common_os.c */
637
638 int mlx5_os_open_device(struct mlx5_common_device *cdev, uint32_t classes);
639 int mlx5_os_pd_prepare(struct mlx5_common_device *cdev);
640 int mlx5_os_pd_release(struct mlx5_common_device *cdev);
641 int mlx5_os_remote_pd_and_ctx_validate(struct mlx5_common_dev_config *config);
642
643 /* mlx5 PMD wrapped MR struct. */
644 struct mlx5_pmd_wrapped_mr {
645 uint32_t lkey;
646 void *addr;
647 size_t len;
648 void *obj; /* verbs mr object or devx umem object. */
649 void *imkey; /* DevX indirect mkey object. */
650 };
651
652 __rte_internal
653 int
654 mlx5_os_wrapped_mkey_create(void *ctx, void *pd, uint32_t pdn, void *addr,
655 size_t length, struct mlx5_pmd_wrapped_mr *pmd_mr);
656
657 __rte_internal
658 void
659 mlx5_os_wrapped_mkey_destroy(struct mlx5_pmd_wrapped_mr *pmd_mr);
660
661 #endif /* RTE_PMD_MLX5_COMMON_H_ */
662