1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 #include <rte_compat.h> 11 12 /* 13 * Defines the amount of retries to allocate the first UAR in the page. 14 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as 15 * UAR base address if UAR was not the first object in the UAR page. 16 * It caused the PMD failure and we should try to get another UAR 17 * till we get the first one with non-NULL base address returned. 18 */ 19 #define MLX5_ALLOC_UAR_RETRY 32 20 21 /* This is limitation of libibverbs: in length variable type is u16. */ 22 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 23 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 24 25 struct mlx5_devx_mkey_attr { 26 uint64_t addr; 27 uint64_t size; 28 uint32_t umem_id; 29 uint32_t pd; 30 uint32_t log_entity_size; 31 uint32_t pg_access:1; 32 uint32_t relaxed_ordering_write:1; 33 uint32_t relaxed_ordering_read:1; 34 uint32_t umr_en:1; 35 uint32_t crypto_en:2; 36 uint32_t set_remote_rw:1; 37 struct mlx5_klm *klm_array; 38 int klm_num; 39 }; 40 41 /* HCA qos attributes. */ 42 struct mlx5_hca_qos_attr { 43 uint32_t sup:1; /* Whether QOS is supported. */ 44 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ 45 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 46 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 47 uint32_t flow_meter:1; 48 /* 49 * Flow meter is supported, updated version. 50 * When flow_meter is 1, it indicates that REG_C sharing is supported. 51 * If flow_meter is 1, flow_meter_old is also 1. 52 * Using older driver versions, flow_meter_old can be 1 53 * while flow_meter is 0. 54 */ 55 uint32_t flow_meter_aso_sup:1; 56 /* Whether FLOW_METER_ASO Object is supported. */ 57 uint8_t log_max_flow_meter; 58 /* Power of the maximum supported meters. */ 59 uint8_t flow_meter_reg_c_ids; 60 /* Bitmap of the reg_Cs available for flow meter to use. */ 61 uint32_t log_meter_aso_granularity:5; 62 /* Power of the minimum allocation granularity Object. */ 63 uint32_t log_meter_aso_max_alloc:5; 64 /* Power of the maximum allocation granularity Object. */ 65 uint32_t log_max_num_meter_aso:5; 66 /* Power of the maximum number of supported objects. */ 67 68 }; 69 70 struct mlx5_hca_vdpa_attr { 71 uint8_t virtio_queue_type; 72 uint32_t valid:1; 73 uint32_t desc_tunnel_offload_type:1; 74 uint32_t eth_frame_offload_type:1; 75 uint32_t virtio_version_1_0:1; 76 uint32_t tso_ipv4:1; 77 uint32_t tso_ipv6:1; 78 uint32_t tx_csum:1; 79 uint32_t rx_csum:1; 80 uint32_t event_mode:3; 81 uint32_t log_doorbell_stride:5; 82 uint32_t log_doorbell_bar_size:5; 83 uint32_t queue_counters_valid:1; 84 uint32_t max_num_virtio_queues; 85 struct { 86 uint32_t a; 87 uint32_t b; 88 } umems[3]; 89 uint64_t doorbell_bar_offset; 90 }; 91 92 struct mlx5_hca_flow_attr { 93 uint32_t tunnel_header_0_1; 94 uint32_t tunnel_header_2_3; 95 }; 96 97 /* HCA supports this number of time periods for LRO. */ 98 #define MLX5_LRO_NUM_SUPP_PERIODS 4 99 100 /* HCA attributes. */ 101 struct mlx5_hca_attr { 102 uint32_t eswitch_manager:1; 103 uint32_t flow_counters_dump:1; 104 uint32_t log_max_rqt_size:5; 105 uint32_t parse_graph_flex_node:1; 106 uint8_t flow_counter_bulk_alloc_bitmap; 107 uint32_t eth_net_offloads:1; 108 uint32_t eth_virt:1; 109 uint32_t wqe_vlan_insert:1; 110 uint32_t csum_cap:1; 111 uint32_t wqe_inline_mode:2; 112 uint32_t vport_inline_mode:3; 113 uint32_t tunnel_stateless_geneve_rx:1; 114 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 115 uint32_t tunnel_stateless_gtp:1; 116 uint32_t lro_cap:1; 117 uint32_t tunnel_lro_gre:1; 118 uint32_t tunnel_lro_vxlan:1; 119 uint32_t lro_max_msg_sz_mode:2; 120 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 121 uint16_t lro_min_mss_size; 122 uint32_t flex_parser_protocols; 123 uint32_t max_geneve_tlv_options; 124 uint32_t max_geneve_tlv_option_data_len; 125 uint32_t hairpin:1; 126 uint32_t log_max_hairpin_queues:5; 127 uint32_t log_max_hairpin_wq_data_sz:5; 128 uint32_t log_max_hairpin_num_packets:5; 129 uint32_t vhca_id:16; 130 uint32_t relaxed_ordering_write:1; 131 uint32_t relaxed_ordering_read:1; 132 uint32_t access_register_user:1; 133 uint32_t wqe_index_ignore:1; 134 uint32_t cross_channel:1; 135 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 136 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 137 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 138 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 139 uint32_t scatter_fcs_w_decap_disable:1; 140 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 141 uint32_t roce:1; 142 uint32_t rq_ts_format:2; 143 uint32_t sq_ts_format:2; 144 uint32_t qp_ts_format:2; 145 uint32_t regex:1; 146 uint32_t reg_c_preserve:1; 147 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ 148 uint32_t crypto:1; /* Crypto engine is supported. */ 149 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ 150 uint32_t dek:1; /* General obj type DEK is supported. */ 151 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ 152 uint32_t credential:1; /* General obj type CREDENTIAL supported. */ 153 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ 154 uint32_t regexp_num_of_engines; 155 uint32_t log_max_ft_sampler_num:8; 156 uint32_t inner_ipv4_ihl:1; 157 uint32_t outer_ipv4_ihl:1; 158 uint32_t geneve_tlv_opt; 159 uint32_t cqe_compression:1; 160 uint32_t mini_cqe_resp_flow_tag:1; 161 uint32_t mini_cqe_resp_l3_l4_tag:1; 162 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ 163 struct mlx5_hca_qos_attr qos; 164 struct mlx5_hca_vdpa_attr vdpa; 165 struct mlx5_hca_flow_attr flow; 166 int log_max_qp_sz; 167 int log_max_cq_sz; 168 int log_max_qp; 169 int log_max_cq; 170 uint32_t log_max_pd; 171 uint32_t log_max_mrw_sz; 172 uint32_t log_max_srq; 173 uint32_t log_max_srq_sz; 174 uint32_t rss_ind_tbl_cap; 175 uint32_t mmo_dma_en:1; 176 uint32_t mmo_compress_en:1; 177 uint32_t mmo_decompress_en:1; 178 uint32_t compress_min_block_size:4; 179 uint32_t log_max_mmo_dma:5; 180 uint32_t log_max_mmo_compress:5; 181 uint32_t log_max_mmo_decompress:5; 182 uint32_t umr_modify_entity_size_disabled:1; 183 uint32_t umr_indirect_mkey_disabled:1; 184 }; 185 186 struct mlx5_devx_wq_attr { 187 uint32_t wq_type:4; 188 uint32_t wq_signature:1; 189 uint32_t end_padding_mode:2; 190 uint32_t cd_slave:1; 191 uint32_t hds_skip_first_sge:1; 192 uint32_t log2_hds_buf_size:3; 193 uint32_t page_offset:5; 194 uint32_t lwm:16; 195 uint32_t pd:24; 196 uint32_t uar_page:24; 197 uint64_t dbr_addr; 198 uint32_t hw_counter; 199 uint32_t sw_counter; 200 uint32_t log_wq_stride:4; 201 uint32_t log_wq_pg_sz:5; 202 uint32_t log_wq_sz:5; 203 uint32_t dbr_umem_valid:1; 204 uint32_t wq_umem_valid:1; 205 uint32_t log_hairpin_num_packets:5; 206 uint32_t log_hairpin_data_sz:5; 207 uint32_t single_wqe_log_num_of_strides:4; 208 uint32_t two_byte_shift_en:1; 209 uint32_t single_stride_log_num_of_bytes:3; 210 uint32_t dbr_umem_id; 211 uint32_t wq_umem_id; 212 uint64_t wq_umem_offset; 213 }; 214 215 /* Create RQ attributes structure, used by create RQ operation. */ 216 struct mlx5_devx_create_rq_attr { 217 uint32_t rlky:1; 218 uint32_t delay_drop_en:1; 219 uint32_t scatter_fcs:1; 220 uint32_t vsd:1; 221 uint32_t mem_rq_type:4; 222 uint32_t state:4; 223 uint32_t flush_in_error_en:1; 224 uint32_t hairpin:1; 225 uint32_t ts_format:2; 226 uint32_t user_index:24; 227 uint32_t cqn:24; 228 uint32_t counter_set_id:8; 229 uint32_t rmpn:24; 230 struct mlx5_devx_wq_attr wq_attr; 231 }; 232 233 /* Modify RQ attributes structure, used by modify RQ operation. */ 234 struct mlx5_devx_modify_rq_attr { 235 uint32_t rqn:24; 236 uint32_t rq_state:4; /* Current RQ state. */ 237 uint32_t state:4; /* Required RQ state. */ 238 uint32_t scatter_fcs:1; 239 uint32_t vsd:1; 240 uint32_t counter_set_id:8; 241 uint32_t hairpin_peer_sq:24; 242 uint32_t hairpin_peer_vhca:16; 243 uint64_t modify_bitmask; 244 uint32_t lwm:16; /* Contained WQ lwm. */ 245 }; 246 247 struct mlx5_rx_hash_field_select { 248 uint32_t l3_prot_type:1; 249 uint32_t l4_prot_type:1; 250 uint32_t selected_fields:30; 251 }; 252 253 /* TIR attributes structure, used by TIR operations. */ 254 struct mlx5_devx_tir_attr { 255 uint32_t disp_type:4; 256 uint32_t lro_timeout_period_usecs:16; 257 uint32_t lro_enable_mask:4; 258 uint32_t lro_max_msg_sz:8; 259 uint32_t inline_rqn:24; 260 uint32_t rx_hash_symmetric:1; 261 uint32_t tunneled_offload_en:1; 262 uint32_t indirect_table:24; 263 uint32_t rx_hash_fn:4; 264 uint32_t self_lb_block:2; 265 uint32_t transport_domain:24; 266 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 267 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 268 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 269 }; 270 271 /* TIR attributes structure, used by TIR modify. */ 272 struct mlx5_devx_modify_tir_attr { 273 uint32_t tirn:24; 274 uint64_t modify_bitmask; 275 struct mlx5_devx_tir_attr tir; 276 }; 277 278 /* RQT attributes structure, used by RQT operations. */ 279 struct mlx5_devx_rqt_attr { 280 uint8_t rq_type; 281 uint32_t rqt_max_size:16; 282 uint32_t rqt_actual_size:16; 283 uint32_t rq_list[]; 284 }; 285 286 /* TIS attributes structure. */ 287 struct mlx5_devx_tis_attr { 288 uint32_t strict_lag_tx_port_affinity:1; 289 uint32_t tls_en:1; 290 uint32_t lag_tx_port_affinity:4; 291 uint32_t prio:4; 292 uint32_t transport_domain:24; 293 }; 294 295 /* SQ attributes structure, used by SQ create operation. */ 296 struct mlx5_devx_create_sq_attr { 297 uint32_t rlky:1; 298 uint32_t cd_master:1; 299 uint32_t fre:1; 300 uint32_t flush_in_error_en:1; 301 uint32_t allow_multi_pkt_send_wqe:1; 302 uint32_t min_wqe_inline_mode:3; 303 uint32_t state:4; 304 uint32_t reg_umr:1; 305 uint32_t allow_swp:1; 306 uint32_t hairpin:1; 307 uint32_t non_wire:1; 308 uint32_t static_sq_wq:1; 309 uint32_t ts_format:2; 310 uint32_t user_index:24; 311 uint32_t cqn:24; 312 uint32_t packet_pacing_rate_limit_index:16; 313 uint32_t tis_lst_sz:16; 314 uint32_t tis_num:24; 315 struct mlx5_devx_wq_attr wq_attr; 316 }; 317 318 /* SQ attributes structure, used by SQ modify operation. */ 319 struct mlx5_devx_modify_sq_attr { 320 uint32_t sq_state:4; 321 uint32_t state:4; 322 uint32_t hairpin_peer_rq:24; 323 uint32_t hairpin_peer_vhca:16; 324 }; 325 326 327 /* CQ attributes structure, used by CQ operations. */ 328 struct mlx5_devx_cq_attr { 329 uint32_t q_umem_valid:1; 330 uint32_t db_umem_valid:1; 331 uint32_t use_first_only:1; 332 uint32_t overrun_ignore:1; 333 uint32_t cqe_comp_en:1; 334 uint32_t mini_cqe_res_format:2; 335 uint32_t mini_cqe_res_format_ext:2; 336 uint32_t log_cq_size:5; 337 uint32_t log_page_size:5; 338 uint32_t uar_page_id; 339 uint32_t q_umem_id; 340 uint64_t q_umem_offset; 341 uint32_t db_umem_id; 342 uint64_t db_umem_offset; 343 uint32_t eqn; 344 uint64_t db_addr; 345 }; 346 347 /* Virtq attributes structure, used by VIRTQ operations. */ 348 struct mlx5_devx_virtq_attr { 349 uint16_t hw_available_index; 350 uint16_t hw_used_index; 351 uint16_t q_size; 352 uint32_t pd:24; 353 uint32_t virtio_version_1_0:1; 354 uint32_t tso_ipv4:1; 355 uint32_t tso_ipv6:1; 356 uint32_t tx_csum:1; 357 uint32_t rx_csum:1; 358 uint32_t event_mode:3; 359 uint32_t state:4; 360 uint32_t hw_latency_mode:2; 361 uint32_t hw_max_latency_us:12; 362 uint32_t hw_max_pending_comp:16; 363 uint32_t dirty_bitmap_dump_enable:1; 364 uint32_t dirty_bitmap_mkey; 365 uint32_t dirty_bitmap_size; 366 uint32_t mkey; 367 uint32_t qp_id; 368 uint32_t queue_index; 369 uint32_t tis_id; 370 uint32_t counters_obj_id; 371 uint64_t dirty_bitmap_addr; 372 uint64_t type; 373 uint64_t desc_addr; 374 uint64_t used_addr; 375 uint64_t available_addr; 376 struct { 377 uint32_t id; 378 uint32_t size; 379 uint64_t offset; 380 } umems[3]; 381 uint8_t error_type; 382 }; 383 384 385 struct mlx5_devx_qp_attr { 386 uint32_t pd:24; 387 uint32_t uar_index:24; 388 uint32_t cqn:24; 389 uint32_t log_page_size:5; 390 uint32_t rq_size:17; /* Must be power of 2. */ 391 uint32_t log_rq_stride:3; 392 uint32_t sq_size:17; /* Must be power of 2. */ 393 uint32_t ts_format:2; 394 uint32_t dbr_umem_valid:1; 395 uint32_t dbr_umem_id; 396 uint64_t dbr_address; 397 uint32_t wq_umem_id; 398 uint64_t wq_umem_offset; 399 }; 400 401 struct mlx5_devx_virtio_q_couners_attr { 402 uint64_t received_desc; 403 uint64_t completed_desc; 404 uint32_t error_cqes; 405 uint32_t bad_desc_errors; 406 uint32_t exceed_max_chain; 407 uint32_t invalid_buffer; 408 }; 409 410 /* 411 * graph flow match sample attributes structure, 412 * used by flex parser operations. 413 */ 414 struct mlx5_devx_match_sample_attr { 415 uint32_t flow_match_sample_en:1; 416 uint32_t flow_match_sample_field_offset:16; 417 uint32_t flow_match_sample_offset_mode:4; 418 uint32_t flow_match_sample_field_offset_mask; 419 uint32_t flow_match_sample_field_offset_shift:4; 420 uint32_t flow_match_sample_field_base_offset:8; 421 uint32_t flow_match_sample_tunnel_mode:3; 422 uint32_t flow_match_sample_field_id; 423 }; 424 425 /* graph node arc attributes structure, used by flex parser operations. */ 426 struct mlx5_devx_graph_arc_attr { 427 uint32_t compare_condition_value:16; 428 uint32_t start_inner_tunnel:1; 429 uint32_t arc_parse_graph_node:8; 430 uint32_t parse_graph_node_handle; 431 }; 432 433 /* Maximal number of samples per graph node. */ 434 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 435 436 /* Maximal number of input/output arcs per graph node. */ 437 #define MLX5_GRAPH_NODE_ARC_NUM 8 438 439 /* parse graph node attributes structure, used by flex parser operations. */ 440 struct mlx5_devx_graph_node_attr { 441 uint32_t modify_field_select; 442 uint32_t header_length_mode:4; 443 uint32_t header_length_base_value:16; 444 uint32_t header_length_field_shift:4; 445 uint32_t header_length_field_offset:16; 446 uint32_t header_length_field_mask; 447 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 448 uint32_t next_header_field_offset:16; 449 uint32_t next_header_field_size:5; 450 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 451 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 452 }; 453 454 /* Encryption key size is up to 1024 bit, 128 bytes. */ 455 #define MLX5_CRYPTO_KEY_MAX_SIZE 128 456 457 struct mlx5_devx_dek_attr { 458 uint32_t key_size:4; 459 uint32_t has_keytag:1; 460 uint32_t key_purpose:4; 461 uint32_t pd:24; 462 uint64_t opaque; 463 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 464 }; 465 466 struct mlx5_devx_import_kek_attr { 467 uint64_t modify_field_select; 468 uint32_t state:8; 469 uint32_t key_size:4; 470 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 471 }; 472 473 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48 474 475 struct mlx5_devx_credential_attr { 476 uint64_t modify_field_select; 477 uint32_t state:8; 478 uint32_t credential_role:8; 479 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 480 }; 481 482 struct mlx5_devx_crypto_login_attr { 483 uint64_t modify_field_select; 484 uint32_t credential_pointer:24; 485 uint32_t session_import_kek_ptr:24; 486 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 487 }; 488 489 /* mlx5_devx_cmds.c */ 490 491 __rte_internal 492 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 493 uint32_t bulk_sz); 494 __rte_internal 495 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 496 __rte_internal 497 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 498 int clear, uint32_t n_counters, 499 uint64_t *pkts, uint64_t *bytes, 500 uint32_t mkey, void *addr, 501 void *cmd_comp, 502 uint64_t async_id); 503 __rte_internal 504 int mlx5_devx_cmd_query_hca_attr(void *ctx, 505 struct mlx5_hca_attr *attr); 506 __rte_internal 507 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 508 struct mlx5_devx_mkey_attr *attr); 509 __rte_internal 510 int mlx5_devx_get_out_command_status(void *out); 511 __rte_internal 512 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 513 uint32_t *tis_td); 514 __rte_internal 515 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 516 struct mlx5_devx_create_rq_attr *rq_attr, 517 int socket); 518 __rte_internal 519 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 520 struct mlx5_devx_modify_rq_attr *rq_attr); 521 __rte_internal 522 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 523 struct mlx5_devx_tir_attr *tir_attr); 524 __rte_internal 525 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 526 struct mlx5_devx_rqt_attr *rqt_attr); 527 __rte_internal 528 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 529 struct mlx5_devx_create_sq_attr *sq_attr); 530 __rte_internal 531 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 532 struct mlx5_devx_modify_sq_attr *sq_attr); 533 __rte_internal 534 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 535 struct mlx5_devx_tis_attr *tis_attr); 536 __rte_internal 537 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 538 __rte_internal 539 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 540 FILE *file); 541 __rte_internal 542 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); 543 __rte_internal 544 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 545 struct mlx5_devx_cq_attr *attr); 546 __rte_internal 547 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 548 struct mlx5_devx_virtq_attr *attr); 549 __rte_internal 550 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 551 struct mlx5_devx_virtq_attr *attr); 552 __rte_internal 553 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 554 struct mlx5_devx_virtq_attr *attr); 555 __rte_internal 556 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 557 struct mlx5_devx_qp_attr *attr); 558 __rte_internal 559 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 560 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 561 __rte_internal 562 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 563 struct mlx5_devx_rqt_attr *rqt_attr); 564 __rte_internal 565 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 566 struct mlx5_devx_modify_tir_attr *tir_attr); 567 __rte_internal 568 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 569 uint32_t ids[], uint32_t num); 570 571 __rte_internal 572 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, 573 struct mlx5_devx_graph_node_attr *data); 574 575 __rte_internal 576 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 577 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 578 579 __rte_internal 580 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, 581 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 582 583 __rte_internal 584 struct mlx5_devx_obj * 585 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 586 uint16_t class, uint8_t type, uint8_t len); 587 588 /** 589 * Create virtio queue counters object DevX API. 590 * 591 * @param[in] ctx 592 * Device context. 593 594 * @return 595 * The DevX object created, NULL otherwise and rte_errno is set. 596 */ 597 __rte_internal 598 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 599 600 /** 601 * Query virtio queue counters object using DevX API. 602 * 603 * @param[in] couners_obj 604 * Pointer to virtq object structure. 605 * @param [in/out] attr 606 * Pointer to virtio queue counters attributes structure. 607 * 608 * @return 609 * 0 on success, a negative errno value otherwise and rte_errno is set. 610 */ 611 __rte_internal 612 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 613 struct mlx5_devx_virtio_q_couners_attr *attr); 614 __rte_internal 615 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 616 uint32_t pd); 617 __rte_internal 618 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 619 620 __rte_internal 621 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); 622 623 __rte_internal 624 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); 625 __rte_internal 626 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 627 uint32_t *out_of_buffers); 628 __rte_internal 629 struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, 630 uint32_t pd, uint32_t log_obj_size); 631 632 /** 633 * Create general object of type FLOW_METER_ASO using DevX API.. 634 * 635 * @param[in] ctx 636 * Device context. 637 * @param [in] pd 638 * PD value to associate the FLOW_METER_ASO object with. 639 * @param [in] log_obj_size 640 * log_obj_size define to allocate number of 2 * meters 641 * in one FLOW_METER_ASO object. 642 * 643 * @return 644 * The DevX object created, NULL otherwise and rte_errno is set. 645 */ 646 __rte_internal 647 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, 648 uint32_t pd, uint32_t log_obj_size); 649 __rte_internal 650 struct mlx5_devx_obj * 651 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); 652 653 __rte_internal 654 struct mlx5_devx_obj * 655 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 656 struct mlx5_devx_import_kek_attr *attr); 657 658 __rte_internal 659 struct mlx5_devx_obj * 660 mlx5_devx_cmd_create_credential_obj(void *ctx, 661 struct mlx5_devx_credential_attr *attr); 662 663 __rte_internal 664 struct mlx5_devx_obj * 665 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 666 struct mlx5_devx_crypto_login_attr *attr); 667 668 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 669