1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2021 NVIDIA Corporation & Affiliates 3 */ 4 5 #include <rte_malloc.h> 6 #include <rte_mempool.h> 7 #include <rte_errno.h> 8 #include <rte_log.h> 9 #include <rte_bus_pci.h> 10 #include <rte_memory.h> 11 12 #include <mlx5_glue.h> 13 #include <mlx5_common.h> 14 #include <mlx5_devx_cmds.h> 15 #include <mlx5_common_os.h> 16 17 #include "mlx5_crypto_utils.h" 18 #include "mlx5_crypto.h" 19 20 #define MLX5_CRYPTO_DRIVER_NAME crypto_mlx5 21 #define MLX5_CRYPTO_LOG_NAME pmd.crypto.mlx5 22 #define MLX5_CRYPTO_MAX_QPS 1024 23 #define MLX5_CRYPTO_MAX_SEGS 56 24 25 #define MLX5_CRYPTO_FEATURE_FLAGS \ 26 (RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | \ 27 RTE_CRYPTODEV_FF_IN_PLACE_SGL | RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT | \ 28 RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT | \ 29 RTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT | \ 30 RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT | \ 31 RTE_CRYPTODEV_FF_CIPHER_WRAPPED_KEY | \ 32 RTE_CRYPTODEV_FF_CIPHER_MULTIPLE_DATA_UNITS) 33 34 TAILQ_HEAD(mlx5_crypto_privs, mlx5_crypto_priv) mlx5_crypto_priv_list = 35 TAILQ_HEAD_INITIALIZER(mlx5_crypto_priv_list); 36 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER; 37 38 int mlx5_crypto_logtype; 39 40 uint8_t mlx5_crypto_driver_id; 41 42 const struct rte_cryptodev_capabilities mlx5_crypto_caps[] = { 43 { /* AES XTS */ 44 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, 45 {.sym = { 46 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, 47 {.cipher = { 48 .algo = RTE_CRYPTO_CIPHER_AES_XTS, 49 .block_size = 16, 50 .key_size = { 51 .min = 32, 52 .max = 64, 53 .increment = 32 54 }, 55 .iv_size = { 56 .min = 16, 57 .max = 16, 58 .increment = 0 59 }, 60 .dataunit_set = 61 RTE_CRYPTO_CIPHER_DATA_UNIT_LEN_512_BYTES | 62 RTE_CRYPTO_CIPHER_DATA_UNIT_LEN_4096_BYTES, 63 }, } 64 }, } 65 }, 66 }; 67 68 static const char mlx5_crypto_drv_name[] = RTE_STR(MLX5_CRYPTO_DRIVER_NAME); 69 70 static const struct rte_driver mlx5_drv = { 71 .name = mlx5_crypto_drv_name, 72 .alias = mlx5_crypto_drv_name 73 }; 74 75 static struct cryptodev_driver mlx5_cryptodev_driver; 76 77 struct mlx5_crypto_session { 78 uint32_t bs_bpt_eo_es; 79 /**< bsf_size, bsf_p_type, encryption_order and encryption standard, 80 * saved in big endian format. 81 */ 82 uint32_t bsp_res; 83 /**< crypto_block_size_pointer and reserved 24 bits saved in big 84 * endian format. 85 */ 86 uint32_t iv_offset:16; 87 /**< Starting point for Initialisation Vector. */ 88 struct mlx5_crypto_dek *dek; /**< Pointer to dek struct. */ 89 uint32_t dek_id; /**< DEK ID */ 90 } __rte_packed; 91 92 static void 93 mlx5_crypto_dev_infos_get(struct rte_cryptodev *dev, 94 struct rte_cryptodev_info *dev_info) 95 { 96 RTE_SET_USED(dev); 97 if (dev_info != NULL) { 98 dev_info->driver_id = mlx5_crypto_driver_id; 99 dev_info->feature_flags = MLX5_CRYPTO_FEATURE_FLAGS; 100 dev_info->capabilities = mlx5_crypto_caps; 101 dev_info->max_nb_queue_pairs = MLX5_CRYPTO_MAX_QPS; 102 dev_info->min_mbuf_headroom_req = 0; 103 dev_info->min_mbuf_tailroom_req = 0; 104 dev_info->sym.max_nb_sessions = 0; 105 /* 106 * If 0, the device does not have any limitation in number of 107 * sessions that can be used. 108 */ 109 } 110 } 111 112 static int 113 mlx5_crypto_dev_configure(struct rte_cryptodev *dev, 114 struct rte_cryptodev_config *config) 115 { 116 struct mlx5_crypto_priv *priv = dev->data->dev_private; 117 118 if (config == NULL) { 119 DRV_LOG(ERR, "Invalid crypto dev configure parameters."); 120 return -EINVAL; 121 } 122 if ((config->ff_disable & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) != 0) { 123 DRV_LOG(ERR, 124 "Disabled symmetric crypto feature is not supported."); 125 return -ENOTSUP; 126 } 127 if (mlx5_crypto_dek_setup(priv) != 0) { 128 DRV_LOG(ERR, "Dek hash list creation has failed."); 129 return -ENOMEM; 130 } 131 priv->dev_config = *config; 132 DRV_LOG(DEBUG, "Device %u was configured.", dev->driver_id); 133 return 0; 134 } 135 136 static void 137 mlx5_crypto_dev_stop(struct rte_cryptodev *dev) 138 { 139 RTE_SET_USED(dev); 140 } 141 142 static int 143 mlx5_crypto_dev_start(struct rte_cryptodev *dev) 144 { 145 RTE_SET_USED(dev); 146 return 0; 147 } 148 149 static int 150 mlx5_crypto_dev_close(struct rte_cryptodev *dev) 151 { 152 struct mlx5_crypto_priv *priv = dev->data->dev_private; 153 154 mlx5_crypto_dek_unset(priv); 155 DRV_LOG(DEBUG, "Device %u was closed.", dev->driver_id); 156 return 0; 157 } 158 159 static unsigned int 160 mlx5_crypto_sym_session_get_size(struct rte_cryptodev *dev __rte_unused) 161 { 162 return sizeof(struct mlx5_crypto_session); 163 } 164 165 static int 166 mlx5_crypto_sym_session_configure(struct rte_cryptodev *dev, 167 struct rte_crypto_sym_xform *xform, 168 struct rte_cryptodev_sym_session *session, 169 struct rte_mempool *mp) 170 { 171 struct mlx5_crypto_priv *priv = dev->data->dev_private; 172 struct mlx5_crypto_session *sess_private_data; 173 struct rte_crypto_cipher_xform *cipher; 174 uint8_t encryption_order; 175 int ret; 176 177 if (unlikely(xform->next != NULL)) { 178 DRV_LOG(ERR, "Xform next is not supported."); 179 return -ENOTSUP; 180 } 181 if (unlikely((xform->type != RTE_CRYPTO_SYM_XFORM_CIPHER) || 182 (xform->cipher.algo != RTE_CRYPTO_CIPHER_AES_XTS))) { 183 DRV_LOG(ERR, "Only AES-XTS algorithm is supported."); 184 return -ENOTSUP; 185 } 186 ret = rte_mempool_get(mp, (void *)&sess_private_data); 187 if (ret != 0) { 188 DRV_LOG(ERR, 189 "Failed to get session %p private data from mempool.", 190 sess_private_data); 191 return -ENOMEM; 192 } 193 cipher = &xform->cipher; 194 sess_private_data->dek = mlx5_crypto_dek_prepare(priv, cipher); 195 if (sess_private_data->dek == NULL) { 196 rte_mempool_put(mp, sess_private_data); 197 DRV_LOG(ERR, "Failed to prepare dek."); 198 return -ENOMEM; 199 } 200 if (cipher->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) 201 encryption_order = MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY; 202 else 203 encryption_order = MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE; 204 sess_private_data->bs_bpt_eo_es = rte_cpu_to_be_32 205 (MLX5_BSF_SIZE_64B << MLX5_BSF_SIZE_OFFSET | 206 MLX5_BSF_P_TYPE_CRYPTO << MLX5_BSF_P_TYPE_OFFSET | 207 encryption_order << MLX5_ENCRYPTION_ORDER_OFFSET | 208 MLX5_ENCRYPTION_STANDARD_AES_XTS); 209 switch (xform->cipher.dataunit_len) { 210 case 0: 211 sess_private_data->bsp_res = 0; 212 break; 213 case 512: 214 sess_private_data->bsp_res = rte_cpu_to_be_32 215 ((uint32_t)MLX5_BLOCK_SIZE_512B << 216 MLX5_BLOCK_SIZE_OFFSET); 217 break; 218 case 4096: 219 sess_private_data->bsp_res = rte_cpu_to_be_32 220 ((uint32_t)MLX5_BLOCK_SIZE_4096B << 221 MLX5_BLOCK_SIZE_OFFSET); 222 break; 223 default: 224 DRV_LOG(ERR, "Cipher data unit length is not supported."); 225 return -ENOTSUP; 226 } 227 sess_private_data->iv_offset = cipher->iv.offset; 228 sess_private_data->dek_id = 229 rte_cpu_to_be_32(sess_private_data->dek->obj->id & 230 0xffffff); 231 set_sym_session_private_data(session, dev->driver_id, 232 sess_private_data); 233 DRV_LOG(DEBUG, "Session %p was configured.", sess_private_data); 234 return 0; 235 } 236 237 static void 238 mlx5_crypto_sym_session_clear(struct rte_cryptodev *dev, 239 struct rte_cryptodev_sym_session *sess) 240 { 241 struct mlx5_crypto_priv *priv = dev->data->dev_private; 242 struct mlx5_crypto_session *spriv = get_sym_session_private_data(sess, 243 dev->driver_id); 244 245 if (unlikely(spriv == NULL)) { 246 DRV_LOG(ERR, "Failed to get session %p private data.", spriv); 247 return; 248 } 249 mlx5_crypto_dek_destroy(priv, spriv->dek); 250 set_sym_session_private_data(sess, dev->driver_id, NULL); 251 rte_mempool_put(rte_mempool_from_obj(spriv), spriv); 252 DRV_LOG(DEBUG, "Session %p was cleared.", spriv); 253 } 254 255 static int 256 mlx5_crypto_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id) 257 { 258 struct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id]; 259 260 if (qp->qp_obj != NULL) 261 claim_zero(mlx5_devx_cmd_destroy(qp->qp_obj)); 262 if (qp->umem_obj != NULL) 263 claim_zero(mlx5_glue->devx_umem_dereg(qp->umem_obj)); 264 if (qp->umem_buf != NULL) 265 rte_free(qp->umem_buf); 266 mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh); 267 mlx5_devx_cq_destroy(&qp->cq_obj); 268 rte_free(qp); 269 dev->data->queue_pairs[qp_id] = NULL; 270 return 0; 271 } 272 273 static int 274 mlx5_crypto_qp2rts(struct mlx5_crypto_qp *qp) 275 { 276 /* 277 * In Order to configure self loopback, when calling these functions the 278 * remote QP id that is used is the id of the same QP. 279 */ 280 if (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_RST2INIT_QP, 281 qp->qp_obj->id)) { 282 DRV_LOG(ERR, "Failed to modify QP to INIT state(%u).", 283 rte_errno); 284 return -1; 285 } 286 if (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_INIT2RTR_QP, 287 qp->qp_obj->id)) { 288 DRV_LOG(ERR, "Failed to modify QP to RTR state(%u).", 289 rte_errno); 290 return -1; 291 } 292 if (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_RTR2RTS_QP, 293 qp->qp_obj->id)) { 294 DRV_LOG(ERR, "Failed to modify QP to RTS state(%u).", 295 rte_errno); 296 return -1; 297 } 298 return 0; 299 } 300 301 static __rte_noinline uint32_t 302 mlx5_crypto_get_block_size(struct rte_crypto_op *op) 303 { 304 uint32_t bl = op->sym->cipher.data.length; 305 306 switch (bl) { 307 case (1 << 20): 308 return RTE_BE32(MLX5_BLOCK_SIZE_1MB << MLX5_BLOCK_SIZE_OFFSET); 309 case (1 << 12): 310 return RTE_BE32(MLX5_BLOCK_SIZE_4096B << 311 MLX5_BLOCK_SIZE_OFFSET); 312 case (1 << 9): 313 return RTE_BE32(MLX5_BLOCK_SIZE_512B << MLX5_BLOCK_SIZE_OFFSET); 314 default: 315 DRV_LOG(ERR, "Unknown block size: %u.", bl); 316 return UINT32_MAX; 317 } 318 } 319 320 /** 321 * Query LKey from a packet buffer for QP. If not found, add the mempool. 322 * 323 * @param priv 324 * Pointer to the priv object. 325 * @param addr 326 * Search key. 327 * @param mr_ctrl 328 * Pointer to per-queue MR control structure. 329 * @param ol_flags 330 * Mbuf offload features. 331 * 332 * @return 333 * Searched LKey on success, UINT32_MAX on no match. 334 */ 335 static __rte_always_inline uint32_t 336 mlx5_crypto_addr2mr(struct mlx5_crypto_priv *priv, uintptr_t addr, 337 struct mlx5_mr_ctrl *mr_ctrl, uint64_t ol_flags) 338 { 339 uint32_t lkey; 340 341 /* Check generation bit to see if there's any change on existing MRs. */ 342 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen)) 343 mlx5_mr_flush_local_cache(mr_ctrl); 344 /* Linear search on MR cache array. */ 345 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, 346 MLX5_MR_CACHE_N, addr); 347 if (likely(lkey != UINT32_MAX)) 348 return lkey; 349 /* Take slower bottom-half on miss. */ 350 return mlx5_mr_addr2mr_bh(priv->pd, 0, &priv->mr_scache, mr_ctrl, addr, 351 !!(ol_flags & EXT_ATTACHED_MBUF)); 352 } 353 354 static __rte_always_inline uint32_t 355 mlx5_crypto_klm_set(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp, 356 struct rte_mbuf *mbuf, struct mlx5_wqe_dseg *klm, 357 uint32_t offset, uint32_t *remain) 358 { 359 uint32_t data_len = (rte_pktmbuf_data_len(mbuf) - offset); 360 uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset); 361 362 if (data_len > *remain) 363 data_len = *remain; 364 *remain -= data_len; 365 klm->bcount = rte_cpu_to_be_32(data_len); 366 klm->pbuf = rte_cpu_to_be_64(addr); 367 klm->lkey = mlx5_crypto_addr2mr(priv, addr, &qp->mr_ctrl, 368 mbuf->ol_flags); 369 return klm->lkey; 370 371 } 372 373 static __rte_always_inline uint32_t 374 mlx5_crypto_klms_set(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp, 375 struct rte_crypto_op *op, struct rte_mbuf *mbuf, 376 struct mlx5_wqe_dseg *klm) 377 { 378 uint32_t remain_len = op->sym->cipher.data.length; 379 uint32_t nb_segs = mbuf->nb_segs; 380 uint32_t klm_n = 1u; 381 382 /* First mbuf needs to take the cipher offset. */ 383 if (unlikely(mlx5_crypto_klm_set(priv, qp, mbuf, klm, 384 op->sym->cipher.data.offset, &remain_len) == UINT32_MAX)) { 385 op->status = RTE_CRYPTO_OP_STATUS_ERROR; 386 return 0; 387 } 388 while (remain_len) { 389 nb_segs--; 390 mbuf = mbuf->next; 391 if (unlikely(mbuf == NULL || nb_segs == 0)) { 392 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS; 393 return 0; 394 } 395 if (unlikely(mlx5_crypto_klm_set(priv, qp, mbuf, ++klm, 0, 396 &remain_len) == UINT32_MAX)) { 397 op->status = RTE_CRYPTO_OP_STATUS_ERROR; 398 return 0; 399 } 400 klm_n++; 401 } 402 return klm_n; 403 } 404 405 static __rte_always_inline int 406 mlx5_crypto_wqe_set(struct mlx5_crypto_priv *priv, 407 struct mlx5_crypto_qp *qp, 408 struct rte_crypto_op *op, 409 struct mlx5_umr_wqe *umr) 410 { 411 struct mlx5_crypto_session *sess = get_sym_session_private_data 412 (op->sym->session, mlx5_crypto_driver_id); 413 struct mlx5_wqe_cseg *cseg = &umr->ctr; 414 struct mlx5_wqe_mkey_cseg *mkc = &umr->mkc; 415 struct mlx5_wqe_dseg *klms = &umr->kseg[0]; 416 struct mlx5_wqe_umr_bsf_seg *bsf = ((struct mlx5_wqe_umr_bsf_seg *) 417 RTE_PTR_ADD(umr, priv->umr_wqe_size)) - 1; 418 uint32_t ds; 419 bool ipl = op->sym->m_dst == NULL || op->sym->m_dst == op->sym->m_src; 420 /* Set UMR WQE. */ 421 uint32_t klm_n = mlx5_crypto_klms_set(priv, qp, op, 422 ipl ? op->sym->m_src : op->sym->m_dst, klms); 423 424 if (unlikely(klm_n == 0)) 425 return 0; 426 bsf->bs_bpt_eo_es = sess->bs_bpt_eo_es; 427 if (unlikely(!sess->bsp_res)) { 428 bsf->bsp_res = mlx5_crypto_get_block_size(op); 429 if (unlikely(bsf->bsp_res == UINT32_MAX)) { 430 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS; 431 return 0; 432 } 433 } else { 434 bsf->bsp_res = sess->bsp_res; 435 } 436 bsf->raw_data_size = rte_cpu_to_be_32(op->sym->cipher.data.length); 437 memcpy(bsf->xts_initial_tweak, 438 rte_crypto_op_ctod_offset(op, uint8_t *, sess->iv_offset), 16); 439 bsf->res_dp = sess->dek_id; 440 mkc->len = rte_cpu_to_be_64(op->sym->cipher.data.length); 441 cseg->opcode = rte_cpu_to_be_32((qp->db_pi << 8) | MLX5_OPCODE_UMR); 442 qp->db_pi += priv->umr_wqe_stride; 443 /* Set RDMA_WRITE WQE. */ 444 cseg = RTE_PTR_ADD(cseg, priv->umr_wqe_size); 445 klms = RTE_PTR_ADD(cseg, sizeof(struct mlx5_rdma_write_wqe)); 446 if (!ipl) { 447 klm_n = mlx5_crypto_klms_set(priv, qp, op, op->sym->m_src, 448 klms); 449 if (unlikely(klm_n == 0)) 450 return 0; 451 } else { 452 memcpy(klms, &umr->kseg[0], sizeof(*klms) * klm_n); 453 } 454 ds = 2 + klm_n; 455 cseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj->id << 8) | ds); 456 cseg->opcode = rte_cpu_to_be_32((qp->db_pi << 8) | 457 MLX5_OPCODE_RDMA_WRITE); 458 ds = RTE_ALIGN(ds, 4); 459 qp->db_pi += ds >> 2; 460 /* Set NOP WQE if needed. */ 461 if (priv->max_rdmar_ds > ds) { 462 cseg += ds; 463 ds = priv->max_rdmar_ds - ds; 464 cseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj->id << 8) | ds); 465 cseg->opcode = rte_cpu_to_be_32((qp->db_pi << 8) | 466 MLX5_OPCODE_NOP); 467 qp->db_pi += ds >> 2; /* Here, DS is 4 aligned for sure. */ 468 } 469 qp->wqe = (uint8_t *)cseg; 470 return 1; 471 } 472 473 static __rte_always_inline void 474 mlx5_crypto_uar_write(uint64_t val, struct mlx5_crypto_priv *priv) 475 { 476 #ifdef RTE_ARCH_64 477 *priv->uar_addr = val; 478 #else /* !RTE_ARCH_64 */ 479 rte_spinlock_lock(&priv->uar32_sl); 480 *(volatile uint32_t *)priv->uar_addr = val; 481 rte_io_wmb(); 482 *((volatile uint32_t *)priv->uar_addr + 1) = val >> 32; 483 rte_spinlock_unlock(&priv->uar32_sl); 484 #endif 485 } 486 487 static uint16_t 488 mlx5_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops, 489 uint16_t nb_ops) 490 { 491 struct mlx5_crypto_qp *qp = queue_pair; 492 struct mlx5_crypto_priv *priv = qp->priv; 493 struct mlx5_umr_wqe *umr; 494 struct rte_crypto_op *op; 495 uint16_t mask = qp->entries_n - 1; 496 uint16_t remain = qp->entries_n - (qp->pi - qp->ci); 497 498 if (remain < nb_ops) 499 nb_ops = remain; 500 else 501 remain = nb_ops; 502 if (unlikely(remain == 0)) 503 return 0; 504 do { 505 op = *ops++; 506 umr = RTE_PTR_ADD(qp->umem_buf, priv->wqe_set_size * qp->pi); 507 if (unlikely(mlx5_crypto_wqe_set(priv, qp, op, umr) == 0)) { 508 qp->stats.enqueue_err_count++; 509 if (remain != nb_ops) { 510 qp->stats.enqueued_count -= remain; 511 break; 512 } 513 return 0; 514 } 515 qp->ops[qp->pi] = op; 516 qp->pi = (qp->pi + 1) & mask; 517 } while (--remain); 518 qp->stats.enqueued_count += nb_ops; 519 rte_io_wmb(); 520 qp->db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->db_pi); 521 rte_wmb(); 522 mlx5_crypto_uar_write(*(volatile uint64_t *)qp->wqe, qp->priv); 523 rte_wmb(); 524 return nb_ops; 525 } 526 527 static __rte_noinline void 528 mlx5_crypto_cqe_err_handle(struct mlx5_crypto_qp *qp, struct rte_crypto_op *op) 529 { 530 const uint32_t idx = qp->ci & (qp->entries_n - 1); 531 volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *) 532 &qp->cq_obj.cqes[idx]; 533 534 op->status = RTE_CRYPTO_OP_STATUS_ERROR; 535 qp->stats.dequeue_err_count++; 536 DRV_LOG(ERR, "CQE ERR:%x.\n", rte_be_to_cpu_32(cqe->syndrome)); 537 } 538 539 static uint16_t 540 mlx5_crypto_dequeue_burst(void *queue_pair, struct rte_crypto_op **ops, 541 uint16_t nb_ops) 542 { 543 struct mlx5_crypto_qp *qp = queue_pair; 544 volatile struct mlx5_cqe *restrict cqe; 545 struct rte_crypto_op *restrict op; 546 const unsigned int cq_size = qp->entries_n; 547 const unsigned int mask = cq_size - 1; 548 uint32_t idx; 549 uint32_t next_idx = qp->ci & mask; 550 const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops); 551 uint16_t i = 0; 552 int ret; 553 554 if (unlikely(max == 0)) 555 return 0; 556 do { 557 idx = next_idx; 558 next_idx = (qp->ci + 1) & mask; 559 op = qp->ops[idx]; 560 cqe = &qp->cq_obj.cqes[idx]; 561 ret = check_cqe(cqe, cq_size, qp->ci); 562 rte_io_rmb(); 563 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) { 564 if (unlikely(ret != MLX5_CQE_STATUS_HW_OWN)) 565 mlx5_crypto_cqe_err_handle(qp, op); 566 break; 567 } 568 op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; 569 ops[i++] = op; 570 qp->ci++; 571 } while (i < max); 572 if (likely(i != 0)) { 573 rte_io_wmb(); 574 qp->cq_obj.db_rec[0] = rte_cpu_to_be_32(qp->ci); 575 qp->stats.dequeued_count += i; 576 } 577 return i; 578 } 579 580 static void 581 mlx5_crypto_qp_init(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp) 582 { 583 uint32_t i; 584 585 for (i = 0 ; i < qp->entries_n; i++) { 586 struct mlx5_wqe_cseg *cseg = RTE_PTR_ADD(qp->umem_buf, i * 587 priv->wqe_set_size); 588 struct mlx5_wqe_umr_cseg *ucseg = (struct mlx5_wqe_umr_cseg *) 589 (cseg + 1); 590 struct mlx5_wqe_umr_bsf_seg *bsf = 591 (struct mlx5_wqe_umr_bsf_seg *)(RTE_PTR_ADD(cseg, 592 priv->umr_wqe_size)) - 1; 593 struct mlx5_wqe_rseg *rseg; 594 595 /* Init UMR WQE. */ 596 cseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj->id << 8) | 597 (priv->umr_wqe_size / MLX5_WSEG_SIZE)); 598 cseg->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR << 599 MLX5_COMP_MODE_OFFSET); 600 cseg->misc = rte_cpu_to_be_32(qp->mkey[i]->id); 601 ucseg->if_cf_toe_cq_res = RTE_BE32(1u << MLX5_UMRC_IF_OFFSET); 602 ucseg->mkey_mask = RTE_BE64(1u << 0); /* Mkey length bit. */ 603 ucseg->ko_to_bs = rte_cpu_to_be_32 604 ((RTE_ALIGN(priv->max_segs_num, 4u) << 605 MLX5_UMRC_KO_OFFSET) | (4 << MLX5_UMRC_TO_BS_OFFSET)); 606 bsf->keytag = priv->keytag; 607 /* Init RDMA WRITE WQE. */ 608 cseg = RTE_PTR_ADD(cseg, priv->umr_wqe_size); 609 cseg->flags = RTE_BE32((MLX5_COMP_ALWAYS << 610 MLX5_COMP_MODE_OFFSET) | 611 MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE); 612 rseg = (struct mlx5_wqe_rseg *)(cseg + 1); 613 rseg->rkey = rte_cpu_to_be_32(qp->mkey[i]->id); 614 } 615 } 616 617 static int 618 mlx5_crypto_indirect_mkeys_prepare(struct mlx5_crypto_priv *priv, 619 struct mlx5_crypto_qp *qp) 620 { 621 struct mlx5_umr_wqe *umr; 622 uint32_t i; 623 struct mlx5_devx_mkey_attr attr = { 624 .pd = priv->pdn, 625 .umr_en = 1, 626 .crypto_en = 1, 627 .set_remote_rw = 1, 628 .klm_num = RTE_ALIGN(priv->max_segs_num, 4), 629 }; 630 631 for (umr = (struct mlx5_umr_wqe *)qp->umem_buf, i = 0; 632 i < qp->entries_n; i++, umr = RTE_PTR_ADD(umr, priv->wqe_set_size)) { 633 attr.klm_array = (struct mlx5_klm *)&umr->kseg[0]; 634 qp->mkey[i] = mlx5_devx_cmd_mkey_create(priv->ctx, &attr); 635 if (!qp->mkey[i]) { 636 DRV_LOG(ERR, "Failed to allocate indirect mkey."); 637 return -1; 638 } 639 } 640 return 0; 641 } 642 643 static int 644 mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, 645 const struct rte_cryptodev_qp_conf *qp_conf, 646 int socket_id) 647 { 648 struct mlx5_crypto_priv *priv = dev->data->dev_private; 649 struct mlx5_devx_qp_attr attr = {0}; 650 struct mlx5_crypto_qp *qp; 651 uint16_t log_nb_desc = rte_log2_u32(qp_conf->nb_descriptors); 652 uint32_t umem_size = RTE_BIT32(log_nb_desc) * 653 priv->wqe_set_size + 654 sizeof(*qp->db_rec) * 2; 655 uint32_t alloc_size = sizeof(*qp); 656 struct mlx5_devx_cq_attr cq_attr = { 657 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar), 658 }; 659 660 if (dev->data->queue_pairs[qp_id] != NULL) 661 mlx5_crypto_queue_pair_release(dev, qp_id); 662 alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE); 663 alloc_size += (sizeof(struct rte_crypto_op *) + 664 sizeof(struct mlx5_devx_obj *)) * 665 RTE_BIT32(log_nb_desc); 666 qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE, 667 socket_id); 668 if (qp == NULL) { 669 DRV_LOG(ERR, "Failed to allocate QP memory."); 670 rte_errno = ENOMEM; 671 return -rte_errno; 672 } 673 if (mlx5_devx_cq_create(priv->ctx, &qp->cq_obj, log_nb_desc, 674 &cq_attr, socket_id) != 0) { 675 DRV_LOG(ERR, "Failed to create CQ."); 676 goto error; 677 } 678 qp->umem_buf = rte_zmalloc_socket(__func__, umem_size, 4096, socket_id); 679 if (qp->umem_buf == NULL) { 680 DRV_LOG(ERR, "Failed to allocate QP umem."); 681 rte_errno = ENOMEM; 682 goto error; 683 } 684 qp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx, 685 (void *)(uintptr_t)qp->umem_buf, 686 umem_size, 687 IBV_ACCESS_LOCAL_WRITE); 688 if (qp->umem_obj == NULL) { 689 DRV_LOG(ERR, "Failed to register QP umem."); 690 goto error; 691 } 692 if (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N, 693 priv->dev_config.socket_id) != 0) { 694 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.", 695 (uint32_t)qp_id); 696 rte_errno = ENOMEM; 697 goto error; 698 } 699 qp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen; 700 attr.pd = priv->pdn; 701 attr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar); 702 attr.cqn = qp->cq_obj.cq->id; 703 attr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE)); 704 attr.rq_size = 0; 705 attr.sq_size = RTE_BIT32(log_nb_desc); 706 attr.dbr_umem_valid = 1; 707 attr.wq_umem_id = qp->umem_obj->umem_id; 708 attr.wq_umem_offset = 0; 709 attr.dbr_umem_id = qp->umem_obj->umem_id; 710 attr.ts_format = mlx5_ts_format_conv(priv->qp_ts_format); 711 attr.dbr_address = RTE_BIT64(log_nb_desc) * priv->wqe_set_size; 712 qp->qp_obj = mlx5_devx_cmd_create_qp(priv->ctx, &attr); 713 if (qp->qp_obj == NULL) { 714 DRV_LOG(ERR, "Failed to create QP(%u).", rte_errno); 715 goto error; 716 } 717 qp->db_rec = RTE_PTR_ADD(qp->umem_buf, (uintptr_t)attr.dbr_address); 718 if (mlx5_crypto_qp2rts(qp)) 719 goto error; 720 qp->mkey = (struct mlx5_devx_obj **)RTE_ALIGN((uintptr_t)(qp + 1), 721 RTE_CACHE_LINE_SIZE); 722 qp->ops = (struct rte_crypto_op **)(qp->mkey + RTE_BIT32(log_nb_desc)); 723 qp->entries_n = 1 << log_nb_desc; 724 if (mlx5_crypto_indirect_mkeys_prepare(priv, qp)) { 725 DRV_LOG(ERR, "Cannot allocate indirect memory regions."); 726 rte_errno = ENOMEM; 727 goto error; 728 } 729 mlx5_crypto_qp_init(priv, qp); 730 qp->priv = priv; 731 dev->data->queue_pairs[qp_id] = qp; 732 return 0; 733 error: 734 mlx5_crypto_queue_pair_release(dev, qp_id); 735 return -1; 736 } 737 738 static void 739 mlx5_crypto_stats_get(struct rte_cryptodev *dev, 740 struct rte_cryptodev_stats *stats) 741 { 742 int qp_id; 743 744 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) { 745 struct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id]; 746 747 stats->enqueued_count += qp->stats.enqueued_count; 748 stats->dequeued_count += qp->stats.dequeued_count; 749 stats->enqueue_err_count += qp->stats.enqueue_err_count; 750 stats->dequeue_err_count += qp->stats.dequeue_err_count; 751 } 752 } 753 754 static void 755 mlx5_crypto_stats_reset(struct rte_cryptodev *dev) 756 { 757 int qp_id; 758 759 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) { 760 struct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id]; 761 762 memset(&qp->stats, 0, sizeof(qp->stats)); 763 } 764 } 765 766 static struct rte_cryptodev_ops mlx5_crypto_ops = { 767 .dev_configure = mlx5_crypto_dev_configure, 768 .dev_start = mlx5_crypto_dev_start, 769 .dev_stop = mlx5_crypto_dev_stop, 770 .dev_close = mlx5_crypto_dev_close, 771 .dev_infos_get = mlx5_crypto_dev_infos_get, 772 .stats_get = mlx5_crypto_stats_get, 773 .stats_reset = mlx5_crypto_stats_reset, 774 .queue_pair_setup = mlx5_crypto_queue_pair_setup, 775 .queue_pair_release = mlx5_crypto_queue_pair_release, 776 .sym_session_get_size = mlx5_crypto_sym_session_get_size, 777 .sym_session_configure = mlx5_crypto_sym_session_configure, 778 .sym_session_clear = mlx5_crypto_sym_session_clear, 779 .sym_get_raw_dp_ctx_size = NULL, 780 .sym_configure_raw_dp_ctx = NULL, 781 }; 782 783 static void 784 mlx5_crypto_hw_global_release(struct mlx5_crypto_priv *priv) 785 { 786 if (priv->pd != NULL) { 787 claim_zero(mlx5_glue->dealloc_pd(priv->pd)); 788 priv->pd = NULL; 789 } 790 if (priv->uar != NULL) { 791 mlx5_glue->devx_free_uar(priv->uar); 792 priv->uar = NULL; 793 } 794 } 795 796 static int 797 mlx5_crypto_pd_create(struct mlx5_crypto_priv *priv) 798 { 799 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 800 struct mlx5dv_obj obj; 801 struct mlx5dv_pd pd_info; 802 int ret; 803 804 priv->pd = mlx5_glue->alloc_pd(priv->ctx); 805 if (priv->pd == NULL) { 806 DRV_LOG(ERR, "Failed to allocate PD."); 807 return errno ? -errno : -ENOMEM; 808 } 809 obj.pd.in = priv->pd; 810 obj.pd.out = &pd_info; 811 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 812 if (ret != 0) { 813 DRV_LOG(ERR, "Fail to get PD object info."); 814 mlx5_glue->dealloc_pd(priv->pd); 815 priv->pd = NULL; 816 return -errno; 817 } 818 priv->pdn = pd_info.pdn; 819 return 0; 820 #else 821 (void)priv; 822 DRV_LOG(ERR, "Cannot get pdn - no DV support."); 823 return -ENOTSUP; 824 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 825 } 826 827 static int 828 mlx5_crypto_hw_global_prepare(struct mlx5_crypto_priv *priv) 829 { 830 if (mlx5_crypto_pd_create(priv) != 0) 831 return -1; 832 priv->uar = mlx5_devx_alloc_uar(priv->ctx, -1); 833 if (priv->uar) 834 priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar); 835 if (priv->uar == NULL || priv->uar_addr == NULL) { 836 rte_errno = errno; 837 claim_zero(mlx5_glue->dealloc_pd(priv->pd)); 838 DRV_LOG(ERR, "Failed to allocate UAR."); 839 return -1; 840 } 841 return 0; 842 } 843 844 845 static int 846 mlx5_crypto_args_check_handler(const char *key, const char *val, void *opaque) 847 { 848 struct mlx5_crypto_devarg_params *devarg_prms = opaque; 849 struct mlx5_devx_crypto_login_attr *attr = &devarg_prms->login_attr; 850 unsigned long tmp; 851 FILE *file; 852 int ret; 853 int i; 854 855 if (strcmp(key, "class") == 0) 856 return 0; 857 if (strcmp(key, "wcs_file") == 0) { 858 file = fopen(val, "rb"); 859 if (file == NULL) { 860 rte_errno = ENOTSUP; 861 return -rte_errno; 862 } 863 for (i = 0 ; i < MLX5_CRYPTO_CREDENTIAL_SIZE ; i++) { 864 ret = fscanf(file, "%02hhX", &attr->credential[i]); 865 if (ret <= 0) { 866 fclose(file); 867 DRV_LOG(ERR, 868 "Failed to read credential from file."); 869 rte_errno = EINVAL; 870 return -rte_errno; 871 } 872 } 873 fclose(file); 874 devarg_prms->login_devarg = true; 875 return 0; 876 } 877 errno = 0; 878 tmp = strtoul(val, NULL, 0); 879 if (errno) { 880 DRV_LOG(WARNING, "%s: \"%s\" is an invalid integer.", key, val); 881 return -errno; 882 } 883 if (strcmp(key, "max_segs_num") == 0) { 884 if (!tmp || tmp > MLX5_CRYPTO_MAX_SEGS) { 885 DRV_LOG(WARNING, "Invalid max_segs_num: %d, should" 886 " be less than %d.", 887 (uint32_t)tmp, MLX5_CRYPTO_MAX_SEGS); 888 rte_errno = EINVAL; 889 return -rte_errno; 890 } 891 devarg_prms->max_segs_num = (uint32_t)tmp; 892 } else if (strcmp(key, "import_kek_id") == 0) { 893 attr->session_import_kek_ptr = (uint32_t)tmp; 894 } else if (strcmp(key, "credential_id") == 0) { 895 attr->credential_pointer = (uint32_t)tmp; 896 } else if (strcmp(key, "keytag") == 0) { 897 devarg_prms->keytag = tmp; 898 } else { 899 DRV_LOG(WARNING, "Invalid key %s.", key); 900 } 901 return 0; 902 } 903 904 static int 905 mlx5_crypto_parse_devargs(struct rte_devargs *devargs, 906 struct mlx5_crypto_devarg_params *devarg_prms) 907 { 908 struct mlx5_devx_crypto_login_attr *attr = &devarg_prms->login_attr; 909 struct rte_kvargs *kvlist; 910 911 /* Default values. */ 912 attr->credential_pointer = 0; 913 attr->session_import_kek_ptr = 0; 914 devarg_prms->keytag = 0; 915 devarg_prms->max_segs_num = 8; 916 if (devargs == NULL) { 917 DRV_LOG(ERR, 918 "No login devargs in order to enable crypto operations in the device."); 919 rte_errno = EINVAL; 920 return -1; 921 } 922 kvlist = rte_kvargs_parse(devargs->args, NULL); 923 if (kvlist == NULL) { 924 DRV_LOG(ERR, "Failed to parse devargs."); 925 rte_errno = EINVAL; 926 return -1; 927 } 928 if (rte_kvargs_process(kvlist, NULL, mlx5_crypto_args_check_handler, 929 devarg_prms) != 0) { 930 DRV_LOG(ERR, "Devargs handler function Failed."); 931 rte_kvargs_free(kvlist); 932 rte_errno = EINVAL; 933 return -1; 934 } 935 rte_kvargs_free(kvlist); 936 if (devarg_prms->login_devarg == false) { 937 DRV_LOG(ERR, 938 "No login credential devarg in order to enable crypto operations " 939 "in the device."); 940 rte_errno = EINVAL; 941 return -1; 942 } 943 return 0; 944 } 945 946 /** 947 * Callback for memory event. 948 * 949 * @param event_type 950 * Memory event type. 951 * @param addr 952 * Address of memory. 953 * @param len 954 * Size of memory. 955 */ 956 static void 957 mlx5_crypto_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr, 958 size_t len, void *arg __rte_unused) 959 { 960 struct mlx5_crypto_priv *priv; 961 962 /* Must be called from the primary process. */ 963 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 964 switch (event_type) { 965 case RTE_MEM_EVENT_FREE: 966 pthread_mutex_lock(&priv_list_lock); 967 /* Iterate all the existing mlx5 devices. */ 968 TAILQ_FOREACH(priv, &mlx5_crypto_priv_list, next) 969 mlx5_free_mr_by_addr(&priv->mr_scache, 970 priv->ctx->device->name, 971 addr, len); 972 pthread_mutex_unlock(&priv_list_lock); 973 break; 974 case RTE_MEM_EVENT_ALLOC: 975 default: 976 break; 977 } 978 } 979 980 static int 981 mlx5_crypto_dev_probe(struct rte_device *dev) 982 { 983 struct ibv_device *ibv; 984 struct rte_cryptodev *crypto_dev; 985 struct ibv_context *ctx; 986 struct mlx5_devx_obj *login; 987 struct mlx5_crypto_priv *priv; 988 struct mlx5_crypto_devarg_params devarg_prms = { 0 }; 989 struct mlx5_hca_attr attr = { 0 }; 990 struct rte_cryptodev_pmd_init_params init_params = { 991 .name = "", 992 .private_data_size = sizeof(struct mlx5_crypto_priv), 993 .socket_id = dev->numa_node, 994 .max_nb_queue_pairs = 995 RTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS, 996 }; 997 uint16_t rdmw_wqe_size; 998 int ret; 999 1000 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1001 DRV_LOG(ERR, "Non-primary process type is not supported."); 1002 rte_errno = ENOTSUP; 1003 return -rte_errno; 1004 } 1005 ibv = mlx5_os_get_ibv_dev(dev); 1006 if (ibv == NULL) 1007 return -rte_errno; 1008 ctx = mlx5_glue->dv_open_device(ibv); 1009 if (ctx == NULL) { 1010 DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name); 1011 rte_errno = ENODEV; 1012 return -rte_errno; 1013 } 1014 if (mlx5_devx_cmd_query_hca_attr(ctx, &attr) != 0 || 1015 attr.crypto == 0 || attr.aes_xts == 0) { 1016 DRV_LOG(ERR, "Not enough capabilities to support crypto " 1017 "operations, maybe old FW/OFED version?"); 1018 claim_zero(mlx5_glue->close_device(ctx)); 1019 rte_errno = ENOTSUP; 1020 return -ENOTSUP; 1021 } 1022 ret = mlx5_crypto_parse_devargs(dev->devargs, &devarg_prms); 1023 if (ret) { 1024 DRV_LOG(ERR, "Failed to parse devargs."); 1025 claim_zero(mlx5_glue->close_device(ctx)); 1026 return -rte_errno; 1027 } 1028 login = mlx5_devx_cmd_create_crypto_login_obj(ctx, 1029 &devarg_prms.login_attr); 1030 if (login == NULL) { 1031 DRV_LOG(ERR, "Failed to configure login."); 1032 claim_zero(mlx5_glue->close_device(ctx)); 1033 return -rte_errno; 1034 } 1035 crypto_dev = rte_cryptodev_pmd_create(ibv->name, dev, 1036 &init_params); 1037 if (crypto_dev == NULL) { 1038 DRV_LOG(ERR, "Failed to create device \"%s\".", ibv->name); 1039 claim_zero(mlx5_glue->close_device(ctx)); 1040 return -ENODEV; 1041 } 1042 DRV_LOG(INFO, 1043 "Crypto device %s was created successfully.", ibv->name); 1044 crypto_dev->dev_ops = &mlx5_crypto_ops; 1045 crypto_dev->dequeue_burst = mlx5_crypto_dequeue_burst; 1046 crypto_dev->enqueue_burst = mlx5_crypto_enqueue_burst; 1047 crypto_dev->feature_flags = MLX5_CRYPTO_FEATURE_FLAGS; 1048 crypto_dev->driver_id = mlx5_crypto_driver_id; 1049 priv = crypto_dev->data->dev_private; 1050 priv->ctx = ctx; 1051 priv->login_obj = login; 1052 priv->crypto_dev = crypto_dev; 1053 priv->qp_ts_format = attr.qp_ts_format; 1054 if (mlx5_crypto_hw_global_prepare(priv) != 0) { 1055 rte_cryptodev_pmd_destroy(priv->crypto_dev); 1056 claim_zero(mlx5_glue->close_device(priv->ctx)); 1057 return -1; 1058 } 1059 if (mlx5_mr_btree_init(&priv->mr_scache.cache, 1060 MLX5_MR_BTREE_CACHE_N * 2, rte_socket_id()) != 0) { 1061 DRV_LOG(ERR, "Failed to allocate shared cache MR memory."); 1062 mlx5_crypto_hw_global_release(priv); 1063 rte_cryptodev_pmd_destroy(priv->crypto_dev); 1064 claim_zero(mlx5_glue->close_device(priv->ctx)); 1065 rte_errno = ENOMEM; 1066 return -rte_errno; 1067 } 1068 priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr; 1069 priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr; 1070 priv->keytag = rte_cpu_to_be_64(devarg_prms.keytag); 1071 priv->max_segs_num = devarg_prms.max_segs_num; 1072 priv->umr_wqe_size = sizeof(struct mlx5_wqe_umr_bsf_seg) + 1073 sizeof(struct mlx5_umr_wqe) + 1074 RTE_ALIGN(priv->max_segs_num, 4) * 1075 sizeof(struct mlx5_wqe_dseg); 1076 rdmw_wqe_size = sizeof(struct mlx5_rdma_write_wqe) + 1077 sizeof(struct mlx5_wqe_dseg) * 1078 (priv->max_segs_num <= 2 ? 2 : 2 + 1079 RTE_ALIGN(priv->max_segs_num - 2, 4)); 1080 priv->wqe_set_size = priv->umr_wqe_size + rdmw_wqe_size; 1081 priv->umr_wqe_stride = priv->umr_wqe_size / MLX5_SEND_WQE_BB; 1082 priv->max_rdmar_ds = rdmw_wqe_size / sizeof(struct mlx5_wqe_dseg); 1083 /* Register callback function for global shared MR cache management. */ 1084 if (TAILQ_EMPTY(&mlx5_crypto_priv_list)) 1085 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 1086 mlx5_crypto_mr_mem_event_cb, 1087 NULL); 1088 pthread_mutex_lock(&priv_list_lock); 1089 TAILQ_INSERT_TAIL(&mlx5_crypto_priv_list, priv, next); 1090 pthread_mutex_unlock(&priv_list_lock); 1091 return 0; 1092 } 1093 1094 static int 1095 mlx5_crypto_dev_remove(struct rte_device *dev) 1096 { 1097 struct mlx5_crypto_priv *priv = NULL; 1098 1099 pthread_mutex_lock(&priv_list_lock); 1100 TAILQ_FOREACH(priv, &mlx5_crypto_priv_list, next) 1101 if (priv->crypto_dev->device == dev) 1102 break; 1103 if (priv) 1104 TAILQ_REMOVE(&mlx5_crypto_priv_list, priv, next); 1105 pthread_mutex_unlock(&priv_list_lock); 1106 if (priv) { 1107 if (TAILQ_EMPTY(&mlx5_crypto_priv_list)) 1108 rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB", 1109 NULL); 1110 mlx5_mr_release_cache(&priv->mr_scache); 1111 mlx5_crypto_hw_global_release(priv); 1112 rte_cryptodev_pmd_destroy(priv->crypto_dev); 1113 claim_zero(mlx5_devx_cmd_destroy(priv->login_obj)); 1114 claim_zero(mlx5_glue->close_device(priv->ctx)); 1115 } 1116 return 0; 1117 } 1118 1119 static const struct rte_pci_id mlx5_crypto_pci_id_map[] = { 1120 { 1121 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1122 PCI_DEVICE_ID_MELLANOX_CONNECTX6) 1123 }, 1124 { 1125 .vendor_id = 0 1126 } 1127 }; 1128 1129 static struct mlx5_class_driver mlx5_crypto_driver = { 1130 .drv_class = MLX5_CLASS_CRYPTO, 1131 .name = RTE_STR(MLX5_CRYPTO_DRIVER_NAME), 1132 .id_table = mlx5_crypto_pci_id_map, 1133 .probe = mlx5_crypto_dev_probe, 1134 .remove = mlx5_crypto_dev_remove, 1135 }; 1136 1137 RTE_INIT(rte_mlx5_crypto_init) 1138 { 1139 mlx5_common_init(); 1140 if (mlx5_glue != NULL) 1141 mlx5_class_driver_register(&mlx5_crypto_driver); 1142 } 1143 1144 RTE_PMD_REGISTER_CRYPTO_DRIVER(mlx5_cryptodev_driver, mlx5_drv, 1145 mlx5_crypto_driver_id); 1146 1147 RTE_LOG_REGISTER_DEFAULT(mlx5_crypto_logtype, NOTICE) 1148 RTE_PMD_EXPORT_NAME(MLX5_CRYPTO_DRIVER_NAME, __COUNTER__); 1149 RTE_PMD_REGISTER_PCI_TABLE(MLX5_CRYPTO_DRIVER_NAME, mlx5_crypto_pci_id_map); 1150 RTE_PMD_REGISTER_KMOD_DEP(MLX5_CRYPTO_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib"); 1151