1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /** 17 * Perform read access to the registers. Reads data from register 18 * and writes ones to the specified buffer. 19 * 20 * @param[in] ctx 21 * Context returned from mlx5 open_device() glue function. 22 * @param[in] reg_id 23 * Register identifier according to the PRM. 24 * @param[in] arg 25 * Register access auxiliary parameter according to the PRM. 26 * @param[out] data 27 * Pointer to the buffer to store read data. 28 * @param[in] dw_cnt 29 * Buffer size in double words. 30 * 31 * @return 32 * 0 on success, a negative value otherwise. 33 */ 34 int 35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 36 uint32_t *data, uint32_t dw_cnt) 37 { 38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 41 int status, rc; 42 43 MLX5_ASSERT(data && dw_cnt); 44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 46 DRV_LOG(ERR, "Not enough buffer for register read data"); 47 return -1; 48 } 49 MLX5_SET(access_register_in, in, opcode, 50 MLX5_CMD_OP_ACCESS_REGISTER_USER); 51 MLX5_SET(access_register_in, in, op_mod, 52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 53 MLX5_SET(access_register_in, in, register_id, reg_id); 54 MLX5_SET(access_register_in, in, argument, arg); 55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 56 MLX5_ST_SZ_BYTES(access_register_out) + 57 sizeof(uint32_t) * dw_cnt); 58 if (rc) 59 goto error; 60 status = MLX5_GET(access_register_out, out, status); 61 if (status) { 62 int syndrome = MLX5_GET(access_register_out, out, syndrome); 63 64 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, " 65 "status %x, syndrome = %x", 66 reg_id, status, syndrome); 67 return -1; 68 } 69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 70 dw_cnt * sizeof(uint32_t)); 71 return 0; 72 error: 73 rc = (rc > 0) ? -rc : rc; 74 return rc; 75 } 76 77 /** 78 * Perform write access to the registers. 79 * 80 * @param[in] ctx 81 * Context returned from mlx5 open_device() glue function. 82 * @param[in] reg_id 83 * Register identifier according to the PRM. 84 * @param[in] arg 85 * Register access auxiliary parameter according to the PRM. 86 * @param[out] data 87 * Pointer to the buffer containing data to write. 88 * @param[in] dw_cnt 89 * Buffer size in double words (32bit units). 90 * 91 * @return 92 * 0 on success, a negative value otherwise. 93 */ 94 int 95 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 96 uint32_t *data, uint32_t dw_cnt) 97 { 98 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 99 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 100 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 101 int status, rc; 102 void *ptr; 103 104 MLX5_ASSERT(data && dw_cnt); 105 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 106 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 107 DRV_LOG(ERR, "Data to write exceeds max size"); 108 return -1; 109 } 110 MLX5_SET(access_register_in, in, opcode, 111 MLX5_CMD_OP_ACCESS_REGISTER_USER); 112 MLX5_SET(access_register_in, in, op_mod, 113 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 114 MLX5_SET(access_register_in, in, register_id, reg_id); 115 MLX5_SET(access_register_in, in, argument, arg); 116 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 117 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 118 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 119 120 rc = mlx5_glue->devx_general_cmd(ctx, in, 121 MLX5_ST_SZ_BYTES(access_register_in) + 122 dw_cnt * sizeof(uint32_t), 123 out, sizeof(out)); 124 if (rc) 125 goto error; 126 status = MLX5_GET(access_register_out, out, status); 127 if (status) { 128 int syndrome = MLX5_GET(access_register_out, out, syndrome); 129 130 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, " 131 "status %x, syndrome = %x", 132 reg_id, status, syndrome); 133 return -1; 134 } 135 return 0; 136 error: 137 rc = (rc > 0) ? -rc : rc; 138 return rc; 139 } 140 141 /** 142 * Allocate flow counters via devx interface. 143 * 144 * @param[in] ctx 145 * Context returned from mlx5 open_device() glue function. 146 * @param dcs 147 * Pointer to counters properties structure to be filled by the routine. 148 * @param bulk_n_128 149 * Bulk counter numbers in 128 counters units. 150 * 151 * @return 152 * Pointer to counter object on success, a negative value otherwise and 153 * rte_errno is set. 154 */ 155 struct mlx5_devx_obj * 156 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 157 { 158 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 159 0, SOCKET_ID_ANY); 160 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 161 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 162 163 if (!dcs) { 164 rte_errno = ENOMEM; 165 return NULL; 166 } 167 MLX5_SET(alloc_flow_counter_in, in, opcode, 168 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 169 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 170 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 171 sizeof(in), out, sizeof(out)); 172 if (!dcs->obj) { 173 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 174 rte_errno = errno; 175 mlx5_free(dcs); 176 return NULL; 177 } 178 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 179 return dcs; 180 } 181 182 /** 183 * Query flow counters values. 184 * 185 * @param[in] dcs 186 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 187 * @param[in] clear 188 * Whether hardware should clear the counters after the query or not. 189 * @param[in] n_counters 190 * 0 in case of 1 counter to read, otherwise the counter number to read. 191 * @param pkts 192 * The number of packets that matched the flow. 193 * @param bytes 194 * The number of bytes that matched the flow. 195 * @param mkey 196 * The mkey key for batch query. 197 * @param addr 198 * The address in the mkey range for batch query. 199 * @param cmd_comp 200 * The completion object for asynchronous batch query. 201 * @param async_id 202 * The ID to be returned in the asynchronous batch query response. 203 * 204 * @return 205 * 0 on success, a negative value otherwise. 206 */ 207 int 208 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 209 int clear, uint32_t n_counters, 210 uint64_t *pkts, uint64_t *bytes, 211 uint32_t mkey, void *addr, 212 void *cmd_comp, 213 uint64_t async_id) 214 { 215 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 216 MLX5_ST_SZ_BYTES(traffic_counter); 217 uint32_t out[out_len]; 218 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 219 void *stats; 220 int rc; 221 222 MLX5_SET(query_flow_counter_in, in, opcode, 223 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 224 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 225 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 226 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 227 228 if (n_counters) { 229 MLX5_SET(query_flow_counter_in, in, num_of_counters, 230 n_counters); 231 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 232 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 233 MLX5_SET64(query_flow_counter_in, in, address, 234 (uint64_t)(uintptr_t)addr); 235 } 236 if (!cmd_comp) 237 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 238 out_len); 239 else 240 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 241 out_len, async_id, 242 cmd_comp); 243 if (rc) { 244 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 245 rte_errno = rc; 246 return -rc; 247 } 248 if (!n_counters) { 249 stats = MLX5_ADDR_OF(query_flow_counter_out, 250 out, flow_statistics); 251 *pkts = MLX5_GET64(traffic_counter, stats, packets); 252 *bytes = MLX5_GET64(traffic_counter, stats, octets); 253 } 254 return 0; 255 } 256 257 /** 258 * Create a new mkey. 259 * 260 * @param[in] ctx 261 * Context returned from mlx5 open_device() glue function. 262 * @param[in] attr 263 * Attributes of the requested mkey. 264 * 265 * @return 266 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 267 * is set. 268 */ 269 struct mlx5_devx_obj * 270 mlx5_devx_cmd_mkey_create(void *ctx, 271 struct mlx5_devx_mkey_attr *attr) 272 { 273 struct mlx5_klm *klm_array = attr->klm_array; 274 int klm_num = attr->klm_num; 275 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 276 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 277 uint32_t in[in_size_dw]; 278 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 279 void *mkc; 280 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 281 0, SOCKET_ID_ANY); 282 size_t pgsize; 283 uint32_t translation_size; 284 285 if (!mkey) { 286 rte_errno = ENOMEM; 287 return NULL; 288 } 289 memset(in, 0, in_size_dw * 4); 290 pgsize = rte_mem_page_size(); 291 if (pgsize == (size_t)-1) { 292 mlx5_free(mkey); 293 DRV_LOG(ERR, "Failed to get page size"); 294 rte_errno = ENOMEM; 295 return NULL; 296 } 297 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 298 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 299 if (klm_num > 0) { 300 int i; 301 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 302 klm_pas_mtt); 303 translation_size = RTE_ALIGN(klm_num, 4); 304 for (i = 0; i < klm_num; i++) { 305 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 306 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 307 MLX5_SET64(klm, klm, address, klm_array[i].address); 308 klm += MLX5_ST_SZ_BYTES(klm); 309 } 310 for (; i < (int)translation_size; i++) { 311 MLX5_SET(klm, klm, mkey, 0x0); 312 MLX5_SET64(klm, klm, address, 0x0); 313 klm += MLX5_ST_SZ_BYTES(klm); 314 } 315 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 316 MLX5_MKC_ACCESS_MODE_KLM_FBS : 317 MLX5_MKC_ACCESS_MODE_KLM); 318 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 319 } else { 320 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 321 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 322 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 323 } 324 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 325 translation_size); 326 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 327 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 328 MLX5_SET(mkc, mkc, lw, 0x1); 329 MLX5_SET(mkc, mkc, lr, 0x1); 330 if (attr->set_remote_rw) { 331 MLX5_SET(mkc, mkc, rw, 0x1); 332 MLX5_SET(mkc, mkc, rr, 0x1); 333 } 334 MLX5_SET(mkc, mkc, qpn, 0xffffff); 335 MLX5_SET(mkc, mkc, pd, attr->pd); 336 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 337 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 338 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 339 MLX5_SET(mkc, mkc, relaxed_ordering_write, 340 attr->relaxed_ordering_write); 341 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 342 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 343 MLX5_SET64(mkc, mkc, len, attr->size); 344 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 345 if (attr->crypto_en) { 346 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 347 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 348 } 349 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 350 sizeof(out)); 351 if (!mkey->obj) { 352 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d", 353 klm_num ? "an in" : "a ", errno); 354 rte_errno = errno; 355 mlx5_free(mkey); 356 return NULL; 357 } 358 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 359 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 360 return mkey; 361 } 362 363 /** 364 * Get status of devx command response. 365 * Mainly used for asynchronous commands. 366 * 367 * @param[in] out 368 * The out response buffer. 369 * 370 * @return 371 * 0 on success, non-zero value otherwise. 372 */ 373 int 374 mlx5_devx_get_out_command_status(void *out) 375 { 376 int status; 377 378 if (!out) 379 return -EINVAL; 380 status = MLX5_GET(query_flow_counter_out, out, status); 381 if (status) { 382 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 383 384 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 385 syndrome); 386 } 387 return status; 388 } 389 390 /** 391 * Destroy any object allocated by a Devx API. 392 * 393 * @param[in] obj 394 * Pointer to a general object. 395 * 396 * @return 397 * 0 on success, a negative value otherwise. 398 */ 399 int 400 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 401 { 402 int ret; 403 404 if (!obj) 405 return 0; 406 ret = mlx5_glue->devx_obj_destroy(obj->obj); 407 mlx5_free(obj); 408 return ret; 409 } 410 411 /** 412 * Query NIC vport context. 413 * Fills minimal inline attribute. 414 * 415 * @param[in] ctx 416 * ibv contexts returned from mlx5dv_open_device. 417 * @param[in] vport 418 * vport index 419 * @param[out] attr 420 * Attributes device values. 421 * 422 * @return 423 * 0 on success, a negative value otherwise. 424 */ 425 static int 426 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 427 unsigned int vport, 428 struct mlx5_hca_attr *attr) 429 { 430 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 431 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 432 void *vctx; 433 int status, syndrome, rc; 434 435 /* Query NIC vport context to determine inline mode. */ 436 MLX5_SET(query_nic_vport_context_in, in, opcode, 437 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 438 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 439 if (vport) 440 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 441 rc = mlx5_glue->devx_general_cmd(ctx, 442 in, sizeof(in), 443 out, sizeof(out)); 444 if (rc) 445 goto error; 446 status = MLX5_GET(query_nic_vport_context_out, out, status); 447 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 448 if (status) { 449 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 450 "status %x, syndrome = %x", status, syndrome); 451 return -1; 452 } 453 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 454 nic_vport_context); 455 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 456 min_wqe_inline_mode); 457 return 0; 458 error: 459 rc = (rc > 0) ? -rc : rc; 460 return rc; 461 } 462 463 /** 464 * Query NIC vDPA attributes. 465 * 466 * @param[in] ctx 467 * Context returned from mlx5 open_device() glue function. 468 * @param[out] vdpa_attr 469 * vDPA Attributes structure to fill. 470 */ 471 static void 472 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 473 struct mlx5_hca_vdpa_attr *vdpa_attr) 474 { 475 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 476 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 477 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 478 int status, syndrome, rc; 479 480 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 481 MLX5_SET(query_hca_cap_in, in, op_mod, 482 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 483 MLX5_HCA_CAP_OPMOD_GET_CUR); 484 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 485 status = MLX5_GET(query_hca_cap_out, out, status); 486 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 487 if (rc || status) { 488 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," 489 " status %x, syndrome = %x", status, syndrome); 490 vdpa_attr->valid = 0; 491 } else { 492 vdpa_attr->valid = 1; 493 vdpa_attr->desc_tunnel_offload_type = 494 MLX5_GET(virtio_emulation_cap, hcattr, 495 desc_tunnel_offload_type); 496 vdpa_attr->eth_frame_offload_type = 497 MLX5_GET(virtio_emulation_cap, hcattr, 498 eth_frame_offload_type); 499 vdpa_attr->virtio_version_1_0 = 500 MLX5_GET(virtio_emulation_cap, hcattr, 501 virtio_version_1_0); 502 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 503 tso_ipv4); 504 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 505 tso_ipv6); 506 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 507 tx_csum); 508 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 509 rx_csum); 510 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 511 event_mode); 512 vdpa_attr->virtio_queue_type = 513 MLX5_GET(virtio_emulation_cap, hcattr, 514 virtio_queue_type); 515 vdpa_attr->log_doorbell_stride = 516 MLX5_GET(virtio_emulation_cap, hcattr, 517 log_doorbell_stride); 518 vdpa_attr->log_doorbell_bar_size = 519 MLX5_GET(virtio_emulation_cap, hcattr, 520 log_doorbell_bar_size); 521 vdpa_attr->doorbell_bar_offset = 522 MLX5_GET64(virtio_emulation_cap, hcattr, 523 doorbell_bar_offset); 524 vdpa_attr->max_num_virtio_queues = 525 MLX5_GET(virtio_emulation_cap, hcattr, 526 max_num_virtio_queues); 527 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 528 umem_1_buffer_param_a); 529 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 530 umem_1_buffer_param_b); 531 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 532 umem_2_buffer_param_a); 533 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 534 umem_2_buffer_param_b); 535 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 536 umem_3_buffer_param_a); 537 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 538 umem_3_buffer_param_b); 539 } 540 } 541 542 int 543 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 544 uint32_t ids[], uint32_t num) 545 { 546 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 547 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 548 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 549 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 550 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 551 int ret; 552 uint32_t idx = 0; 553 uint32_t i; 554 555 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 556 rte_errno = EINVAL; 557 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 558 return -rte_errno; 559 } 560 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 561 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 562 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 563 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 564 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 565 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 566 out, sizeof(out)); 567 if (ret) { 568 rte_errno = ret; 569 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 570 (void *)flex_obj); 571 return -rte_errno; 572 } 573 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 574 void *s_off = (void *)((char *)sample + i * 575 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 576 uint32_t en; 577 578 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 579 flow_match_sample_en); 580 if (!en) 581 continue; 582 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 583 flow_match_sample_field_id); 584 } 585 if (num != idx) { 586 rte_errno = EINVAL; 587 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 588 return -rte_errno; 589 } 590 return ret; 591 } 592 593 594 struct mlx5_devx_obj * 595 mlx5_devx_cmd_create_flex_parser(void *ctx, 596 struct mlx5_devx_graph_node_attr *data) 597 { 598 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 599 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 600 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 601 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 602 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 603 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 604 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 605 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 606 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 607 uint32_t i; 608 609 if (!parse_flex_obj) { 610 DRV_LOG(ERR, "Failed to allocate flex parser data."); 611 rte_errno = ENOMEM; 612 return NULL; 613 } 614 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 615 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 616 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 617 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 618 MLX5_SET(parse_graph_flex, flex, header_length_mode, 619 data->header_length_mode); 620 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 621 data->header_length_base_value); 622 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 623 data->header_length_field_offset); 624 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 625 data->header_length_field_shift); 626 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 627 data->header_length_field_mask); 628 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 629 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 630 void *s_off = (void *)((char *)sample + i * 631 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 632 633 if (!s->flow_match_sample_en) 634 continue; 635 MLX5_SET(parse_graph_flow_match_sample, s_off, 636 flow_match_sample_en, !!s->flow_match_sample_en); 637 MLX5_SET(parse_graph_flow_match_sample, s_off, 638 flow_match_sample_field_offset, 639 s->flow_match_sample_field_offset); 640 MLX5_SET(parse_graph_flow_match_sample, s_off, 641 flow_match_sample_offset_mode, 642 s->flow_match_sample_offset_mode); 643 MLX5_SET(parse_graph_flow_match_sample, s_off, 644 flow_match_sample_field_offset_mask, 645 s->flow_match_sample_field_offset_mask); 646 MLX5_SET(parse_graph_flow_match_sample, s_off, 647 flow_match_sample_field_offset_shift, 648 s->flow_match_sample_field_offset_shift); 649 MLX5_SET(parse_graph_flow_match_sample, s_off, 650 flow_match_sample_field_base_offset, 651 s->flow_match_sample_field_base_offset); 652 MLX5_SET(parse_graph_flow_match_sample, s_off, 653 flow_match_sample_tunnel_mode, 654 s->flow_match_sample_tunnel_mode); 655 } 656 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 657 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 658 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 659 void *in_off = (void *)((char *)in_arc + i * 660 MLX5_ST_SZ_BYTES(parse_graph_arc)); 661 void *out_off = (void *)((char *)out_arc + i * 662 MLX5_ST_SZ_BYTES(parse_graph_arc)); 663 664 if (ia->arc_parse_graph_node != 0) { 665 MLX5_SET(parse_graph_arc, in_off, 666 compare_condition_value, 667 ia->compare_condition_value); 668 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 669 ia->start_inner_tunnel); 670 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 671 ia->arc_parse_graph_node); 672 MLX5_SET(parse_graph_arc, in_off, 673 parse_graph_node_handle, 674 ia->parse_graph_node_handle); 675 } 676 if (oa->arc_parse_graph_node != 0) { 677 MLX5_SET(parse_graph_arc, out_off, 678 compare_condition_value, 679 oa->compare_condition_value); 680 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 681 oa->start_inner_tunnel); 682 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 683 oa->arc_parse_graph_node); 684 MLX5_SET(parse_graph_arc, out_off, 685 parse_graph_node_handle, 686 oa->parse_graph_node_handle); 687 } 688 } 689 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 690 out, sizeof(out)); 691 if (!parse_flex_obj->obj) { 692 rte_errno = errno; 693 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 694 "by using DevX."); 695 mlx5_free(parse_flex_obj); 696 return NULL; 697 } 698 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 699 return parse_flex_obj; 700 } 701 702 static int 703 mlx5_devx_query_pkt_integrity_match(void *hcattr) 704 { 705 return MLX5_GET(flow_table_nic_cap, hcattr, 706 ft_field_support_2_nic_receive.inner_l3_ok) && 707 MLX5_GET(flow_table_nic_cap, hcattr, 708 ft_field_support_2_nic_receive.inner_l4_ok) && 709 MLX5_GET(flow_table_nic_cap, hcattr, 710 ft_field_support_2_nic_receive.outer_l3_ok) && 711 MLX5_GET(flow_table_nic_cap, hcattr, 712 ft_field_support_2_nic_receive.outer_l4_ok) && 713 MLX5_GET(flow_table_nic_cap, hcattr, 714 ft_field_support_2_nic_receive 715 .inner_ipv4_checksum_ok) && 716 MLX5_GET(flow_table_nic_cap, hcattr, 717 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 718 MLX5_GET(flow_table_nic_cap, hcattr, 719 ft_field_support_2_nic_receive 720 .outer_ipv4_checksum_ok) && 721 MLX5_GET(flow_table_nic_cap, hcattr, 722 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 723 } 724 725 /** 726 * Query HCA attributes. 727 * Using those attributes we can check on run time if the device 728 * is having the required capabilities. 729 * 730 * @param[in] ctx 731 * Context returned from mlx5 open_device() glue function. 732 * @param[out] attr 733 * Attributes device values. 734 * 735 * @return 736 * 0 on success, a negative value otherwise. 737 */ 738 int 739 mlx5_devx_cmd_query_hca_attr(void *ctx, 740 struct mlx5_hca_attr *attr) 741 { 742 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 743 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 744 void *hcattr; 745 int status, syndrome, rc, i; 746 uint64_t general_obj_types_supported = 0; 747 748 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 749 MLX5_SET(query_hca_cap_in, in, op_mod, 750 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 751 MLX5_HCA_CAP_OPMOD_GET_CUR); 752 753 rc = mlx5_glue->devx_general_cmd(ctx, 754 in, sizeof(in), out, sizeof(out)); 755 if (rc) 756 goto error; 757 status = MLX5_GET(query_hca_cap_out, out, status); 758 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 759 if (status) { 760 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 761 "status %x, syndrome = %x", status, syndrome); 762 return -1; 763 } 764 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 765 attr->flow_counter_bulk_alloc_bitmap = 766 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 767 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 768 flow_counters_dump); 769 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 770 log_max_rqt_size); 771 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 772 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 773 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 774 log_max_hairpin_queues); 775 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 776 log_max_hairpin_wq_data_sz); 777 attr->log_max_hairpin_num_packets = MLX5_GET 778 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 779 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 780 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 781 relaxed_ordering_write); 782 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 783 relaxed_ordering_read); 784 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 785 access_register_user); 786 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 787 eth_net_offloads); 788 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 789 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 790 flex_parser_protocols); 791 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 792 max_geneve_tlv_options); 793 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 794 max_geneve_tlv_option_data_len); 795 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 796 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 797 general_obj_types) & 798 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 799 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 800 general_obj_types) & 801 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 802 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 803 general_obj_types) & 804 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 805 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 806 general_obj_types) & 807 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 808 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 809 wqe_index_ignore_cap); 810 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 811 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 812 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 813 log_max_static_sq_wq); 814 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 815 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 816 device_frequency_khz); 817 attr->scatter_fcs_w_decap_disable = 818 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 819 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 820 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 821 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 822 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); 823 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 824 regexp_num_of_engines); 825 /* Read the general_obj_types bitmap and extract the relevant bits. */ 826 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 827 general_obj_types); 828 attr->vdpa.valid = !!(general_obj_types_supported & 829 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 830 attr->vdpa.queue_counters_valid = 831 !!(general_obj_types_supported & 832 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 833 attr->parse_graph_flex_node = 834 !!(general_obj_types_supported & 835 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 836 attr->flow_hit_aso = !!(general_obj_types_supported & 837 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 838 attr->geneve_tlv_opt = !!(general_obj_types_supported & 839 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 840 attr->dek = !!(general_obj_types_supported & 841 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 842 attr->import_kek = !!(general_obj_types_supported & 843 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 844 attr->credential = !!(general_obj_types_supported & 845 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 846 attr->crypto_login = !!(general_obj_types_supported & 847 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 848 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 849 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 850 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 851 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 852 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 853 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 854 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 855 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 856 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 857 attr->reg_c_preserve = 858 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 859 attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo); 860 attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress); 861 attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress); 862 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 863 compress_min_block_size); 864 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 865 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 866 log_compress_mmo_size); 867 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 868 log_decompress_mmo_size); 869 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 870 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 871 mini_cqe_resp_flow_tag); 872 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 873 mini_cqe_resp_l3_l4_tag); 874 attr->umr_indirect_mkey_disabled = 875 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 876 attr->umr_modify_entity_size_disabled = 877 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 878 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 879 if (attr->crypto) 880 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); 881 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 882 general_obj_types) & 883 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 884 if (attr->qos.sup) { 885 MLX5_SET(query_hca_cap_in, in, op_mod, 886 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 887 MLX5_HCA_CAP_OPMOD_GET_CUR); 888 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 889 out, sizeof(out)); 890 if (rc) 891 goto error; 892 if (status) { 893 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," 894 " status %x, syndrome = %x", status, syndrome); 895 return -1; 896 } 897 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 898 attr->qos.flow_meter_old = 899 MLX5_GET(qos_cap, hcattr, flow_meter_old); 900 attr->qos.log_max_flow_meter = 901 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 902 attr->qos.flow_meter_reg_c_ids = 903 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 904 attr->qos.flow_meter = 905 MLX5_GET(qos_cap, hcattr, flow_meter); 906 attr->qos.packet_pacing = 907 MLX5_GET(qos_cap, hcattr, packet_pacing); 908 attr->qos.wqe_rate_pp = 909 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 910 if (attr->qos.flow_meter_aso_sup) { 911 attr->qos.log_meter_aso_granularity = 912 MLX5_GET(qos_cap, hcattr, 913 log_meter_aso_granularity); 914 attr->qos.log_meter_aso_max_alloc = 915 MLX5_GET(qos_cap, hcattr, 916 log_meter_aso_max_alloc); 917 attr->qos.log_max_num_meter_aso = 918 MLX5_GET(qos_cap, hcattr, 919 log_max_num_meter_aso); 920 } 921 } 922 if (attr->vdpa.valid) 923 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 924 if (!attr->eth_net_offloads) 925 return 0; 926 927 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 928 memset(in, 0, sizeof(in)); 929 memset(out, 0, sizeof(out)); 930 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 931 MLX5_SET(query_hca_cap_in, in, op_mod, 932 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 933 MLX5_HCA_CAP_OPMOD_GET_CUR); 934 935 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 936 if (rc) 937 goto error; 938 status = MLX5_GET(query_hca_cap_out, out, status); 939 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 940 if (status) { 941 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 942 "status %x, syndrome = %x", status, syndrome); 943 attr->log_max_ft_sampler_num = 0; 944 return -1; 945 } 946 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 947 attr->log_max_ft_sampler_num = MLX5_GET 948 (flow_table_nic_cap, hcattr, 949 flow_table_properties_nic_receive.log_max_ft_sampler_num); 950 attr->flow.tunnel_header_0_1 = MLX5_GET 951 (flow_table_nic_cap, hcattr, 952 ft_field_support_2_nic_receive.tunnel_header_0_1); 953 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 954 attr->inner_ipv4_ihl = MLX5_GET 955 (flow_table_nic_cap, hcattr, 956 ft_field_support_2_nic_receive.inner_ipv4_ihl); 957 attr->outer_ipv4_ihl = MLX5_GET 958 (flow_table_nic_cap, hcattr, 959 ft_field_support_2_nic_receive.outer_ipv4_ihl); 960 /* Query HCA offloads for Ethernet protocol. */ 961 memset(in, 0, sizeof(in)); 962 memset(out, 0, sizeof(out)); 963 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 964 MLX5_SET(query_hca_cap_in, in, op_mod, 965 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 966 MLX5_HCA_CAP_OPMOD_GET_CUR); 967 968 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 969 if (rc) { 970 attr->eth_net_offloads = 0; 971 goto error; 972 } 973 status = MLX5_GET(query_hca_cap_out, out, status); 974 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 975 if (status) { 976 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 977 "status %x, syndrome = %x", status, syndrome); 978 attr->eth_net_offloads = 0; 979 return -1; 980 } 981 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 982 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 983 hcattr, wqe_vlan_insert); 984 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 985 hcattr, csum_cap); 986 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 987 lro_cap); 988 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 989 hcattr, tunnel_lro_gre); 990 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 991 hcattr, tunnel_lro_vxlan); 992 attr->lro_max_msg_sz_mode = MLX5_GET 993 (per_protocol_networking_offload_caps, 994 hcattr, lro_max_msg_sz_mode); 995 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 996 attr->lro_timer_supported_periods[i] = 997 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 998 lro_timer_supported_periods[i]); 999 } 1000 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1001 hcattr, lro_min_mss_size); 1002 attr->tunnel_stateless_geneve_rx = 1003 MLX5_GET(per_protocol_networking_offload_caps, 1004 hcattr, tunnel_stateless_geneve_rx); 1005 attr->geneve_max_opt_len = 1006 MLX5_GET(per_protocol_networking_offload_caps, 1007 hcattr, max_geneve_opt_len); 1008 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1009 hcattr, wqe_inline_mode); 1010 attr->tunnel_stateless_gtp = MLX5_GET 1011 (per_protocol_networking_offload_caps, 1012 hcattr, tunnel_stateless_gtp); 1013 attr->rss_ind_tbl_cap = MLX5_GET 1014 (per_protocol_networking_offload_caps, 1015 hcattr, rss_ind_tbl_cap); 1016 /* Query HCA attribute for ROCE. */ 1017 if (attr->roce) { 1018 memset(in, 0, sizeof(in)); 1019 memset(out, 0, sizeof(out)); 1020 MLX5_SET(query_hca_cap_in, in, opcode, 1021 MLX5_CMD_OP_QUERY_HCA_CAP); 1022 MLX5_SET(query_hca_cap_in, in, op_mod, 1023 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1024 MLX5_HCA_CAP_OPMOD_GET_CUR); 1025 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 1026 out, sizeof(out)); 1027 if (rc) 1028 goto error; 1029 status = MLX5_GET(query_hca_cap_out, out, status); 1030 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 1031 if (status) { 1032 DRV_LOG(DEBUG, 1033 "Failed to query devx HCA ROCE capabilities, " 1034 "status %x, syndrome = %x", status, syndrome); 1035 return -1; 1036 } 1037 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 1038 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1039 } 1040 if (attr->eth_virt && 1041 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1042 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1043 if (rc) { 1044 attr->eth_virt = 0; 1045 goto error; 1046 } 1047 } 1048 return 0; 1049 error: 1050 rc = (rc > 0) ? -rc : rc; 1051 return rc; 1052 } 1053 1054 /** 1055 * Query TIS transport domain from QP verbs object using DevX API. 1056 * 1057 * @param[in] qp 1058 * Pointer to verbs QP returned by ibv_create_qp . 1059 * @param[in] tis_num 1060 * TIS number of TIS to query. 1061 * @param[out] tis_td 1062 * Pointer to TIS transport domain variable, to be set by the routine. 1063 * 1064 * @return 1065 * 0 on success, a negative value otherwise. 1066 */ 1067 int 1068 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1069 uint32_t *tis_td) 1070 { 1071 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1072 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1073 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1074 int rc; 1075 void *tis_ctx; 1076 1077 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1078 MLX5_SET(query_tis_in, in, tisn, tis_num); 1079 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1080 if (rc) { 1081 DRV_LOG(ERR, "Failed to query QP using DevX"); 1082 return -rc; 1083 }; 1084 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1085 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1086 return 0; 1087 #else 1088 (void)qp; 1089 (void)tis_num; 1090 (void)tis_td; 1091 return -ENOTSUP; 1092 #endif 1093 } 1094 1095 /** 1096 * Fill WQ data for DevX API command. 1097 * Utility function for use when creating DevX objects containing a WQ. 1098 * 1099 * @param[in] wq_ctx 1100 * Pointer to WQ context to fill with data. 1101 * @param [in] wq_attr 1102 * Pointer to WQ attributes structure to fill in WQ context. 1103 */ 1104 static void 1105 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1106 { 1107 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1108 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1109 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1110 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1111 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1112 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1113 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1114 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1115 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1116 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1117 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1118 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1119 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1120 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1121 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1122 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1123 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1124 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1125 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1126 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1127 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1128 wq_attr->log_hairpin_num_packets); 1129 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1130 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1131 wq_attr->single_wqe_log_num_of_strides); 1132 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1133 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1134 wq_attr->single_stride_log_num_of_bytes); 1135 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1136 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1137 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1138 } 1139 1140 /** 1141 * Create RQ using DevX API. 1142 * 1143 * @param[in] ctx 1144 * Context returned from mlx5 open_device() glue function. 1145 * @param [in] rq_attr 1146 * Pointer to create RQ attributes structure. 1147 * @param [in] socket 1148 * CPU socket ID for allocations. 1149 * 1150 * @return 1151 * The DevX object created, NULL otherwise and rte_errno is set. 1152 */ 1153 struct mlx5_devx_obj * 1154 mlx5_devx_cmd_create_rq(void *ctx, 1155 struct mlx5_devx_create_rq_attr *rq_attr, 1156 int socket) 1157 { 1158 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1159 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1160 void *rq_ctx, *wq_ctx; 1161 struct mlx5_devx_wq_attr *wq_attr; 1162 struct mlx5_devx_obj *rq = NULL; 1163 1164 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1165 if (!rq) { 1166 DRV_LOG(ERR, "Failed to allocate RQ data"); 1167 rte_errno = ENOMEM; 1168 return NULL; 1169 } 1170 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1171 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1172 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1173 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1174 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1175 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1176 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1177 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1178 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1179 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1180 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1181 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1182 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1183 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1184 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1185 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1186 wq_attr = &rq_attr->wq_attr; 1187 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1188 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1189 out, sizeof(out)); 1190 if (!rq->obj) { 1191 DRV_LOG(ERR, "Failed to create RQ using DevX"); 1192 rte_errno = errno; 1193 mlx5_free(rq); 1194 return NULL; 1195 } 1196 rq->id = MLX5_GET(create_rq_out, out, rqn); 1197 return rq; 1198 } 1199 1200 /** 1201 * Modify RQ using DevX API. 1202 * 1203 * @param[in] rq 1204 * Pointer to RQ object structure. 1205 * @param [in] rq_attr 1206 * Pointer to modify RQ attributes structure. 1207 * 1208 * @return 1209 * 0 on success, a negative errno value otherwise and rte_errno is set. 1210 */ 1211 int 1212 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1213 struct mlx5_devx_modify_rq_attr *rq_attr) 1214 { 1215 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1216 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1217 void *rq_ctx, *wq_ctx; 1218 int ret; 1219 1220 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1221 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1222 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1223 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1224 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1225 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1226 if (rq_attr->modify_bitmask & 1227 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1228 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1229 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1230 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1231 if (rq_attr->modify_bitmask & 1232 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1233 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1234 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1235 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1236 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1237 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1238 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1239 } 1240 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1241 out, sizeof(out)); 1242 if (ret) { 1243 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1244 rte_errno = errno; 1245 return -errno; 1246 } 1247 return ret; 1248 } 1249 1250 /** 1251 * Create TIR using DevX API. 1252 * 1253 * @param[in] ctx 1254 * Context returned from mlx5 open_device() glue function. 1255 * @param [in] tir_attr 1256 * Pointer to TIR attributes structure. 1257 * 1258 * @return 1259 * The DevX object created, NULL otherwise and rte_errno is set. 1260 */ 1261 struct mlx5_devx_obj * 1262 mlx5_devx_cmd_create_tir(void *ctx, 1263 struct mlx5_devx_tir_attr *tir_attr) 1264 { 1265 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1266 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1267 void *tir_ctx, *outer, *inner, *rss_key; 1268 struct mlx5_devx_obj *tir = NULL; 1269 1270 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1271 if (!tir) { 1272 DRV_LOG(ERR, "Failed to allocate TIR data"); 1273 rte_errno = ENOMEM; 1274 return NULL; 1275 } 1276 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1277 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1278 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1279 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1280 tir_attr->lro_timeout_period_usecs); 1281 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1282 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1283 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1284 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1285 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1286 tir_attr->tunneled_offload_en); 1287 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1288 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1289 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1290 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1291 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1292 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1293 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1294 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1295 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1296 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1297 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1298 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1299 tir_attr->rx_hash_field_selector_outer.selected_fields); 1300 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1301 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1302 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1303 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1304 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1305 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1306 tir_attr->rx_hash_field_selector_inner.selected_fields); 1307 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1308 out, sizeof(out)); 1309 if (!tir->obj) { 1310 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1311 rte_errno = errno; 1312 mlx5_free(tir); 1313 return NULL; 1314 } 1315 tir->id = MLX5_GET(create_tir_out, out, tirn); 1316 return tir; 1317 } 1318 1319 /** 1320 * Modify TIR using DevX API. 1321 * 1322 * @param[in] tir 1323 * Pointer to TIR DevX object structure. 1324 * @param [in] modify_tir_attr 1325 * Pointer to TIR modification attributes structure. 1326 * 1327 * @return 1328 * 0 on success, a negative errno value otherwise and rte_errno is set. 1329 */ 1330 int 1331 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1332 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1333 { 1334 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1335 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1336 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1337 void *tir_ctx; 1338 int ret; 1339 1340 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1341 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1342 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1343 modify_tir_attr->modify_bitmask); 1344 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1345 if (modify_tir_attr->modify_bitmask & 1346 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1347 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1348 tir_attr->lro_timeout_period_usecs); 1349 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1350 tir_attr->lro_enable_mask); 1351 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1352 tir_attr->lro_max_msg_sz); 1353 } 1354 if (modify_tir_attr->modify_bitmask & 1355 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1356 MLX5_SET(tirc, tir_ctx, indirect_table, 1357 tir_attr->indirect_table); 1358 if (modify_tir_attr->modify_bitmask & 1359 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1360 int i; 1361 void *outer, *inner; 1362 1363 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1364 tir_attr->rx_hash_symmetric); 1365 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1366 for (i = 0; i < 10; i++) { 1367 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1368 tir_attr->rx_hash_toeplitz_key[i]); 1369 } 1370 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1371 rx_hash_field_selector_outer); 1372 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1373 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1374 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1375 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1376 MLX5_SET 1377 (rx_hash_field_select, outer, selected_fields, 1378 tir_attr->rx_hash_field_selector_outer.selected_fields); 1379 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1380 rx_hash_field_selector_inner); 1381 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1382 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1383 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1384 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1385 MLX5_SET 1386 (rx_hash_field_select, inner, selected_fields, 1387 tir_attr->rx_hash_field_selector_inner.selected_fields); 1388 } 1389 if (modify_tir_attr->modify_bitmask & 1390 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1391 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1392 } 1393 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1394 out, sizeof(out)); 1395 if (ret) { 1396 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1397 rte_errno = errno; 1398 return -errno; 1399 } 1400 return ret; 1401 } 1402 1403 /** 1404 * Create RQT using DevX API. 1405 * 1406 * @param[in] ctx 1407 * Context returned from mlx5 open_device() glue function. 1408 * @param [in] rqt_attr 1409 * Pointer to RQT attributes structure. 1410 * 1411 * @return 1412 * The DevX object created, NULL otherwise and rte_errno is set. 1413 */ 1414 struct mlx5_devx_obj * 1415 mlx5_devx_cmd_create_rqt(void *ctx, 1416 struct mlx5_devx_rqt_attr *rqt_attr) 1417 { 1418 uint32_t *in = NULL; 1419 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1420 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1421 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1422 void *rqt_ctx; 1423 struct mlx5_devx_obj *rqt = NULL; 1424 int i; 1425 1426 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1427 if (!in) { 1428 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1429 rte_errno = ENOMEM; 1430 return NULL; 1431 } 1432 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1433 if (!rqt) { 1434 DRV_LOG(ERR, "Failed to allocate RQT data"); 1435 rte_errno = ENOMEM; 1436 mlx5_free(in); 1437 return NULL; 1438 } 1439 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1440 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1441 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1442 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1443 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1444 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1445 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1446 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1447 mlx5_free(in); 1448 if (!rqt->obj) { 1449 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1450 rte_errno = errno; 1451 mlx5_free(rqt); 1452 return NULL; 1453 } 1454 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1455 return rqt; 1456 } 1457 1458 /** 1459 * Modify RQT using DevX API. 1460 * 1461 * @param[in] rqt 1462 * Pointer to RQT DevX object structure. 1463 * @param [in] rqt_attr 1464 * Pointer to RQT attributes structure. 1465 * 1466 * @return 1467 * 0 on success, a negative errno value otherwise and rte_errno is set. 1468 */ 1469 int 1470 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1471 struct mlx5_devx_rqt_attr *rqt_attr) 1472 { 1473 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1474 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1475 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1476 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1477 void *rqt_ctx; 1478 int i; 1479 int ret; 1480 1481 if (!in) { 1482 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1483 rte_errno = ENOMEM; 1484 return -ENOMEM; 1485 } 1486 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1487 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1488 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1489 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1490 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1491 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1492 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1493 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1494 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1495 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1496 mlx5_free(in); 1497 if (ret) { 1498 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1499 rte_errno = errno; 1500 return -rte_errno; 1501 } 1502 return ret; 1503 } 1504 1505 /** 1506 * Create SQ using DevX API. 1507 * 1508 * @param[in] ctx 1509 * Context returned from mlx5 open_device() glue function. 1510 * @param [in] sq_attr 1511 * Pointer to SQ attributes structure. 1512 * @param [in] socket 1513 * CPU socket ID for allocations. 1514 * 1515 * @return 1516 * The DevX object created, NULL otherwise and rte_errno is set. 1517 **/ 1518 struct mlx5_devx_obj * 1519 mlx5_devx_cmd_create_sq(void *ctx, 1520 struct mlx5_devx_create_sq_attr *sq_attr) 1521 { 1522 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1523 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1524 void *sq_ctx; 1525 void *wq_ctx; 1526 struct mlx5_devx_wq_attr *wq_attr; 1527 struct mlx5_devx_obj *sq = NULL; 1528 1529 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1530 if (!sq) { 1531 DRV_LOG(ERR, "Failed to allocate SQ data"); 1532 rte_errno = ENOMEM; 1533 return NULL; 1534 } 1535 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1536 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1537 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1538 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1539 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1540 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1541 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1542 sq_attr->allow_multi_pkt_send_wqe); 1543 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1544 sq_attr->min_wqe_inline_mode); 1545 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1546 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1547 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1548 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1549 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1550 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1551 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1552 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1553 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1554 sq_attr->packet_pacing_rate_limit_index); 1555 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1556 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1557 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1558 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1559 wq_attr = &sq_attr->wq_attr; 1560 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1561 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1562 out, sizeof(out)); 1563 if (!sq->obj) { 1564 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1565 rte_errno = errno; 1566 mlx5_free(sq); 1567 return NULL; 1568 } 1569 sq->id = MLX5_GET(create_sq_out, out, sqn); 1570 return sq; 1571 } 1572 1573 /** 1574 * Modify SQ using DevX API. 1575 * 1576 * @param[in] sq 1577 * Pointer to SQ object structure. 1578 * @param [in] sq_attr 1579 * Pointer to SQ attributes structure. 1580 * 1581 * @return 1582 * 0 on success, a negative errno value otherwise and rte_errno is set. 1583 */ 1584 int 1585 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1586 struct mlx5_devx_modify_sq_attr *sq_attr) 1587 { 1588 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1589 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1590 void *sq_ctx; 1591 int ret; 1592 1593 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1594 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1595 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1596 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1597 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1598 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1599 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1600 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1601 out, sizeof(out)); 1602 if (ret) { 1603 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1604 rte_errno = errno; 1605 return -rte_errno; 1606 } 1607 return ret; 1608 } 1609 1610 /** 1611 * Create TIS using DevX API. 1612 * 1613 * @param[in] ctx 1614 * Context returned from mlx5 open_device() glue function. 1615 * @param [in] tis_attr 1616 * Pointer to TIS attributes structure. 1617 * 1618 * @return 1619 * The DevX object created, NULL otherwise and rte_errno is set. 1620 */ 1621 struct mlx5_devx_obj * 1622 mlx5_devx_cmd_create_tis(void *ctx, 1623 struct mlx5_devx_tis_attr *tis_attr) 1624 { 1625 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1626 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1627 struct mlx5_devx_obj *tis = NULL; 1628 void *tis_ctx; 1629 1630 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1631 if (!tis) { 1632 DRV_LOG(ERR, "Failed to allocate TIS object"); 1633 rte_errno = ENOMEM; 1634 return NULL; 1635 } 1636 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1637 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1638 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1639 tis_attr->strict_lag_tx_port_affinity); 1640 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1641 tis_attr->lag_tx_port_affinity); 1642 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1643 MLX5_SET(tisc, tis_ctx, transport_domain, 1644 tis_attr->transport_domain); 1645 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1646 out, sizeof(out)); 1647 if (!tis->obj) { 1648 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1649 rte_errno = errno; 1650 mlx5_free(tis); 1651 return NULL; 1652 } 1653 tis->id = MLX5_GET(create_tis_out, out, tisn); 1654 return tis; 1655 } 1656 1657 /** 1658 * Create transport domain using DevX API. 1659 * 1660 * @param[in] ctx 1661 * Context returned from mlx5 open_device() glue function. 1662 * @return 1663 * The DevX object created, NULL otherwise and rte_errno is set. 1664 */ 1665 struct mlx5_devx_obj * 1666 mlx5_devx_cmd_create_td(void *ctx) 1667 { 1668 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1669 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1670 struct mlx5_devx_obj *td = NULL; 1671 1672 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1673 if (!td) { 1674 DRV_LOG(ERR, "Failed to allocate TD object"); 1675 rte_errno = ENOMEM; 1676 return NULL; 1677 } 1678 MLX5_SET(alloc_transport_domain_in, in, opcode, 1679 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1680 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1681 out, sizeof(out)); 1682 if (!td->obj) { 1683 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1684 rte_errno = errno; 1685 mlx5_free(td); 1686 return NULL; 1687 } 1688 td->id = MLX5_GET(alloc_transport_domain_out, out, 1689 transport_domain); 1690 return td; 1691 } 1692 1693 /** 1694 * Dump all flows to file. 1695 * 1696 * @param[in] fdb_domain 1697 * FDB domain. 1698 * @param[in] rx_domain 1699 * RX domain. 1700 * @param[in] tx_domain 1701 * TX domain. 1702 * @param[out] file 1703 * Pointer to file stream. 1704 * 1705 * @return 1706 * 0 on success, a nagative value otherwise. 1707 */ 1708 int 1709 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1710 void *rx_domain __rte_unused, 1711 void *tx_domain __rte_unused, FILE *file __rte_unused) 1712 { 1713 int ret = 0; 1714 1715 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1716 if (fdb_domain) { 1717 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1718 if (ret) 1719 return ret; 1720 } 1721 MLX5_ASSERT(rx_domain); 1722 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1723 if (ret) 1724 return ret; 1725 MLX5_ASSERT(tx_domain); 1726 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1727 #else 1728 ret = ENOTSUP; 1729 #endif 1730 return -ret; 1731 } 1732 1733 int 1734 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 1735 FILE *file __rte_unused) 1736 { 1737 int ret = 0; 1738 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 1739 if (rule_info) 1740 ret = mlx5_glue->dr_dump_rule(file, rule_info); 1741 #else 1742 ret = ENOTSUP; 1743 #endif 1744 return -ret; 1745 } 1746 1747 /* 1748 * Create CQ using DevX API. 1749 * 1750 * @param[in] ctx 1751 * Context returned from mlx5 open_device() glue function. 1752 * @param [in] attr 1753 * Pointer to CQ attributes structure. 1754 * 1755 * @return 1756 * The DevX object created, NULL otherwise and rte_errno is set. 1757 */ 1758 struct mlx5_devx_obj * 1759 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1760 { 1761 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1762 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1763 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1764 sizeof(*cq_obj), 1765 0, SOCKET_ID_ANY); 1766 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1767 1768 if (!cq_obj) { 1769 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1770 rte_errno = ENOMEM; 1771 return NULL; 1772 } 1773 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1774 if (attr->db_umem_valid) { 1775 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1776 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1777 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1778 } else { 1779 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1780 } 1781 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1782 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1783 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1784 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1785 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1786 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1787 MLX5_SET(cqc, cqctx, log_page_size, 1788 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1789 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1790 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1791 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1792 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1793 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1794 attr->mini_cqe_res_format_ext); 1795 if (attr->q_umem_valid) { 1796 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1797 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1798 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1799 attr->q_umem_offset); 1800 } 1801 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1802 sizeof(out)); 1803 if (!cq_obj->obj) { 1804 rte_errno = errno; 1805 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1806 mlx5_free(cq_obj); 1807 return NULL; 1808 } 1809 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1810 return cq_obj; 1811 } 1812 1813 /** 1814 * Create VIRTQ using DevX API. 1815 * 1816 * @param[in] ctx 1817 * Context returned from mlx5 open_device() glue function. 1818 * @param [in] attr 1819 * Pointer to VIRTQ attributes structure. 1820 * 1821 * @return 1822 * The DevX object created, NULL otherwise and rte_errno is set. 1823 */ 1824 struct mlx5_devx_obj * 1825 mlx5_devx_cmd_create_virtq(void *ctx, 1826 struct mlx5_devx_virtq_attr *attr) 1827 { 1828 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1829 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1830 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1831 sizeof(*virtq_obj), 1832 0, SOCKET_ID_ANY); 1833 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1834 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1835 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1836 1837 if (!virtq_obj) { 1838 DRV_LOG(ERR, "Failed to allocate virtq data."); 1839 rte_errno = ENOMEM; 1840 return NULL; 1841 } 1842 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1843 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1844 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1845 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1846 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1847 attr->hw_available_index); 1848 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1849 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1850 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1851 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1852 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1853 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1854 attr->virtio_version_1_0); 1855 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1856 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1857 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1858 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1859 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1860 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1861 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1862 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1863 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1864 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1865 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1866 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1867 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1868 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1869 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1870 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1871 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1872 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1873 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1874 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 1875 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 1876 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 1877 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1878 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1879 sizeof(out)); 1880 if (!virtq_obj->obj) { 1881 rte_errno = errno; 1882 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 1883 mlx5_free(virtq_obj); 1884 return NULL; 1885 } 1886 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1887 return virtq_obj; 1888 } 1889 1890 /** 1891 * Modify VIRTQ using DevX API. 1892 * 1893 * @param[in] virtq_obj 1894 * Pointer to virtq object structure. 1895 * @param [in] attr 1896 * Pointer to modify virtq attributes structure. 1897 * 1898 * @return 1899 * 0 on success, a negative errno value otherwise and rte_errno is set. 1900 */ 1901 int 1902 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 1903 struct mlx5_devx_virtq_attr *attr) 1904 { 1905 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1906 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1907 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1908 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1909 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1910 int ret; 1911 1912 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1913 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 1914 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1915 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1916 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1917 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 1918 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1919 switch (attr->type) { 1920 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 1921 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 1922 break; 1923 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 1924 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 1925 attr->dirty_bitmap_mkey); 1926 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 1927 attr->dirty_bitmap_addr); 1928 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 1929 attr->dirty_bitmap_size); 1930 break; 1931 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 1932 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 1933 attr->dirty_bitmap_dump_enable); 1934 break; 1935 default: 1936 rte_errno = EINVAL; 1937 return -rte_errno; 1938 } 1939 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 1940 out, sizeof(out)); 1941 if (ret) { 1942 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1943 rte_errno = errno; 1944 return -rte_errno; 1945 } 1946 return ret; 1947 } 1948 1949 /** 1950 * Query VIRTQ using DevX API. 1951 * 1952 * @param[in] virtq_obj 1953 * Pointer to virtq object structure. 1954 * @param [in/out] attr 1955 * Pointer to virtq attributes structure. 1956 * 1957 * @return 1958 * 0 on success, a negative errno value otherwise and rte_errno is set. 1959 */ 1960 int 1961 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 1962 struct mlx5_devx_virtq_attr *attr) 1963 { 1964 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1965 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 1966 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 1967 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 1968 int ret; 1969 1970 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1971 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1972 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1973 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1974 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1975 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 1976 out, sizeof(out)); 1977 if (ret) { 1978 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1979 rte_errno = errno; 1980 return -errno; 1981 } 1982 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 1983 hw_available_index); 1984 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 1985 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 1986 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 1987 virtio_q_context.error_type); 1988 return ret; 1989 } 1990 1991 /** 1992 * Create QP using DevX API. 1993 * 1994 * @param[in] ctx 1995 * Context returned from mlx5 open_device() glue function. 1996 * @param [in] attr 1997 * Pointer to QP attributes structure. 1998 * 1999 * @return 2000 * The DevX object created, NULL otherwise and rte_errno is set. 2001 */ 2002 struct mlx5_devx_obj * 2003 mlx5_devx_cmd_create_qp(void *ctx, 2004 struct mlx5_devx_qp_attr *attr) 2005 { 2006 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2007 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2008 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2009 sizeof(*qp_obj), 2010 0, SOCKET_ID_ANY); 2011 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2012 2013 if (!qp_obj) { 2014 DRV_LOG(ERR, "Failed to allocate QP data."); 2015 rte_errno = ENOMEM; 2016 return NULL; 2017 } 2018 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2019 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2020 MLX5_SET(qpc, qpc, pd, attr->pd); 2021 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2022 if (attr->uar_index) { 2023 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2024 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2025 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2026 MLX5_SET(qpc, qpc, log_page_size, 2027 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2028 if (attr->sq_size) { 2029 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 2030 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2031 MLX5_SET(qpc, qpc, log_sq_size, 2032 rte_log2_u32(attr->sq_size)); 2033 } else { 2034 MLX5_SET(qpc, qpc, no_sq, 1); 2035 } 2036 if (attr->rq_size) { 2037 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 2038 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2039 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2040 MLX5_LOG_RQ_STRIDE_SHIFT); 2041 MLX5_SET(qpc, qpc, log_rq_size, 2042 rte_log2_u32(attr->rq_size)); 2043 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2044 } else { 2045 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2046 } 2047 if (attr->dbr_umem_valid) { 2048 MLX5_SET(qpc, qpc, dbr_umem_valid, 2049 attr->dbr_umem_valid); 2050 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2051 } 2052 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2053 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2054 attr->wq_umem_offset); 2055 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2056 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2057 } else { 2058 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2059 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2060 MLX5_SET(qpc, qpc, no_sq, 1); 2061 } 2062 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2063 sizeof(out)); 2064 if (!qp_obj->obj) { 2065 rte_errno = errno; 2066 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 2067 mlx5_free(qp_obj); 2068 return NULL; 2069 } 2070 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2071 return qp_obj; 2072 } 2073 2074 /** 2075 * Modify QP using DevX API. 2076 * Currently supports only force loop-back QP. 2077 * 2078 * @param[in] qp 2079 * Pointer to QP object structure. 2080 * @param [in] qp_st_mod_op 2081 * The QP state modification operation. 2082 * @param [in] remote_qp_id 2083 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2084 * 2085 * @return 2086 * 0 on success, a negative errno value otherwise and rte_errno is set. 2087 */ 2088 int 2089 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2090 uint32_t remote_qp_id) 2091 { 2092 union { 2093 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2094 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2095 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2096 } in; 2097 union { 2098 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2099 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2100 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2101 } out; 2102 void *qpc; 2103 int ret; 2104 unsigned int inlen; 2105 unsigned int outlen; 2106 2107 memset(&in, 0, sizeof(in)); 2108 memset(&out, 0, sizeof(out)); 2109 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2110 switch (qp_st_mod_op) { 2111 case MLX5_CMD_OP_RST2INIT_QP: 2112 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2113 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2114 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2115 MLX5_SET(qpc, qpc, rre, 1); 2116 MLX5_SET(qpc, qpc, rwe, 1); 2117 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2118 inlen = sizeof(in.rst2init); 2119 outlen = sizeof(out.rst2init); 2120 break; 2121 case MLX5_CMD_OP_INIT2RTR_QP: 2122 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2123 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2124 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2125 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2126 MLX5_SET(qpc, qpc, mtu, 1); 2127 MLX5_SET(qpc, qpc, log_msg_max, 30); 2128 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2129 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2130 inlen = sizeof(in.init2rtr); 2131 outlen = sizeof(out.init2rtr); 2132 break; 2133 case MLX5_CMD_OP_RTR2RTS_QP: 2134 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2135 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2136 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 2137 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2138 MLX5_SET(qpc, qpc, retry_count, 7); 2139 MLX5_SET(qpc, qpc, rnr_retry, 7); 2140 inlen = sizeof(in.rtr2rts); 2141 outlen = sizeof(out.rtr2rts); 2142 break; 2143 default: 2144 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2145 qp_st_mod_op); 2146 rte_errno = EINVAL; 2147 return -rte_errno; 2148 } 2149 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2150 if (ret) { 2151 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2152 rte_errno = errno; 2153 return -rte_errno; 2154 } 2155 return ret; 2156 } 2157 2158 struct mlx5_devx_obj * 2159 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2160 { 2161 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2162 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2163 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2164 sizeof(*couners_obj), 0, 2165 SOCKET_ID_ANY); 2166 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2167 2168 if (!couners_obj) { 2169 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2170 rte_errno = ENOMEM; 2171 return NULL; 2172 } 2173 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2174 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2175 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2176 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2177 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2178 sizeof(out)); 2179 if (!couners_obj->obj) { 2180 rte_errno = errno; 2181 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 2182 " DevX."); 2183 mlx5_free(couners_obj); 2184 return NULL; 2185 } 2186 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2187 return couners_obj; 2188 } 2189 2190 int 2191 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2192 struct mlx5_devx_virtio_q_couners_attr *attr) 2193 { 2194 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2195 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2196 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2197 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2198 virtio_q_counters); 2199 int ret; 2200 2201 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2202 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2203 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2204 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2205 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2206 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2207 sizeof(out)); 2208 if (ret) { 2209 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2210 rte_errno = errno; 2211 return -errno; 2212 } 2213 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2214 received_desc); 2215 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2216 completed_desc); 2217 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2218 error_cqes); 2219 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2220 bad_desc_errors); 2221 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2222 exceed_max_chain); 2223 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2224 invalid_buffer); 2225 return ret; 2226 } 2227 2228 /** 2229 * Create general object of type FLOW_HIT_ASO using DevX API. 2230 * 2231 * @param[in] ctx 2232 * Context returned from mlx5 open_device() glue function. 2233 * @param [in] pd 2234 * PD value to associate the FLOW_HIT_ASO object with. 2235 * 2236 * @return 2237 * The DevX object created, NULL otherwise and rte_errno is set. 2238 */ 2239 struct mlx5_devx_obj * 2240 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2241 { 2242 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2243 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2244 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2245 void *ptr = NULL; 2246 2247 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2248 0, SOCKET_ID_ANY); 2249 if (!flow_hit_aso_obj) { 2250 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2251 rte_errno = ENOMEM; 2252 return NULL; 2253 } 2254 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2255 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2256 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2257 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2258 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2259 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2260 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2261 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2262 out, sizeof(out)); 2263 if (!flow_hit_aso_obj->obj) { 2264 rte_errno = errno; 2265 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2266 mlx5_free(flow_hit_aso_obj); 2267 return NULL; 2268 } 2269 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2270 return flow_hit_aso_obj; 2271 } 2272 2273 /* 2274 * Create PD using DevX API. 2275 * 2276 * @param[in] ctx 2277 * Context returned from mlx5 open_device() glue function. 2278 * 2279 * @return 2280 * The DevX object created, NULL otherwise and rte_errno is set. 2281 */ 2282 struct mlx5_devx_obj * 2283 mlx5_devx_cmd_alloc_pd(void *ctx) 2284 { 2285 struct mlx5_devx_obj *ppd = 2286 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2287 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2288 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2289 2290 if (!ppd) { 2291 DRV_LOG(ERR, "Failed to allocate PD data."); 2292 rte_errno = ENOMEM; 2293 return NULL; 2294 } 2295 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2296 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2297 out, sizeof(out)); 2298 if (!ppd->obj) { 2299 mlx5_free(ppd); 2300 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2301 rte_errno = errno; 2302 return NULL; 2303 } 2304 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2305 return ppd; 2306 } 2307 2308 /** 2309 * Create general object of type FLOW_METER_ASO using DevX API. 2310 * 2311 * @param[in] ctx 2312 * Context returned from mlx5 open_device() glue function. 2313 * @param [in] pd 2314 * PD value to associate the FLOW_METER_ASO object with. 2315 * @param [in] log_obj_size 2316 * log_obj_size define to allocate number of 2 * meters 2317 * in one FLOW_METER_ASO object. 2318 * 2319 * @return 2320 * The DevX object created, NULL otherwise and rte_errno is set. 2321 */ 2322 struct mlx5_devx_obj * 2323 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2324 uint32_t log_obj_size) 2325 { 2326 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2327 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2328 struct mlx5_devx_obj *flow_meter_aso_obj; 2329 void *ptr; 2330 2331 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2332 sizeof(*flow_meter_aso_obj), 2333 0, SOCKET_ID_ANY); 2334 if (!flow_meter_aso_obj) { 2335 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2336 rte_errno = ENOMEM; 2337 return NULL; 2338 } 2339 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2340 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2341 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2342 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2343 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2344 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2345 log_obj_size); 2346 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2347 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2348 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2349 ctx, in, sizeof(in), 2350 out, sizeof(out)); 2351 if (!flow_meter_aso_obj->obj) { 2352 rte_errno = errno; 2353 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX."); 2354 mlx5_free(flow_meter_aso_obj); 2355 return NULL; 2356 } 2357 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2358 out, obj_id); 2359 return flow_meter_aso_obj; 2360 } 2361 2362 /* 2363 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2364 * 2365 * @param[in] ctx 2366 * Context returned from mlx5 open_device() glue function. 2367 * @param [in] pd 2368 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2369 * @param [in] log_obj_size 2370 * log_obj_size to allocate its power of 2 * objects 2371 * in one CONN_TRACK_OFFLOAD bulk allocation. 2372 * 2373 * @return 2374 * The DevX object created, NULL otherwise and rte_errno is set. 2375 */ 2376 struct mlx5_devx_obj * 2377 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2378 uint32_t log_obj_size) 2379 { 2380 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2381 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2382 struct mlx5_devx_obj *ct_aso_obj; 2383 void *ptr; 2384 2385 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2386 0, SOCKET_ID_ANY); 2387 if (!ct_aso_obj) { 2388 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2389 rte_errno = ENOMEM; 2390 return NULL; 2391 } 2392 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2393 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2394 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2395 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2396 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2397 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2398 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2399 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2400 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2401 out, sizeof(out)); 2402 if (!ct_aso_obj->obj) { 2403 rte_errno = errno; 2404 DRV_LOG(ERR, "Failed to create CONN_TRACK_OFFLOAD obj by using DevX."); 2405 mlx5_free(ct_aso_obj); 2406 return NULL; 2407 } 2408 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2409 return ct_aso_obj; 2410 } 2411 2412 /** 2413 * Create general object of type GENEVE TLV option using DevX API. 2414 * 2415 * @param[in] ctx 2416 * Context returned from mlx5 open_device() glue function. 2417 * @param [in] class 2418 * TLV option variable value of class 2419 * @param [in] type 2420 * TLV option variable value of type 2421 * @param [in] len 2422 * TLV option variable value of len 2423 * 2424 * @return 2425 * The DevX object created, NULL otherwise and rte_errno is set. 2426 */ 2427 struct mlx5_devx_obj * 2428 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2429 uint16_t class, uint8_t type, uint8_t len) 2430 { 2431 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2432 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2433 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2434 sizeof(*geneve_tlv_opt_obj), 2435 0, SOCKET_ID_ANY); 2436 2437 if (!geneve_tlv_opt_obj) { 2438 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2439 rte_errno = ENOMEM; 2440 return NULL; 2441 } 2442 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2443 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2444 geneve_tlv_opt); 2445 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2446 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2447 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2448 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2449 MLX5_SET(geneve_tlv_option, opt, option_class, 2450 rte_be_to_cpu_16(class)); 2451 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2452 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2453 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2454 sizeof(in), out, sizeof(out)); 2455 if (!geneve_tlv_opt_obj->obj) { 2456 rte_errno = errno; 2457 DRV_LOG(ERR, "Failed to create Geneve tlv option " 2458 "Obj using DevX."); 2459 mlx5_free(geneve_tlv_opt_obj); 2460 return NULL; 2461 } 2462 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2463 return geneve_tlv_opt_obj; 2464 } 2465 2466 int 2467 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2468 { 2469 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2470 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2471 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2472 int rc; 2473 void *rq_ctx; 2474 2475 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2476 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2477 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2478 if (rc) { 2479 rte_errno = errno; 2480 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2481 "rc = %d, errno = %d.", rc, errno); 2482 return -rc; 2483 }; 2484 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2485 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2486 return 0; 2487 #else 2488 (void)wq; 2489 (void)counter_set_id; 2490 return -ENOTSUP; 2491 #endif 2492 } 2493 2494 /* 2495 * Allocate queue counters via devx interface. 2496 * 2497 * @param[in] ctx 2498 * Context returned from mlx5 open_device() glue function. 2499 * 2500 * @return 2501 * Pointer to counter object on success, a NULL value otherwise and 2502 * rte_errno is set. 2503 */ 2504 struct mlx5_devx_obj * 2505 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2506 { 2507 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2508 SOCKET_ID_ANY); 2509 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2510 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2511 2512 if (!dcs) { 2513 rte_errno = ENOMEM; 2514 return NULL; 2515 } 2516 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2517 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2518 sizeof(out)); 2519 if (!dcs->obj) { 2520 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error " 2521 "%d.", errno); 2522 rte_errno = errno; 2523 mlx5_free(dcs); 2524 return NULL; 2525 } 2526 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2527 return dcs; 2528 } 2529 2530 /** 2531 * Query queue counters values. 2532 * 2533 * @param[in] dcs 2534 * devx object of the queue counter set. 2535 * @param[in] clear 2536 * Whether hardware should clear the counters after the query or not. 2537 * @param[out] out_of_buffers 2538 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2539 * 2540 * @return 2541 * 0 on success, a negative value otherwise. 2542 */ 2543 int 2544 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2545 uint32_t *out_of_buffers) 2546 { 2547 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2548 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2549 int rc; 2550 2551 MLX5_SET(query_q_counter_in, in, opcode, 2552 MLX5_CMD_OP_QUERY_Q_COUNTER); 2553 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2554 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2555 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2556 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2557 sizeof(out)); 2558 if (rc) { 2559 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2560 rte_errno = rc; 2561 return -rc; 2562 } 2563 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2564 return 0; 2565 } 2566 2567 /** 2568 * Create general object of type DEK using DevX API. 2569 * 2570 * @param[in] ctx 2571 * Context returned from mlx5 open_device() glue function. 2572 * @param [in] attr 2573 * Pointer to DEK attributes structure. 2574 * 2575 * @return 2576 * The DevX object created, NULL otherwise and rte_errno is set. 2577 */ 2578 struct mlx5_devx_obj * 2579 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2580 { 2581 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2582 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2583 struct mlx5_devx_obj *dek_obj = NULL; 2584 void *ptr = NULL, *key_addr = NULL; 2585 2586 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2587 0, SOCKET_ID_ANY); 2588 if (dek_obj == NULL) { 2589 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2590 rte_errno = ENOMEM; 2591 return NULL; 2592 } 2593 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2594 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2595 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2596 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2597 MLX5_GENERAL_OBJ_TYPE_DEK); 2598 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2599 MLX5_SET(dek, ptr, key_size, attr->key_size); 2600 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2601 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2602 MLX5_SET(dek, ptr, pd, attr->pd); 2603 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2604 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2605 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2606 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2607 out, sizeof(out)); 2608 if (dek_obj->obj == NULL) { 2609 rte_errno = errno; 2610 DRV_LOG(ERR, "Failed to create DEK obj using DevX."); 2611 mlx5_free(dek_obj); 2612 return NULL; 2613 } 2614 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2615 return dek_obj; 2616 } 2617 2618 /** 2619 * Create general object of type IMPORT_KEK using DevX API. 2620 * 2621 * @param[in] ctx 2622 * Context returned from mlx5 open_device() glue function. 2623 * @param [in] attr 2624 * Pointer to IMPORT_KEK attributes structure. 2625 * 2626 * @return 2627 * The DevX object created, NULL otherwise and rte_errno is set. 2628 */ 2629 struct mlx5_devx_obj * 2630 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2631 struct mlx5_devx_import_kek_attr *attr) 2632 { 2633 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2634 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2635 struct mlx5_devx_obj *import_kek_obj = NULL; 2636 void *ptr = NULL, *key_addr = NULL; 2637 2638 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2639 0, SOCKET_ID_ANY); 2640 if (import_kek_obj == NULL) { 2641 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2642 rte_errno = ENOMEM; 2643 return NULL; 2644 } 2645 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2646 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2647 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2648 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2649 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2650 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2651 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2652 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2653 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2654 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2655 out, sizeof(out)); 2656 if (import_kek_obj->obj == NULL) { 2657 rte_errno = errno; 2658 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX."); 2659 mlx5_free(import_kek_obj); 2660 return NULL; 2661 } 2662 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2663 return import_kek_obj; 2664 } 2665 2666 /** 2667 * Create general object of type CREDENTIAL using DevX API. 2668 * 2669 * @param[in] ctx 2670 * Context returned from mlx5 open_device() glue function. 2671 * @param [in] attr 2672 * Pointer to CREDENTIAL attributes structure. 2673 * 2674 * @return 2675 * The DevX object created, NULL otherwise and rte_errno is set. 2676 */ 2677 struct mlx5_devx_obj * 2678 mlx5_devx_cmd_create_credential_obj(void *ctx, 2679 struct mlx5_devx_credential_attr *attr) 2680 { 2681 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 2682 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2683 struct mlx5_devx_obj *credential_obj = NULL; 2684 void *ptr = NULL, *credential_addr = NULL; 2685 2686 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 2687 0, SOCKET_ID_ANY); 2688 if (credential_obj == NULL) { 2689 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 2690 rte_errno = ENOMEM; 2691 return NULL; 2692 } 2693 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 2694 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2695 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2696 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2697 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 2698 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 2699 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 2700 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 2701 memcpy(credential_addr, (void *)(attr->credential), 2702 MLX5_CRYPTO_CREDENTIAL_SIZE); 2703 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2704 out, sizeof(out)); 2705 if (credential_obj->obj == NULL) { 2706 rte_errno = errno; 2707 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX."); 2708 mlx5_free(credential_obj); 2709 return NULL; 2710 } 2711 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2712 return credential_obj; 2713 } 2714 2715 /** 2716 * Create general object of type CRYPTO_LOGIN using DevX API. 2717 * 2718 * @param[in] ctx 2719 * Context returned from mlx5 open_device() glue function. 2720 * @param [in] attr 2721 * Pointer to CRYPTO_LOGIN attributes structure. 2722 * 2723 * @return 2724 * The DevX object created, NULL otherwise and rte_errno is set. 2725 */ 2726 struct mlx5_devx_obj * 2727 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 2728 struct mlx5_devx_crypto_login_attr *attr) 2729 { 2730 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 2731 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2732 struct mlx5_devx_obj *crypto_login_obj = NULL; 2733 void *ptr = NULL, *credential_addr = NULL; 2734 2735 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 2736 0, SOCKET_ID_ANY); 2737 if (crypto_login_obj == NULL) { 2738 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 2739 rte_errno = ENOMEM; 2740 return NULL; 2741 } 2742 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 2743 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2744 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2745 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2746 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 2747 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 2748 MLX5_SET(crypto_login, ptr, credential_pointer, 2749 attr->credential_pointer); 2750 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 2751 attr->session_import_kek_ptr); 2752 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 2753 memcpy(credential_addr, (void *)(attr->credential), 2754 MLX5_CRYPTO_CREDENTIAL_SIZE); 2755 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2756 out, sizeof(out)); 2757 if (crypto_login_obj->obj == NULL) { 2758 rte_errno = errno; 2759 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX."); 2760 mlx5_free(crypto_login_obj); 2761 return NULL; 2762 } 2763 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2764 return crypto_login_obj; 2765 } 2766