1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /* FW writes status value to the OUT buffer at offset 00H */ 17 #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status) 18 /* FW writes syndrome value to the OUT buffer at offset 04H */ 19 #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome) 20 21 #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1)) 22 23 #define DEVX_DRV_LOG(level, out, reason, param, value) \ 24 do { \ 25 /* \ 26 * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \ 27 * do not expand correctly when the macro invoked when the `param` \ 28 * is `NULL`. \ 29 * Use `local_param` to avoid direct `NULL` expansion. \ 30 */ \ 31 const char *local_param = (const char *)param; \ 32 \ 33 rte_errno = errno; \ 34 if (!local_param) { \ 35 DRV_LOG(level, \ 36 "DevX %s failed errno=%d status=%#x syndrome=%#x", \ 37 (reason), errno, MLX5_FW_STATUS((out)), \ 38 MLX5_FW_SYNDROME((out))); \ 39 } else { \ 40 DRV_LOG(level, \ 41 "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\ 42 (reason), local_param, (value), errno, \ 43 MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \ 44 } \ 45 } while (0) 46 47 static void * 48 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 49 int *err, uint32_t flags) 50 { 51 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 52 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 53 int rc; 54 55 memset(in, 0, size_in); 56 memset(out, 0, size_out); 57 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 58 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 59 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 60 if (rc || MLX5_FW_STATUS(out)) { 61 DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1); 62 if (err) 63 *err = MLX5_DEVX_ERR_RC(rc); 64 return NULL; 65 } 66 if (err) 67 *err = 0; 68 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 69 } 70 71 /** 72 * Perform read access to the registers. Reads data from register 73 * and writes ones to the specified buffer. 74 * 75 * @param[in] ctx 76 * Context returned from mlx5 open_device() glue function. 77 * @param[in] reg_id 78 * Register identifier according to the PRM. 79 * @param[in] arg 80 * Register access auxiliary parameter according to the PRM. 81 * @param[out] data 82 * Pointer to the buffer to store read data. 83 * @param[in] dw_cnt 84 * Buffer size in double words. 85 * 86 * @return 87 * 0 on success, a negative value otherwise. 88 */ 89 int 90 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 91 uint32_t *data, uint32_t dw_cnt) 92 { 93 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 94 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 95 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 96 int rc; 97 98 MLX5_ASSERT(data && dw_cnt); 99 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 100 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 101 DRV_LOG(ERR, "Not enough buffer for register read data"); 102 return -1; 103 } 104 MLX5_SET(access_register_in, in, opcode, 105 MLX5_CMD_OP_ACCESS_REGISTER_USER); 106 MLX5_SET(access_register_in, in, op_mod, 107 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 108 MLX5_SET(access_register_in, in, register_id, reg_id); 109 MLX5_SET(access_register_in, in, argument, arg); 110 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 111 MLX5_ST_SZ_BYTES(access_register_out) + 112 sizeof(uint32_t) * dw_cnt); 113 if (rc || MLX5_FW_STATUS(out)) { 114 DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id); 115 return MLX5_DEVX_ERR_RC(rc); 116 } 117 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 118 dw_cnt * sizeof(uint32_t)); 119 return 0; 120 } 121 122 /** 123 * Perform write access to the registers. 124 * 125 * @param[in] ctx 126 * Context returned from mlx5 open_device() glue function. 127 * @param[in] reg_id 128 * Register identifier according to the PRM. 129 * @param[in] arg 130 * Register access auxiliary parameter according to the PRM. 131 * @param[out] data 132 * Pointer to the buffer containing data to write. 133 * @param[in] dw_cnt 134 * Buffer size in double words (32bit units). 135 * 136 * @return 137 * 0 on success, a negative value otherwise. 138 */ 139 int 140 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 141 uint32_t *data, uint32_t dw_cnt) 142 { 143 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 144 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 145 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 146 int rc; 147 void *ptr; 148 149 MLX5_ASSERT(data && dw_cnt); 150 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 151 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 152 DRV_LOG(ERR, "Data to write exceeds max size"); 153 return -1; 154 } 155 MLX5_SET(access_register_in, in, opcode, 156 MLX5_CMD_OP_ACCESS_REGISTER_USER); 157 MLX5_SET(access_register_in, in, op_mod, 158 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 159 MLX5_SET(access_register_in, in, register_id, reg_id); 160 MLX5_SET(access_register_in, in, argument, arg); 161 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 162 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 163 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 164 if (rc || MLX5_FW_STATUS(out)) { 165 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 166 return MLX5_DEVX_ERR_RC(rc); 167 } 168 rc = mlx5_glue->devx_general_cmd(ctx, in, 169 MLX5_ST_SZ_BYTES(access_register_in) + 170 dw_cnt * sizeof(uint32_t), 171 out, sizeof(out)); 172 if (rc || MLX5_FW_STATUS(out)) { 173 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 174 return MLX5_DEVX_ERR_RC(rc); 175 } 176 return 0; 177 } 178 179 struct mlx5_devx_obj * 180 mlx5_devx_cmd_flow_counter_alloc_general(void *ctx, 181 struct mlx5_devx_counter_attr *attr) 182 { 183 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 184 0, SOCKET_ID_ANY); 185 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 186 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 187 188 if (!dcs) { 189 rte_errno = ENOMEM; 190 return NULL; 191 } 192 MLX5_SET(alloc_flow_counter_in, in, opcode, 193 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 194 if (attr->bulk_log_max_alloc) 195 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk_log_size, 196 attr->flow_counter_bulk_log_size); 197 else 198 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, 199 attr->bulk_n_128); 200 if (attr->pd_valid) 201 MLX5_SET(alloc_flow_counter_in, in, pd, attr->pd); 202 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 203 sizeof(in), out, sizeof(out)); 204 if (!dcs->obj) { 205 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 206 rte_errno = errno; 207 mlx5_free(dcs); 208 return NULL; 209 } 210 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 211 return dcs; 212 } 213 214 /** 215 * Allocate flow counters via devx interface. 216 * 217 * @param[in] ctx 218 * Context returned from mlx5 open_device() glue function. 219 * @param dcs 220 * Pointer to counters properties structure to be filled by the routine. 221 * @param bulk_n_128 222 * Bulk counter numbers in 128 counters units. 223 * 224 * @return 225 * Pointer to counter object on success, a negative value otherwise and 226 * rte_errno is set. 227 */ 228 struct mlx5_devx_obj * 229 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 230 { 231 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 232 0, SOCKET_ID_ANY); 233 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 234 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 235 236 if (!dcs) { 237 rte_errno = ENOMEM; 238 return NULL; 239 } 240 MLX5_SET(alloc_flow_counter_in, in, opcode, 241 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 242 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 243 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 244 sizeof(in), out, sizeof(out)); 245 if (!dcs->obj) { 246 DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0); 247 mlx5_free(dcs); 248 return NULL; 249 } 250 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 251 return dcs; 252 } 253 254 /** 255 * Query flow counters values. 256 * 257 * @param[in] dcs 258 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 259 * @param[in] clear 260 * Whether hardware should clear the counters after the query or not. 261 * @param[in] n_counters 262 * 0 in case of 1 counter to read, otherwise the counter number to read. 263 * @param pkts 264 * The number of packets that matched the flow. 265 * @param bytes 266 * The number of bytes that matched the flow. 267 * @param mkey 268 * The mkey key for batch query. 269 * @param addr 270 * The address in the mkey range for batch query. 271 * @param cmd_comp 272 * The completion object for asynchronous batch query. 273 * @param async_id 274 * The ID to be returned in the asynchronous batch query response. 275 * 276 * @return 277 * 0 on success, a negative value otherwise. 278 */ 279 int 280 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 281 int clear, uint32_t n_counters, 282 uint64_t *pkts, uint64_t *bytes, 283 uint32_t mkey, void *addr, 284 void *cmd_comp, 285 uint64_t async_id) 286 { 287 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 288 MLX5_ST_SZ_BYTES(traffic_counter); 289 uint32_t out[out_len]; 290 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 291 void *stats; 292 int rc; 293 294 MLX5_SET(query_flow_counter_in, in, opcode, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 296 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 297 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 298 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 299 300 if (n_counters) { 301 MLX5_SET(query_flow_counter_in, in, num_of_counters, 302 n_counters); 303 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 304 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 305 MLX5_SET64(query_flow_counter_in, in, address, 306 (uint64_t)(uintptr_t)addr); 307 } 308 if (!cmd_comp) 309 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 310 out_len); 311 else 312 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 313 out_len, async_id, 314 cmd_comp); 315 if (rc) { 316 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 317 rte_errno = rc; 318 return -rc; 319 } 320 if (!n_counters) { 321 stats = MLX5_ADDR_OF(query_flow_counter_out, 322 out, flow_statistics); 323 *pkts = MLX5_GET64(traffic_counter, stats, packets); 324 *bytes = MLX5_GET64(traffic_counter, stats, octets); 325 } 326 return 0; 327 } 328 329 /** 330 * Create a new mkey. 331 * 332 * @param[in] ctx 333 * Context returned from mlx5 open_device() glue function. 334 * @param[in] attr 335 * Attributes of the requested mkey. 336 * 337 * @return 338 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 339 * is set. 340 */ 341 struct mlx5_devx_obj * 342 mlx5_devx_cmd_mkey_create(void *ctx, 343 struct mlx5_devx_mkey_attr *attr) 344 { 345 struct mlx5_klm *klm_array = attr->klm_array; 346 int klm_num = attr->klm_num; 347 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 348 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 349 uint32_t in[in_size_dw]; 350 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 351 void *mkc; 352 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 353 0, SOCKET_ID_ANY); 354 size_t pgsize; 355 uint32_t translation_size; 356 357 if (!mkey) { 358 rte_errno = ENOMEM; 359 return NULL; 360 } 361 memset(in, 0, in_size_dw * 4); 362 pgsize = rte_mem_page_size(); 363 if (pgsize == (size_t)-1) { 364 mlx5_free(mkey); 365 DRV_LOG(ERR, "Failed to get page size"); 366 rte_errno = ENOMEM; 367 return NULL; 368 } 369 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 370 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 371 if (klm_num > 0) { 372 int i; 373 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 374 klm_pas_mtt); 375 translation_size = RTE_ALIGN(klm_num, 4); 376 for (i = 0; i < klm_num; i++) { 377 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 378 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 379 MLX5_SET64(klm, klm, address, klm_array[i].address); 380 klm += MLX5_ST_SZ_BYTES(klm); 381 } 382 for (; i < (int)translation_size; i++) { 383 MLX5_SET(klm, klm, mkey, 0x0); 384 MLX5_SET64(klm, klm, address, 0x0); 385 klm += MLX5_ST_SZ_BYTES(klm); 386 } 387 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 388 MLX5_MKC_ACCESS_MODE_KLM_FBS : 389 MLX5_MKC_ACCESS_MODE_KLM); 390 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 391 } else { 392 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 393 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 394 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 395 } 396 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 397 translation_size); 398 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 399 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 400 MLX5_SET(mkc, mkc, lw, 0x1); 401 MLX5_SET(mkc, mkc, lr, 0x1); 402 if (attr->set_remote_rw) { 403 MLX5_SET(mkc, mkc, rw, 0x1); 404 MLX5_SET(mkc, mkc, rr, 0x1); 405 } 406 MLX5_SET(mkc, mkc, qpn, 0xffffff); 407 MLX5_SET(mkc, mkc, pd, attr->pd); 408 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 409 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 410 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 411 MLX5_SET(mkc, mkc, relaxed_ordering_write, 412 attr->relaxed_ordering_write); 413 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 414 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 415 MLX5_SET64(mkc, mkc, len, attr->size); 416 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 417 if (attr->crypto_en) { 418 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 419 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 420 } 421 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 422 sizeof(out)); 423 if (!mkey->obj) { 424 DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey" 425 : "create direct key", NULL, 0); 426 mlx5_free(mkey); 427 return NULL; 428 } 429 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 430 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 431 return mkey; 432 } 433 434 /** 435 * Get status of devx command response. 436 * Mainly used for asynchronous commands. 437 * 438 * @param[in] out 439 * The out response buffer. 440 * 441 * @return 442 * 0 on success, non-zero value otherwise. 443 */ 444 int 445 mlx5_devx_get_out_command_status(void *out) 446 { 447 int status; 448 449 if (!out) 450 return -EINVAL; 451 status = MLX5_GET(query_flow_counter_out, out, status); 452 if (status) { 453 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 454 455 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 456 syndrome); 457 } 458 return status; 459 } 460 461 /** 462 * Destroy any object allocated by a Devx API. 463 * 464 * @param[in] obj 465 * Pointer to a general object. 466 * 467 * @return 468 * 0 on success, a negative value otherwise. 469 */ 470 int 471 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 472 { 473 int ret; 474 475 if (!obj) 476 return 0; 477 ret = mlx5_glue->devx_obj_destroy(obj->obj); 478 mlx5_free(obj); 479 return ret; 480 } 481 482 /** 483 * Query NIC vport context. 484 * Fills minimal inline attribute. 485 * 486 * @param[in] ctx 487 * ibv contexts returned from mlx5dv_open_device. 488 * @param[in] vport 489 * vport index 490 * @param[out] attr 491 * Attributes device values. 492 * 493 * @return 494 * 0 on success, a negative value otherwise. 495 */ 496 static int 497 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 498 unsigned int vport, 499 struct mlx5_hca_attr *attr) 500 { 501 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 502 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 503 void *vctx; 504 int rc; 505 506 /* Query NIC vport context to determine inline mode. */ 507 MLX5_SET(query_nic_vport_context_in, in, opcode, 508 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 509 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 510 if (vport) 511 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 512 rc = mlx5_glue->devx_general_cmd(ctx, 513 in, sizeof(in), 514 out, sizeof(out)); 515 if (rc || MLX5_FW_STATUS(out)) { 516 DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0); 517 return MLX5_DEVX_ERR_RC(rc); 518 } 519 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 520 nic_vport_context); 521 if (attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) 522 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 523 min_wqe_inline_mode); 524 attr->system_image_guid = MLX5_GET64(nic_vport_context, vctx, 525 system_image_guid); 526 return 0; 527 } 528 529 /** 530 * Query NIC vDPA attributes. 531 * 532 * @param[in] ctx 533 * Context returned from mlx5 open_device() glue function. 534 * @param[out] vdpa_attr 535 * vDPA Attributes structure to fill. 536 */ 537 static void 538 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 539 struct mlx5_hca_vdpa_attr *vdpa_attr) 540 { 541 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 542 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 543 void *hcattr; 544 545 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 546 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 547 MLX5_HCA_CAP_OPMOD_GET_CUR); 548 if (!hcattr) { 549 DRV_LOG(DEBUG, "Failed to query devx VDPA capabilities"); 550 vdpa_attr->valid = 0; 551 } else { 552 vdpa_attr->valid = 1; 553 vdpa_attr->desc_tunnel_offload_type = 554 MLX5_GET(virtio_emulation_cap, hcattr, 555 desc_tunnel_offload_type); 556 vdpa_attr->eth_frame_offload_type = 557 MLX5_GET(virtio_emulation_cap, hcattr, 558 eth_frame_offload_type); 559 vdpa_attr->virtio_version_1_0 = 560 MLX5_GET(virtio_emulation_cap, hcattr, 561 virtio_version_1_0); 562 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 563 tso_ipv4); 564 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 565 tso_ipv6); 566 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 567 tx_csum); 568 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 569 rx_csum); 570 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 571 event_mode); 572 vdpa_attr->virtio_queue_type = 573 MLX5_GET(virtio_emulation_cap, hcattr, 574 virtio_queue_type); 575 vdpa_attr->log_doorbell_stride = 576 MLX5_GET(virtio_emulation_cap, hcattr, 577 log_doorbell_stride); 578 vdpa_attr->vnet_modify_ext = 579 MLX5_GET(virtio_emulation_cap, hcattr, 580 vnet_modify_ext); 581 vdpa_attr->virtio_net_q_addr_modify = 582 MLX5_GET(virtio_emulation_cap, hcattr, 583 virtio_net_q_addr_modify); 584 vdpa_attr->virtio_q_index_modify = 585 MLX5_GET(virtio_emulation_cap, hcattr, 586 virtio_q_index_modify); 587 vdpa_attr->log_doorbell_bar_size = 588 MLX5_GET(virtio_emulation_cap, hcattr, 589 log_doorbell_bar_size); 590 vdpa_attr->doorbell_bar_offset = 591 MLX5_GET64(virtio_emulation_cap, hcattr, 592 doorbell_bar_offset); 593 vdpa_attr->max_num_virtio_queues = 594 MLX5_GET(virtio_emulation_cap, hcattr, 595 max_num_virtio_queues); 596 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 597 umem_1_buffer_param_a); 598 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 599 umem_1_buffer_param_b); 600 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 601 umem_2_buffer_param_a); 602 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 603 umem_2_buffer_param_b); 604 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 605 umem_3_buffer_param_a); 606 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 607 umem_3_buffer_param_b); 608 } 609 } 610 611 /** 612 * Query match sample handle parameters. 613 * 614 * This command allows translating a field sample handle returned by either 615 * PARSE_GRAPH_FLOW_MATCH_SAMPLE or by GENEVE TLV OPTION object into values 616 * used for header modification or header matching/hashing. 617 * 618 * @param[in] ctx 619 * Context used to create either GENEVE TLV option or FLEX PARSE GRAPH object. 620 * @param[in] sample_field_id 621 * Field sample handle returned by either PARSE_GRAPH_FLOW_MATCH_SAMPLE 622 * or by GENEVE TLV OPTION object. 623 * @param[out] attr 624 * Pointer to match sample info attributes structure. 625 * 626 * @return 627 * 0 on success, a negative errno otherwise and rte_errno is set. 628 */ 629 int 630 mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id, 631 struct mlx5_devx_match_sample_info_query_attr *attr) 632 { 633 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 634 uint32_t out[MLX5_ST_SZ_DW(query_match_sample_info_out)] = {0}; 635 uint32_t in[MLX5_ST_SZ_DW(query_match_sample_info_in)] = {0}; 636 int rc; 637 638 MLX5_SET(query_match_sample_info_in, in, opcode, 639 MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO); 640 MLX5_SET(query_match_sample_info_in, in, op_mod, 0); 641 MLX5_SET(query_match_sample_info_in, in, sample_field_id, 642 sample_field_id); 643 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 644 if (rc || MLX5_FW_STATUS(out)) { 645 DEVX_DRV_LOG(ERR, out, "query match sample info", 646 "sample_field_id", sample_field_id); 647 return MLX5_DEVX_ERR_RC(rc); 648 } 649 attr->modify_field_id = MLX5_GET(query_match_sample_info_out, out, 650 modify_field_id); 651 attr->sample_dw_data = MLX5_GET(query_match_sample_info_out, out, 652 field_format_select_dw); 653 attr->sample_dw_ok_bit = MLX5_GET(query_match_sample_info_out, out, 654 ok_bit_format_select_dw); 655 attr->sample_dw_ok_bit_offset = MLX5_GET(query_match_sample_info_out, 656 out, ok_bit_offset); 657 return 0; 658 #else 659 (void)ctx; 660 (void)sample_field_id; 661 (void)attr; 662 return -ENOTSUP; 663 #endif 664 } 665 666 int 667 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 668 uint32_t *ids, 669 uint32_t num, uint8_t *anchor) 670 { 671 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 672 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 673 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 674 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 675 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 676 int ret; 677 uint32_t idx = 0; 678 uint32_t i; 679 680 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 681 rte_errno = EINVAL; 682 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 683 return -rte_errno; 684 } 685 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 686 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 687 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 688 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 689 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 690 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 691 out, sizeof(out)); 692 if (ret) { 693 rte_errno = ret; 694 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 695 (void *)flex_obj); 696 return -rte_errno; 697 } 698 if (anchor) 699 *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); 700 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx < num; i++) { 701 void *s_off = (void *)((char *)sample + i * 702 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 703 uint32_t en; 704 705 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 706 flow_match_sample_en); 707 if (!en) 708 continue; 709 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 710 flow_match_sample_field_id); 711 } 712 if (num != idx) { 713 rte_errno = EINVAL; 714 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 715 return -rte_errno; 716 } 717 return ret; 718 } 719 720 struct mlx5_devx_obj * 721 mlx5_devx_cmd_create_flex_parser(void *ctx, 722 struct mlx5_devx_graph_node_attr *data) 723 { 724 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 725 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 726 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 727 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 728 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 729 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 730 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 731 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 732 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 733 uint32_t i; 734 735 if (!parse_flex_obj) { 736 DRV_LOG(ERR, "Failed to allocate flex parser data."); 737 rte_errno = ENOMEM; 738 return NULL; 739 } 740 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 741 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 742 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 743 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 744 MLX5_SET(parse_graph_flex, flex, header_length_mode, 745 data->header_length_mode); 746 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 747 data->modify_field_select); 748 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 749 data->header_length_base_value); 750 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 751 data->header_length_field_offset); 752 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 753 data->header_length_field_shift); 754 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 755 data->next_header_field_offset); 756 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 757 data->next_header_field_size); 758 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 759 data->header_length_field_mask); 760 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 761 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 762 void *s_off = (void *)((char *)sample + i * 763 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 764 765 if (!s->flow_match_sample_en) 766 continue; 767 MLX5_SET(parse_graph_flow_match_sample, s_off, 768 flow_match_sample_en, !!s->flow_match_sample_en); 769 MLX5_SET(parse_graph_flow_match_sample, s_off, 770 flow_match_sample_field_offset, 771 s->flow_match_sample_field_offset); 772 MLX5_SET(parse_graph_flow_match_sample, s_off, 773 flow_match_sample_offset_mode, 774 s->flow_match_sample_offset_mode); 775 MLX5_SET(parse_graph_flow_match_sample, s_off, 776 flow_match_sample_field_offset_mask, 777 s->flow_match_sample_field_offset_mask); 778 MLX5_SET(parse_graph_flow_match_sample, s_off, 779 flow_match_sample_field_offset_shift, 780 s->flow_match_sample_field_offset_shift); 781 MLX5_SET(parse_graph_flow_match_sample, s_off, 782 flow_match_sample_field_base_offset, 783 s->flow_match_sample_field_base_offset); 784 MLX5_SET(parse_graph_flow_match_sample, s_off, 785 flow_match_sample_tunnel_mode, 786 s->flow_match_sample_tunnel_mode); 787 } 788 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 789 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 790 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 791 void *in_off = (void *)((char *)in_arc + i * 792 MLX5_ST_SZ_BYTES(parse_graph_arc)); 793 void *out_off = (void *)((char *)out_arc + i * 794 MLX5_ST_SZ_BYTES(parse_graph_arc)); 795 796 if (ia->arc_parse_graph_node != 0) { 797 MLX5_SET(parse_graph_arc, in_off, 798 compare_condition_value, 799 ia->compare_condition_value); 800 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 801 ia->start_inner_tunnel); 802 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 803 ia->arc_parse_graph_node); 804 MLX5_SET(parse_graph_arc, in_off, 805 parse_graph_node_handle, 806 ia->parse_graph_node_handle); 807 } 808 if (oa->arc_parse_graph_node != 0) { 809 MLX5_SET(parse_graph_arc, out_off, 810 compare_condition_value, 811 oa->compare_condition_value); 812 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 813 oa->start_inner_tunnel); 814 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 815 oa->arc_parse_graph_node); 816 MLX5_SET(parse_graph_arc, out_off, 817 parse_graph_node_handle, 818 oa->parse_graph_node_handle); 819 } 820 } 821 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 822 out, sizeof(out)); 823 if (!parse_flex_obj->obj) { 824 DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0); 825 mlx5_free(parse_flex_obj); 826 return NULL; 827 } 828 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 829 return parse_flex_obj; 830 } 831 832 static int 833 mlx5_devx_cmd_query_hca_parse_graph_node_cap 834 (void *ctx, struct mlx5_hca_flex_attr *attr) 835 { 836 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 837 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 838 void *hcattr; 839 int rc; 840 841 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 842 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 843 MLX5_HCA_CAP_OPMOD_GET_CUR); 844 if (!hcattr) 845 return rc; 846 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 847 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 848 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 849 header_length_mode); 850 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 851 sample_offset_mode); 852 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 853 max_num_arc_in); 854 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 855 max_num_arc_out); 856 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 857 max_num_sample); 858 attr->parse_graph_anchor = MLX5_GET(parse_graph_node_cap, hcattr, parse_graph_anchor); 859 attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr, 860 sample_tunnel_inner2); 861 attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr, 862 zero_size_supported); 863 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 864 sample_id_in_out); 865 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 866 max_base_header_length); 867 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 868 max_sample_base_offset); 869 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 870 max_next_header_offset); 871 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 872 header_length_mask_width); 873 /* Get the max supported samples from HCA CAP 2 */ 874 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 875 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 876 MLX5_HCA_CAP_OPMOD_GET_CUR); 877 if (!hcattr) 878 return rc; 879 attr->max_num_prog_sample = 880 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 881 return 0; 882 } 883 884 static int 885 mlx5_devx_query_pkt_integrity_match(void *hcattr) 886 { 887 return MLX5_GET(flow_table_nic_cap, hcattr, 888 ft_field_support_2_nic_receive.inner_l3_ok) && 889 MLX5_GET(flow_table_nic_cap, hcattr, 890 ft_field_support_2_nic_receive.inner_l4_ok) && 891 MLX5_GET(flow_table_nic_cap, hcattr, 892 ft_field_support_2_nic_receive.outer_l3_ok) && 893 MLX5_GET(flow_table_nic_cap, hcattr, 894 ft_field_support_2_nic_receive.outer_l4_ok) && 895 MLX5_GET(flow_table_nic_cap, hcattr, 896 ft_field_support_2_nic_receive 897 .inner_ipv4_checksum_ok) && 898 MLX5_GET(flow_table_nic_cap, hcattr, 899 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 900 MLX5_GET(flow_table_nic_cap, hcattr, 901 ft_field_support_2_nic_receive 902 .outer_ipv4_checksum_ok) && 903 MLX5_GET(flow_table_nic_cap, hcattr, 904 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 905 } 906 907 /** 908 * Query HCA attributes. 909 * Using those attributes we can check on run time if the device 910 * is having the required capabilities. 911 * 912 * @param[in] ctx 913 * Context returned from mlx5 open_device() glue function. 914 * @param[out] attr 915 * Attributes device values. 916 * 917 * @return 918 * 0 on success, a negative value otherwise. 919 */ 920 int 921 mlx5_devx_cmd_query_hca_attr(void *ctx, 922 struct mlx5_hca_attr *attr) 923 { 924 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 925 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 926 bool hca_cap_2_sup; 927 uint64_t general_obj_types_supported = 0; 928 void *hcattr; 929 int rc, i; 930 931 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 932 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 933 MLX5_HCA_CAP_OPMOD_GET_CUR); 934 if (!hcattr) 935 return rc; 936 hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); 937 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); 938 attr->flow_counter_bulk_alloc_bitmap = 939 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 940 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 941 flow_counters_dump); 942 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 943 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 944 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 945 log_max_rqt_size); 946 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 947 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 948 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 949 log_max_hairpin_queues); 950 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 951 log_max_hairpin_wq_data_sz); 952 attr->log_max_hairpin_num_packets = MLX5_GET 953 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 954 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 955 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 956 relaxed_ordering_write); 957 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 958 relaxed_ordering_read); 959 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 960 access_register_user); 961 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 962 eth_net_offloads); 963 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 964 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 965 flex_parser_protocols); 966 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 967 max_geneve_tlv_options); 968 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 969 max_geneve_tlv_option_data_len); 970 attr->geneve_tlv_option_offset = MLX5_GET(cmd_hca_cap, hcattr, 971 geneve_tlv_option_offset); 972 attr->geneve_tlv_sample = MLX5_GET(cmd_hca_cap, hcattr, 973 geneve_tlv_sample); 974 attr->query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr, 975 query_match_sample_info); 976 attr->geneve_tlv_option_sample_id = MLX5_GET(cmd_hca_cap, hcattr, 977 flex_parser_id_geneve_opt_0); 978 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 979 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 980 wqe_index_ignore_cap); 981 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 982 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 983 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 984 log_max_static_sq_wq); 985 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 986 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 987 device_frequency_khz); 988 attr->scatter_fcs_w_decap_disable = 989 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 990 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 991 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 992 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 993 attr->steering_format_version = 994 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 995 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 996 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 997 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 998 regexp_num_of_engines); 999 /* Read the general_obj_types bitmap and extract the relevant bits. */ 1000 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 1001 general_obj_types); 1002 attr->qos.flow_meter_aso_sup = 1003 !!(general_obj_types_supported & 1004 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 1005 attr->vdpa.valid = !!(general_obj_types_supported & 1006 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 1007 attr->vdpa.queue_counters_valid = 1008 !!(general_obj_types_supported & 1009 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 1010 attr->parse_graph_flex_node = 1011 !!(general_obj_types_supported & 1012 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 1013 attr->flow_hit_aso = !!(general_obj_types_supported & 1014 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 1015 attr->geneve_tlv_opt = !!(general_obj_types_supported & 1016 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 1017 attr->dek = !!(general_obj_types_supported & 1018 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 1019 attr->import_kek = !!(general_obj_types_supported & 1020 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 1021 attr->credential = !!(general_obj_types_supported & 1022 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 1023 attr->crypto_login = !!(general_obj_types_supported & 1024 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 1025 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 1026 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 1027 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 1028 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 1029 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 1030 attr->log_max_wq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_wq_sz); 1031 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 1032 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 1033 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 1034 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 1035 attr->reg_c_preserve = 1036 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 1037 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 1038 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 1039 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 1040 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 1041 compress_mmo_sq); 1042 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 1043 decompress_mmo_sq); 1044 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 1045 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 1046 compress_mmo_qp); 1047 attr->decomp_deflate_v1_en = MLX5_GET(cmd_hca_cap, hcattr, 1048 decompress_deflate_v1); 1049 attr->decomp_deflate_v2_en = MLX5_GET(cmd_hca_cap, hcattr, 1050 decompress_deflate_v2); 1051 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 1052 compress_min_block_size); 1053 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 1054 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 1055 log_compress_mmo_size); 1056 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 1057 log_decompress_mmo_size); 1058 attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr, 1059 decompress_lz4_data_only_v2); 1060 attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1061 decompress_lz4_no_checksum_v2); 1062 attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1063 decompress_lz4_checksum_v2); 1064 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 1065 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 1066 mini_cqe_resp_flow_tag); 1067 attr->cqe_compression_128 = MLX5_GET(cmd_hca_cap, hcattr, 1068 cqe_compression_128); 1069 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 1070 mini_cqe_resp_l3_l4_tag); 1071 attr->enhanced_cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, 1072 enhanced_cqe_compression); 1073 attr->umr_indirect_mkey_disabled = 1074 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 1075 attr->umr_modify_entity_size_disabled = 1076 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 1077 attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); 1078 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 1079 attr->ct_offload = !!(general_obj_types_supported & 1080 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 1081 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 1082 attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table); 1083 attr->striding_rq = MLX5_GET(cmd_hca_cap, hcattr, striding_rq); 1084 attr->ext_stride_num_range = 1085 MLX5_GET(cmd_hca_cap, hcattr, ext_stride_num_range); 1086 attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table); 1087 attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr, 1088 max_flow_counter_15_0); 1089 attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr, 1090 max_flow_counter_31_16); 1091 attr->alloc_flow_counter_pd = MLX5_GET(cmd_hca_cap, hcattr, 1092 alloc_flow_counter_pd); 1093 attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr, 1094 flow_counter_access_aso); 1095 attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr, 1096 flow_access_aso_opc_mod); 1097 attr->wqe_based_flow_table_sup = MLX5_GET(cmd_hca_cap, hcattr, 1098 wqe_based_flow_table_update_cap); 1099 /* 1100 * Flex item support needs max_num_prog_sample_field 1101 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1102 */ 1103 if (attr->parse_graph_flex_node) { 1104 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1105 (ctx, &attr->flex); 1106 if (rc) 1107 return -1; 1108 attr->flex.query_match_sample_info = 1109 attr->query_match_sample_info; 1110 } 1111 if (attr->crypto) { 1112 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) || 1113 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) || 1114 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_single_block_le_tweak); 1115 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1116 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO | 1117 MLX5_HCA_CAP_OPMOD_GET_CUR); 1118 if (!hcattr) 1119 return -1; 1120 attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps, 1121 hcattr, wrapped_import_method) 1122 & 1 << 2); 1123 attr->crypto_mmo.crypto_mmo_qp = MLX5_GET(crypto_caps, hcattr, crypto_mmo_qp); 1124 attr->crypto_mmo.gcm_256_encrypt = 1125 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_encrypt); 1126 attr->crypto_mmo.gcm_128_encrypt = 1127 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_encrypt); 1128 attr->crypto_mmo.gcm_256_decrypt = 1129 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_decrypt); 1130 attr->crypto_mmo.gcm_128_decrypt = 1131 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_decrypt); 1132 attr->crypto_mmo.gcm_auth_tag_128 = 1133 MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_128); 1134 attr->crypto_mmo.gcm_auth_tag_96 = 1135 MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_96); 1136 attr->crypto_mmo.log_crypto_mmo_max_size = 1137 MLX5_GET(crypto_caps, hcattr, log_crypto_mmo_max_size); 1138 } 1139 if (hca_cap_2_sup) { 1140 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1141 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 1142 MLX5_HCA_CAP_OPMOD_GET_CUR); 1143 if (!hcattr) { 1144 DRV_LOG(DEBUG, 1145 "Failed to query DevX HCA capabilities 2."); 1146 return rc; 1147 } 1148 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, 1149 log_min_stride_wqe_sz); 1150 attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr, 1151 hairpin_sq_wqe_bb_size); 1152 attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr, 1153 hairpin_sq_wq_in_host_mem); 1154 attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr, 1155 hairpin_data_buffer_locked); 1156 attr->flow_counter_bulk_log_max_alloc = MLX5_GET(cmd_hca_cap_2, 1157 hcattr, flow_counter_bulk_log_max_alloc); 1158 attr->flow_counter_bulk_log_granularity = 1159 MLX5_GET(cmd_hca_cap_2, hcattr, 1160 flow_counter_bulk_log_granularity); 1161 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1162 cross_vhca_object_to_object_supported); 1163 attr->cross_vhca = 1164 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR) && 1165 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT) && 1166 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT) && 1167 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC); 1168 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1169 allowed_object_for_other_vhca_access); 1170 attr->cross_vhca = attr->cross_vhca && 1171 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR) && 1172 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) && 1173 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC); 1174 if (attr->ct_offload) 1175 attr->log_max_conn_track_offload = MLX5_GET(cmd_hca_cap_2, hcattr, 1176 log_max_conn_track_offload); 1177 } 1178 if (attr->log_min_stride_wqe_sz == 0) 1179 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 1180 if (attr->qos.sup) { 1181 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1182 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 1183 MLX5_HCA_CAP_OPMOD_GET_CUR); 1184 if (!hcattr) { 1185 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 1186 return rc; 1187 } 1188 attr->qos.flow_meter_old = 1189 MLX5_GET(qos_cap, hcattr, flow_meter_old); 1190 attr->qos.log_max_flow_meter = 1191 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 1192 attr->qos.flow_meter_reg_c_ids = 1193 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 1194 attr->qos.flow_meter = 1195 MLX5_GET(qos_cap, hcattr, flow_meter); 1196 attr->qos.packet_pacing = 1197 MLX5_GET(qos_cap, hcattr, packet_pacing); 1198 attr->qos.wqe_rate_pp = 1199 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 1200 if (attr->qos.flow_meter_aso_sup) { 1201 attr->qos.log_meter_aso_granularity = 1202 MLX5_GET(qos_cap, hcattr, 1203 log_meter_aso_granularity); 1204 attr->qos.log_meter_aso_max_alloc = 1205 MLX5_GET(qos_cap, hcattr, 1206 log_meter_aso_max_alloc); 1207 attr->qos.log_max_num_meter_aso = 1208 MLX5_GET(qos_cap, hcattr, 1209 log_max_num_meter_aso); 1210 } 1211 } 1212 if (attr->vdpa.valid) 1213 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1214 if (!attr->eth_net_offloads) 1215 return 0; 1216 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1217 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1218 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1219 MLX5_HCA_CAP_OPMOD_GET_CUR); 1220 if (!hcattr) { 1221 attr->log_max_ft_sampler_num = 0; 1222 return rc; 1223 } 1224 attr->log_max_ft_sampler_num = MLX5_GET 1225 (flow_table_nic_cap, hcattr, 1226 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1227 attr->flow.tunnel_header_0_1 = MLX5_GET 1228 (flow_table_nic_cap, hcattr, 1229 ft_field_support_2_nic_receive.tunnel_header_0_1); 1230 attr->flow.tunnel_header_2_3 = MLX5_GET 1231 (flow_table_nic_cap, hcattr, 1232 ft_field_support_2_nic_receive.tunnel_header_2_3); 1233 attr->modify_outer_ip_ecn = MLX5_GET 1234 (flow_table_nic_cap, hcattr, 1235 ft_header_modify_nic_receive.outer_ip_ecn); 1236 attr->modify_outer_ipv6_traffic_class = MLX5_GET 1237 (flow_table_nic_cap, hcattr, 1238 ft_header_modify_nic_receive.outer_ipv6_traffic_class); 1239 attr->set_reg_c = 0xffff; 1240 if (attr->nic_flow_table) { 1241 #define GET_RX_REG_X_BITS \ 1242 MLX5_GET(flow_table_nic_cap, hcattr, \ 1243 ft_header_modify_nic_receive.metadata_reg_c_x) 1244 #define GET_TX_REG_X_BITS \ 1245 MLX5_GET(flow_table_nic_cap, hcattr, \ 1246 ft_header_modify_nic_transmit.metadata_reg_c_x) 1247 1248 uint32_t tx_reg, rx_reg, reg_c_8_15; 1249 1250 tx_reg = GET_TX_REG_X_BITS; 1251 reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr, 1252 ft_field_support_2_nic_transmit.metadata_reg_c_8_15); 1253 tx_reg |= ((0xff & reg_c_8_15) << 8); 1254 rx_reg = GET_RX_REG_X_BITS; 1255 reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr, 1256 ft_field_support_2_nic_receive.metadata_reg_c_8_15); 1257 rx_reg |= ((0xff & reg_c_8_15) << 8); 1258 attr->set_reg_c &= (rx_reg & tx_reg); 1259 1260 #undef GET_RX_REG_X_BITS 1261 #undef GET_TX_REG_X_BITS 1262 } 1263 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1264 attr->inner_ipv4_ihl = MLX5_GET 1265 (flow_table_nic_cap, hcattr, 1266 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1267 attr->outer_ipv4_ihl = MLX5_GET 1268 (flow_table_nic_cap, hcattr, 1269 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1270 attr->lag_rx_port_affinity = MLX5_GET 1271 (flow_table_nic_cap, hcattr, 1272 ft_field_support_2_nic_receive.lag_rx_port_affinity); 1273 /* Query HCA offloads for Ethernet protocol. */ 1274 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1275 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1276 MLX5_HCA_CAP_OPMOD_GET_CUR); 1277 if (!hcattr) { 1278 attr->eth_net_offloads = 0; 1279 return rc; 1280 } 1281 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1282 hcattr, wqe_vlan_insert); 1283 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1284 hcattr, csum_cap); 1285 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1286 hcattr, vlan_cap); 1287 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1288 lro_cap); 1289 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1290 hcattr, max_lso_cap); 1291 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1292 hcattr, scatter_fcs); 1293 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1294 hcattr, tunnel_lro_gre); 1295 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1296 hcattr, tunnel_lro_vxlan); 1297 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1298 hcattr, swp); 1299 attr->tunnel_stateless_gre = 1300 MLX5_GET(per_protocol_networking_offload_caps, 1301 hcattr, tunnel_stateless_gre); 1302 attr->tunnel_stateless_vxlan = 1303 MLX5_GET(per_protocol_networking_offload_caps, 1304 hcattr, tunnel_stateless_vxlan); 1305 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1306 hcattr, swp_csum); 1307 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1308 hcattr, swp_lso); 1309 attr->lro_max_msg_sz_mode = MLX5_GET 1310 (per_protocol_networking_offload_caps, 1311 hcattr, lro_max_msg_sz_mode); 1312 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1313 attr->lro_timer_supported_periods[i] = 1314 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1315 lro_timer_supported_periods[i]); 1316 } 1317 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1318 hcattr, lro_min_mss_size); 1319 attr->tunnel_stateless_geneve_rx = 1320 MLX5_GET(per_protocol_networking_offload_caps, 1321 hcattr, tunnel_stateless_geneve_rx); 1322 attr->geneve_max_opt_len = 1323 MLX5_GET(per_protocol_networking_offload_caps, 1324 hcattr, max_geneve_opt_len); 1325 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1326 hcattr, wqe_inline_mode); 1327 attr->tunnel_stateless_gtp = MLX5_GET 1328 (per_protocol_networking_offload_caps, 1329 hcattr, tunnel_stateless_gtp); 1330 attr->tunnel_stateless_vxlan_gpe_nsh = MLX5_GET 1331 (per_protocol_networking_offload_caps, 1332 hcattr, tunnel_stateless_vxlan_gpe_nsh); 1333 attr->rss_ind_tbl_cap = MLX5_GET 1334 (per_protocol_networking_offload_caps, 1335 hcattr, rss_ind_tbl_cap); 1336 attr->multi_pkt_send_wqe = MLX5_GET 1337 (per_protocol_networking_offload_caps, 1338 hcattr, multi_pkt_send_wqe); 1339 attr->enhanced_multi_pkt_send_wqe = MLX5_GET 1340 (per_protocol_networking_offload_caps, 1341 hcattr, enhanced_multi_pkt_send_wqe); 1342 if (attr->wqe_based_flow_table_sup) { 1343 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1344 MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE | 1345 MLX5_HCA_CAP_OPMOD_GET_CUR); 1346 if (!hcattr) { 1347 DRV_LOG(DEBUG, "Failed to query WQE Based Flow table capabilities"); 1348 return rc; 1349 } 1350 attr->max_header_modify_pattern_length = MLX5_GET(wqe_based_flow_table_cap, 1351 hcattr, 1352 max_header_modify_pattern_length); 1353 } 1354 /* Query HCA attribute for ROCE. */ 1355 if (attr->roce) { 1356 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1357 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1358 MLX5_HCA_CAP_OPMOD_GET_CUR); 1359 if (!hcattr) { 1360 DRV_LOG(DEBUG, 1361 "Failed to query devx HCA ROCE capabilities"); 1362 return rc; 1363 } 1364 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1365 } 1366 if (attr->eth_virt) { 1367 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1368 if (rc) { 1369 attr->eth_virt = 0; 1370 goto error; 1371 } 1372 } 1373 if (attr->eswitch_manager) { 1374 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1375 MLX5_SET_HCA_CAP_OP_MOD_ESW | 1376 MLX5_HCA_CAP_OPMOD_GET_CUR); 1377 if (!hcattr) 1378 return rc; 1379 attr->esw_mgr_vport_id_valid = 1380 MLX5_GET(esw_cap, hcattr, 1381 esw_manager_vport_number_valid); 1382 attr->esw_mgr_vport_id = 1383 MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); 1384 } 1385 if (attr->eswitch_manager) { 1386 uint32_t esw_reg, reg_c_8_15; 1387 1388 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1389 MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE | 1390 MLX5_HCA_CAP_OPMOD_GET_CUR); 1391 if (!hcattr) 1392 return rc; 1393 esw_reg = MLX5_GET(flow_table_esw_cap, hcattr, 1394 ft_header_modify_esw_fdb.metadata_reg_c_x); 1395 reg_c_8_15 = MLX5_GET(flow_table_esw_cap, hcattr, 1396 ft_field_support_2_esw_fdb.metadata_reg_c_8_15); 1397 attr->set_reg_c &= ((0xff & reg_c_8_15) << 8) | esw_reg; 1398 } 1399 return 0; 1400 error: 1401 rc = (rc > 0) ? -rc : rc; 1402 return rc; 1403 } 1404 1405 /** 1406 * Query TIS transport domain from QP verbs object using DevX API. 1407 * 1408 * @param[in] qp 1409 * Pointer to verbs QP returned by ibv_create_qp . 1410 * @param[in] tis_num 1411 * TIS number of TIS to query. 1412 * @param[out] tis_td 1413 * Pointer to TIS transport domain variable, to be set by the routine. 1414 * 1415 * @return 1416 * 0 on success, a negative value otherwise. 1417 */ 1418 int 1419 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1420 uint32_t *tis_td) 1421 { 1422 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1423 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1424 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1425 int rc; 1426 void *tis_ctx; 1427 1428 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1429 MLX5_SET(query_tis_in, in, tisn, tis_num); 1430 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1431 if (rc) { 1432 DRV_LOG(ERR, "Failed to query QP using DevX"); 1433 return -rc; 1434 }; 1435 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1436 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1437 return 0; 1438 #else 1439 (void)qp; 1440 (void)tis_num; 1441 (void)tis_td; 1442 return -ENOTSUP; 1443 #endif 1444 } 1445 1446 /** 1447 * Fill WQ data for DevX API command. 1448 * Utility function for use when creating DevX objects containing a WQ. 1449 * 1450 * @param[in] wq_ctx 1451 * Pointer to WQ context to fill with data. 1452 * @param [in] wq_attr 1453 * Pointer to WQ attributes structure to fill in WQ context. 1454 */ 1455 static void 1456 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1457 { 1458 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1459 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1460 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1461 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1462 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1463 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1464 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1465 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1466 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1467 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1468 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1469 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1470 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1471 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1472 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1473 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1474 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1475 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1476 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1477 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1478 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1479 wq_attr->log_hairpin_num_packets); 1480 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1481 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1482 wq_attr->single_wqe_log_num_of_strides); 1483 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1484 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1485 wq_attr->single_stride_log_num_of_bytes); 1486 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1487 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1488 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1489 } 1490 1491 /** 1492 * Create RQ using DevX API. 1493 * 1494 * @param[in] ctx 1495 * Context returned from mlx5 open_device() glue function. 1496 * @param [in] rq_attr 1497 * Pointer to create RQ attributes structure. 1498 * @param [in] socket 1499 * CPU socket ID for allocations. 1500 * 1501 * @return 1502 * The DevX object created, NULL otherwise and rte_errno is set. 1503 */ 1504 struct mlx5_devx_obj * 1505 mlx5_devx_cmd_create_rq(void *ctx, 1506 struct mlx5_devx_create_rq_attr *rq_attr, 1507 int socket) 1508 { 1509 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1510 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1511 void *rq_ctx, *wq_ctx; 1512 struct mlx5_devx_wq_attr *wq_attr; 1513 struct mlx5_devx_obj *rq = NULL; 1514 1515 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1516 if (!rq) { 1517 DRV_LOG(ERR, "Failed to allocate RQ data"); 1518 rte_errno = ENOMEM; 1519 return NULL; 1520 } 1521 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1522 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1523 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1524 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1525 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1526 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1527 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1528 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1529 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1530 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1531 MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type); 1532 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1533 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1534 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1535 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1536 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1537 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1538 wq_attr = &rq_attr->wq_attr; 1539 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1540 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1541 out, sizeof(out)); 1542 if (!rq->obj) { 1543 DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0); 1544 mlx5_free(rq); 1545 return NULL; 1546 } 1547 rq->id = MLX5_GET(create_rq_out, out, rqn); 1548 return rq; 1549 } 1550 1551 /** 1552 * Modify RQ using DevX API. 1553 * 1554 * @param[in] rq 1555 * Pointer to RQ object structure. 1556 * @param [in] rq_attr 1557 * Pointer to modify RQ attributes structure. 1558 * 1559 * @return 1560 * 0 on success, a negative errno value otherwise and rte_errno is set. 1561 */ 1562 int 1563 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1564 struct mlx5_devx_modify_rq_attr *rq_attr) 1565 { 1566 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1567 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1568 void *rq_ctx, *wq_ctx; 1569 int ret; 1570 1571 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1572 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1573 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1574 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1575 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1576 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1577 if (rq_attr->modify_bitmask & 1578 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1579 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1580 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1581 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1582 if (rq_attr->modify_bitmask & 1583 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1584 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1585 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1586 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1587 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1588 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1589 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1590 } 1591 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1592 out, sizeof(out)); 1593 if (ret) { 1594 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1595 rte_errno = errno; 1596 return -errno; 1597 } 1598 return ret; 1599 } 1600 1601 /* 1602 * Query RQ using DevX API. 1603 * 1604 * @param[in] rq_obj 1605 * RQ Devx Object 1606 * @param[out] out 1607 * RQ Query Output 1608 * @param[in] outlen 1609 * RQ Query Output Length 1610 * 1611 * @return 1612 * 0 if Query successful, else non-zero return value from devx_obj_query API 1613 */ 1614 int 1615 mlx5_devx_cmd_query_rq(struct mlx5_devx_obj *rq_obj, void *out, size_t outlen) 1616 { 1617 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 1618 int rc; 1619 1620 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 1621 MLX5_SET(query_rq_in, in, rqn, rq_obj->id); 1622 rc = mlx5_glue->devx_obj_query(rq_obj->obj, in, sizeof(in), out, outlen); 1623 if (rc || MLX5_FW_STATUS(out)) { 1624 DEVX_DRV_LOG(ERR, out, "RQ query", "rq_id", rq_obj->id); 1625 return MLX5_DEVX_ERR_RC(rc); 1626 } 1627 return 0; 1628 } 1629 1630 /** 1631 * Create RMP using DevX API. 1632 * 1633 * @param[in] ctx 1634 * Context returned from mlx5 open_device() glue function. 1635 * @param [in] rmp_attr 1636 * Pointer to create RMP attributes structure. 1637 * @param [in] socket 1638 * CPU socket ID for allocations. 1639 * 1640 * @return 1641 * The DevX object created, NULL otherwise and rte_errno is set. 1642 */ 1643 struct mlx5_devx_obj * 1644 mlx5_devx_cmd_create_rmp(void *ctx, 1645 struct mlx5_devx_create_rmp_attr *rmp_attr, 1646 int socket) 1647 { 1648 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1649 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1650 void *rmp_ctx, *wq_ctx; 1651 struct mlx5_devx_wq_attr *wq_attr; 1652 struct mlx5_devx_obj *rmp = NULL; 1653 1654 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1655 if (!rmp) { 1656 DRV_LOG(ERR, "Failed to allocate RMP data"); 1657 rte_errno = ENOMEM; 1658 return NULL; 1659 } 1660 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1661 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1662 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1663 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1664 rmp_attr->basic_cyclic_rcv_wqe); 1665 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1666 wq_attr = &rmp_attr->wq_attr; 1667 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1668 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1669 sizeof(out)); 1670 if (!rmp->obj) { 1671 DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0); 1672 mlx5_free(rmp); 1673 return NULL; 1674 } 1675 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1676 return rmp; 1677 } 1678 1679 /* 1680 * Create TIR using DevX API. 1681 * 1682 * @param[in] ctx 1683 * Context returned from mlx5 open_device() glue function. 1684 * @param [in] tir_attr 1685 * Pointer to TIR attributes structure. 1686 * 1687 * @return 1688 * The DevX object created, NULL otherwise and rte_errno is set. 1689 */ 1690 struct mlx5_devx_obj * 1691 mlx5_devx_cmd_create_tir(void *ctx, 1692 struct mlx5_devx_tir_attr *tir_attr) 1693 { 1694 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1695 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1696 void *tir_ctx, *outer, *inner, *rss_key; 1697 struct mlx5_devx_obj *tir = NULL; 1698 1699 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1700 if (!tir) { 1701 DRV_LOG(ERR, "Failed to allocate TIR data"); 1702 rte_errno = ENOMEM; 1703 return NULL; 1704 } 1705 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1706 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1707 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1708 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1709 tir_attr->lro_timeout_period_usecs); 1710 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1711 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1712 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1713 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1714 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1715 tir_attr->tunneled_offload_en); 1716 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1717 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1718 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1719 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1720 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1721 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1722 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1723 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1724 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1725 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1726 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1727 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1728 tir_attr->rx_hash_field_selector_outer.selected_fields); 1729 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1730 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1731 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1732 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1733 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1734 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1735 tir_attr->rx_hash_field_selector_inner.selected_fields); 1736 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1737 out, sizeof(out)); 1738 if (!tir->obj) { 1739 DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0); 1740 mlx5_free(tir); 1741 return NULL; 1742 } 1743 tir->id = MLX5_GET(create_tir_out, out, tirn); 1744 return tir; 1745 } 1746 1747 /** 1748 * Modify TIR using DevX API. 1749 * 1750 * @param[in] tir 1751 * Pointer to TIR DevX object structure. 1752 * @param [in] modify_tir_attr 1753 * Pointer to TIR modification attributes structure. 1754 * 1755 * @return 1756 * 0 on success, a negative errno value otherwise and rte_errno is set. 1757 */ 1758 int 1759 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1760 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1761 { 1762 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1763 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1764 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1765 void *tir_ctx; 1766 int ret; 1767 1768 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1769 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1770 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1771 modify_tir_attr->modify_bitmask); 1772 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1773 if (modify_tir_attr->modify_bitmask & 1774 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1775 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1776 tir_attr->lro_timeout_period_usecs); 1777 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1778 tir_attr->lro_enable_mask); 1779 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1780 tir_attr->lro_max_msg_sz); 1781 } 1782 if (modify_tir_attr->modify_bitmask & 1783 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1784 MLX5_SET(tirc, tir_ctx, indirect_table, 1785 tir_attr->indirect_table); 1786 if (modify_tir_attr->modify_bitmask & 1787 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1788 int i; 1789 void *outer, *inner; 1790 1791 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1792 tir_attr->rx_hash_symmetric); 1793 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1794 for (i = 0; i < 10; i++) { 1795 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1796 tir_attr->rx_hash_toeplitz_key[i]); 1797 } 1798 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1799 rx_hash_field_selector_outer); 1800 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1801 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1802 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1803 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1804 MLX5_SET 1805 (rx_hash_field_select, outer, selected_fields, 1806 tir_attr->rx_hash_field_selector_outer.selected_fields); 1807 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1808 rx_hash_field_selector_inner); 1809 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1810 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1811 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1812 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1813 MLX5_SET 1814 (rx_hash_field_select, inner, selected_fields, 1815 tir_attr->rx_hash_field_selector_inner.selected_fields); 1816 } 1817 if (modify_tir_attr->modify_bitmask & 1818 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1819 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1820 } 1821 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1822 out, sizeof(out)); 1823 if (ret) { 1824 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1825 rte_errno = errno; 1826 return -errno; 1827 } 1828 return ret; 1829 } 1830 1831 /** 1832 * Create RQT using DevX API. 1833 * 1834 * @param[in] ctx 1835 * Context returned from mlx5 open_device() glue function. 1836 * @param [in] rqt_attr 1837 * Pointer to RQT attributes structure. 1838 * 1839 * @return 1840 * The DevX object created, NULL otherwise and rte_errno is set. 1841 */ 1842 struct mlx5_devx_obj * 1843 mlx5_devx_cmd_create_rqt(void *ctx, 1844 struct mlx5_devx_rqt_attr *rqt_attr) 1845 { 1846 uint32_t *in = NULL; 1847 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1848 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1849 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1850 void *rqt_ctx; 1851 struct mlx5_devx_obj *rqt = NULL; 1852 unsigned int i; 1853 1854 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1855 if (!in) { 1856 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1857 rte_errno = ENOMEM; 1858 return NULL; 1859 } 1860 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1861 if (!rqt) { 1862 DRV_LOG(ERR, "Failed to allocate RQT data"); 1863 rte_errno = ENOMEM; 1864 mlx5_free(in); 1865 return NULL; 1866 } 1867 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1868 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1869 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1870 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1871 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1872 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1873 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1874 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1875 mlx5_free(in); 1876 if (!rqt->obj) { 1877 DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0); 1878 mlx5_free(rqt); 1879 return NULL; 1880 } 1881 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1882 return rqt; 1883 } 1884 1885 /** 1886 * Modify RQT using DevX API. 1887 * 1888 * @param[in] rqt 1889 * Pointer to RQT DevX object structure. 1890 * @param [in] rqt_attr 1891 * Pointer to RQT attributes structure. 1892 * 1893 * @return 1894 * 0 on success, a negative errno value otherwise and rte_errno is set. 1895 */ 1896 int 1897 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1898 struct mlx5_devx_rqt_attr *rqt_attr) 1899 { 1900 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1901 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1902 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1903 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1904 void *rqt_ctx; 1905 unsigned int i; 1906 int ret; 1907 1908 if (!in) { 1909 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1910 rte_errno = ENOMEM; 1911 return -ENOMEM; 1912 } 1913 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1914 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1915 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1916 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1917 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1918 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1919 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1920 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1921 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1922 mlx5_free(in); 1923 if (ret) { 1924 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1925 rte_errno = errno; 1926 return -rte_errno; 1927 } 1928 return ret; 1929 } 1930 1931 /** 1932 * Create SQ using DevX API. 1933 * 1934 * @param[in] ctx 1935 * Context returned from mlx5 open_device() glue function. 1936 * @param [in] sq_attr 1937 * Pointer to SQ attributes structure. 1938 * @param [in] socket 1939 * CPU socket ID for allocations. 1940 * 1941 * @return 1942 * The DevX object created, NULL otherwise and rte_errno is set. 1943 **/ 1944 struct mlx5_devx_obj * 1945 mlx5_devx_cmd_create_sq(void *ctx, 1946 struct mlx5_devx_create_sq_attr *sq_attr) 1947 { 1948 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1949 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1950 void *sq_ctx; 1951 void *wq_ctx; 1952 struct mlx5_devx_wq_attr *wq_attr; 1953 struct mlx5_devx_obj *sq = NULL; 1954 1955 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1956 if (!sq) { 1957 DRV_LOG(ERR, "Failed to allocate SQ data"); 1958 rte_errno = ENOMEM; 1959 return NULL; 1960 } 1961 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1962 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1963 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1964 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1965 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1966 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1967 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1968 sq_attr->allow_multi_pkt_send_wqe); 1969 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1970 sq_attr->min_wqe_inline_mode); 1971 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1972 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1973 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1974 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1975 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1976 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1977 MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type); 1978 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1979 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1980 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1981 sq_attr->packet_pacing_rate_limit_index); 1982 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1983 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1984 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1985 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1986 wq_attr = &sq_attr->wq_attr; 1987 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1988 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1989 out, sizeof(out)); 1990 if (!sq->obj) { 1991 DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0); 1992 mlx5_free(sq); 1993 return NULL; 1994 } 1995 sq->id = MLX5_GET(create_sq_out, out, sqn); 1996 return sq; 1997 } 1998 1999 /** 2000 * Modify SQ using DevX API. 2001 * 2002 * @param[in] sq 2003 * Pointer to SQ object structure. 2004 * @param [in] sq_attr 2005 * Pointer to SQ attributes structure. 2006 * 2007 * @return 2008 * 0 on success, a negative errno value otherwise and rte_errno is set. 2009 */ 2010 int 2011 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 2012 struct mlx5_devx_modify_sq_attr *sq_attr) 2013 { 2014 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 2015 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 2016 void *sq_ctx; 2017 int ret; 2018 2019 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 2020 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 2021 MLX5_SET(modify_sq_in, in, sqn, sq->id); 2022 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2023 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 2024 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 2025 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 2026 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 2027 out, sizeof(out)); 2028 if (ret) { 2029 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 2030 rte_errno = errno; 2031 return -rte_errno; 2032 } 2033 return ret; 2034 } 2035 2036 /* 2037 * Query SQ using DevX API. 2038 * 2039 * @param[in] sq_obj 2040 * SQ Devx Object 2041 * @param[out] out 2042 * SQ Query Output 2043 * @param[in] outlen 2044 * SQ Query Output Length 2045 * 2046 * @return 2047 * 0 if Query successful, else non-zero return value from devx_obj_query API 2048 */ 2049 int 2050 mlx5_devx_cmd_query_sq(struct mlx5_devx_obj *sq_obj, void *out, size_t outlen) 2051 { 2052 uint32_t in[MLX5_ST_SZ_DW(query_sq_in)] = {0}; 2053 int rc; 2054 2055 MLX5_SET(query_sq_in, in, opcode, MLX5_CMD_OP_QUERY_SQ); 2056 MLX5_SET(query_sq_in, in, sqn, sq_obj->id); 2057 rc = mlx5_glue->devx_obj_query(sq_obj->obj, in, sizeof(in), out, outlen); 2058 if (rc || MLX5_FW_STATUS(out)) { 2059 DEVX_DRV_LOG(ERR, out, "SQ query", "sq_id", sq_obj->id); 2060 return MLX5_DEVX_ERR_RC(rc); 2061 } 2062 return 0; 2063 } 2064 2065 /** 2066 * Create TIS using DevX API. 2067 * 2068 * @param[in] ctx 2069 * Context returned from mlx5 open_device() glue function. 2070 * @param [in] tis_attr 2071 * Pointer to TIS attributes structure. 2072 * 2073 * @return 2074 * The DevX object created, NULL otherwise and rte_errno is set. 2075 */ 2076 struct mlx5_devx_obj * 2077 mlx5_devx_cmd_create_tis(void *ctx, 2078 struct mlx5_devx_tis_attr *tis_attr) 2079 { 2080 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 2081 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 2082 struct mlx5_devx_obj *tis = NULL; 2083 void *tis_ctx; 2084 2085 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 2086 if (!tis) { 2087 DRV_LOG(ERR, "Failed to allocate TIS object"); 2088 rte_errno = ENOMEM; 2089 return NULL; 2090 } 2091 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 2092 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 2093 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 2094 tis_attr->strict_lag_tx_port_affinity); 2095 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 2096 tis_attr->lag_tx_port_affinity); 2097 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 2098 MLX5_SET(tisc, tis_ctx, transport_domain, 2099 tis_attr->transport_domain); 2100 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2101 out, sizeof(out)); 2102 if (!tis->obj) { 2103 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 2104 mlx5_free(tis); 2105 return NULL; 2106 } 2107 tis->id = MLX5_GET(create_tis_out, out, tisn); 2108 return tis; 2109 } 2110 2111 /** 2112 * Create transport domain using DevX API. 2113 * 2114 * @param[in] ctx 2115 * Context returned from mlx5 open_device() glue function. 2116 * @return 2117 * The DevX object created, NULL otherwise and rte_errno is set. 2118 */ 2119 struct mlx5_devx_obj * 2120 mlx5_devx_cmd_create_td(void *ctx) 2121 { 2122 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 2123 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 2124 struct mlx5_devx_obj *td = NULL; 2125 2126 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 2127 if (!td) { 2128 DRV_LOG(ERR, "Failed to allocate TD object"); 2129 rte_errno = ENOMEM; 2130 return NULL; 2131 } 2132 MLX5_SET(alloc_transport_domain_in, in, opcode, 2133 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 2134 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2135 out, sizeof(out)); 2136 if (!td->obj) { 2137 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 2138 mlx5_free(td); 2139 return NULL; 2140 } 2141 td->id = MLX5_GET(alloc_transport_domain_out, out, 2142 transport_domain); 2143 return td; 2144 } 2145 2146 /** 2147 * Dump all flows to file. 2148 * 2149 * @param[in] fdb_domain 2150 * FDB domain. 2151 * @param[in] rx_domain 2152 * RX domain. 2153 * @param[in] tx_domain 2154 * TX domain. 2155 * @param[out] file 2156 * Pointer to file stream. 2157 * 2158 * @return 2159 * 0 on success, a negative value otherwise. 2160 */ 2161 int 2162 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 2163 void *rx_domain __rte_unused, 2164 void *tx_domain __rte_unused, FILE *file __rte_unused) 2165 { 2166 int ret = 0; 2167 2168 #ifdef HAVE_MLX5_DR_FLOW_DUMP 2169 if (fdb_domain) { 2170 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 2171 if (ret) 2172 return ret; 2173 } 2174 MLX5_ASSERT(rx_domain); 2175 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 2176 if (ret) 2177 return ret; 2178 MLX5_ASSERT(tx_domain); 2179 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 2180 #else 2181 ret = ENOTSUP; 2182 #endif 2183 return -ret; 2184 } 2185 2186 int 2187 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 2188 FILE *file __rte_unused) 2189 { 2190 int ret = 0; 2191 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 2192 if (rule_info) 2193 ret = mlx5_glue->dr_dump_rule(file, rule_info); 2194 #else 2195 ret = ENOTSUP; 2196 #endif 2197 return -ret; 2198 } 2199 2200 /* 2201 * Create CQ using DevX API. 2202 * 2203 * @param[in] ctx 2204 * Context returned from mlx5 open_device() glue function. 2205 * @param [in] attr 2206 * Pointer to CQ attributes structure. 2207 * 2208 * @return 2209 * The DevX object created, NULL otherwise and rte_errno is set. 2210 */ 2211 struct mlx5_devx_obj * 2212 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 2213 { 2214 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 2215 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 2216 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2217 sizeof(*cq_obj), 2218 0, SOCKET_ID_ANY); 2219 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2220 2221 if (!cq_obj) { 2222 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 2223 rte_errno = ENOMEM; 2224 return NULL; 2225 } 2226 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 2227 if (attr->db_umem_valid) { 2228 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 2229 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 2230 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 2231 } else { 2232 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 2233 } 2234 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 2235 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 2236 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 2237 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 2238 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 2239 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2240 MLX5_SET(cqc, cqctx, log_page_size, 2241 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2242 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 2243 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 2244 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 2245 MLX5_SET(cqc, cqctx, cqe_comp_layout, !!attr->cqe_comp_layout); 2246 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 2247 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 2248 attr->mini_cqe_res_format_ext); 2249 if (attr->q_umem_valid) { 2250 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 2251 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 2252 MLX5_SET64(create_cq_in, in, cq_umem_offset, 2253 attr->q_umem_offset); 2254 } 2255 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2256 sizeof(out)); 2257 if (!cq_obj->obj) { 2258 DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0); 2259 mlx5_free(cq_obj); 2260 return NULL; 2261 } 2262 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 2263 return cq_obj; 2264 } 2265 2266 /* 2267 * Query CQ using DevX API. 2268 * 2269 * @param[in] cq_obj 2270 * CQ Devx Object 2271 * @param[out] out 2272 * CQ Query Output 2273 * @param[in] outlen 2274 * CQ Query Output Length 2275 * 2276 * @return 2277 * 0 if Query successful, else non-zero return value from devx_obj_query API 2278 */ 2279 int 2280 mlx5_devx_cmd_query_cq(struct mlx5_devx_obj *cq_obj, void *out, size_t outlen) 2281 { 2282 uint32_t in[MLX5_ST_SZ_DW(query_cq_in)] = {0}; 2283 int rc; 2284 2285 MLX5_SET(query_cq_in, in, opcode, MLX5_CMD_OP_QUERY_CQ); 2286 MLX5_SET(query_cq_in, in, cqn, cq_obj->id); 2287 rc = mlx5_glue->devx_obj_query(cq_obj->obj, in, sizeof(in), out, outlen); 2288 if (rc || MLX5_FW_STATUS(out)) { 2289 DEVX_DRV_LOG(ERR, out, "CQ query", "cq_id", cq_obj->id); 2290 return MLX5_DEVX_ERR_RC(rc); 2291 } 2292 return 0; 2293 } 2294 2295 /** 2296 * Create VIRTQ using DevX API. 2297 * 2298 * @param[in] ctx 2299 * Context returned from mlx5 open_device() glue function. 2300 * @param [in] attr 2301 * Pointer to VIRTQ attributes structure. 2302 * 2303 * @return 2304 * The DevX object created, NULL otherwise and rte_errno is set. 2305 */ 2306 struct mlx5_devx_obj * 2307 mlx5_devx_cmd_create_virtq(void *ctx, 2308 struct mlx5_devx_virtq_attr *attr) 2309 { 2310 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2311 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2312 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2313 sizeof(*virtq_obj), 2314 0, SOCKET_ID_ANY); 2315 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2316 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2317 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2318 2319 if (!virtq_obj) { 2320 DRV_LOG(ERR, "Failed to allocate virtq data."); 2321 rte_errno = ENOMEM; 2322 return NULL; 2323 } 2324 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2325 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2326 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2327 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2328 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2329 attr->hw_available_index); 2330 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 2331 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2332 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2333 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2334 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2335 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2336 attr->virtio_version_1_0); 2337 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2338 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2339 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2340 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2341 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 2342 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2343 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 2344 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2345 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 2346 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 2347 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 2348 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 2349 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 2350 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 2351 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 2352 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 2353 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 2354 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 2355 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 2356 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 2357 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 2358 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 2359 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 2360 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2361 sizeof(out)); 2362 if (!virtq_obj->obj) { 2363 DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0); 2364 mlx5_free(virtq_obj); 2365 return NULL; 2366 } 2367 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2368 return virtq_obj; 2369 } 2370 2371 /** 2372 * Modify VIRTQ using DevX API. 2373 * 2374 * @param[in] virtq_obj 2375 * Pointer to virtq object structure. 2376 * @param [in] attr 2377 * Pointer to modify virtq attributes structure. 2378 * 2379 * @return 2380 * 0 on success, a negative errno value otherwise and rte_errno is set. 2381 */ 2382 int 2383 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2384 struct mlx5_devx_virtq_attr *attr) 2385 { 2386 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2387 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2388 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2389 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2390 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2391 int ret; 2392 2393 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2394 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2395 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2396 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2397 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2398 MLX5_SET64(virtio_net_q, virtq, modify_field_select, 2399 attr->mod_fields_bitmap); 2400 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2401 if (!attr->mod_fields_bitmap) { 2402 DRV_LOG(ERR, "Failed to modify VIRTQ for no type set."); 2403 rte_errno = EINVAL; 2404 return -rte_errno; 2405 } 2406 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE) 2407 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2408 if (attr->mod_fields_bitmap & 2409 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) { 2410 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2411 attr->dirty_bitmap_mkey); 2412 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2413 attr->dirty_bitmap_addr); 2414 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2415 attr->dirty_bitmap_size); 2416 } 2417 if (attr->mod_fields_bitmap & 2418 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE) 2419 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2420 attr->dirty_bitmap_dump_enable); 2421 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) { 2422 MLX5_SET(virtio_q, virtctx, queue_period_mode, 2423 attr->hw_latency_mode); 2424 MLX5_SET(virtio_q, virtctx, queue_period_us, 2425 attr->hw_max_latency_us); 2426 MLX5_SET(virtio_q, virtctx, queue_max_count, 2427 attr->hw_max_pending_comp); 2428 } 2429 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) { 2430 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2431 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2432 MLX5_SET64(virtio_q, virtctx, available_addr, 2433 attr->available_addr); 2434 } 2435 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX) 2436 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2437 attr->hw_available_index); 2438 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX) 2439 MLX5_SET16(virtio_net_q, virtq, hw_used_index, 2440 attr->hw_used_index); 2441 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE) 2442 MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type); 2443 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0) 2444 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2445 attr->virtio_version_1_0); 2446 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY) 2447 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2448 if (attr->mod_fields_bitmap & 2449 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) { 2450 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2451 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2452 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2453 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2454 } 2455 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) { 2456 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2457 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2458 } 2459 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2460 out, sizeof(out)); 2461 if (ret) { 2462 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2463 rte_errno = errno; 2464 return -rte_errno; 2465 } 2466 return ret; 2467 } 2468 2469 /** 2470 * Query VIRTQ using DevX API. 2471 * 2472 * @param[in] virtq_obj 2473 * Pointer to virtq object structure. 2474 * @param [in/out] attr 2475 * Pointer to virtq attributes structure. 2476 * 2477 * @return 2478 * 0 on success, a negative errno value otherwise and rte_errno is set. 2479 */ 2480 int 2481 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2482 struct mlx5_devx_virtq_attr *attr) 2483 { 2484 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2485 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2486 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2487 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2488 int ret; 2489 2490 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2491 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2492 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2493 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2494 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2495 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2496 out, sizeof(out)); 2497 if (ret) { 2498 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2499 rte_errno = errno; 2500 return -errno; 2501 } 2502 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2503 hw_available_index); 2504 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2505 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2506 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2507 virtio_q_context.error_type); 2508 return ret; 2509 } 2510 2511 /** 2512 * Create QP using DevX API. 2513 * 2514 * @param[in] ctx 2515 * Context returned from mlx5 open_device() glue function. 2516 * @param [in] attr 2517 * Pointer to QP attributes structure. 2518 * 2519 * @return 2520 * The DevX object created, NULL otherwise and rte_errno is set. 2521 */ 2522 struct mlx5_devx_obj * 2523 mlx5_devx_cmd_create_qp(void *ctx, 2524 struct mlx5_devx_qp_attr *attr) 2525 { 2526 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2527 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2528 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2529 sizeof(*qp_obj), 2530 0, SOCKET_ID_ANY); 2531 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2532 2533 if (!qp_obj) { 2534 DRV_LOG(ERR, "Failed to allocate QP data."); 2535 rte_errno = ENOMEM; 2536 return NULL; 2537 } 2538 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2539 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2540 MLX5_SET(qpc, qpc, pd, attr->pd); 2541 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2542 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2543 if (attr->uar_index) { 2544 if (attr->mmo) { 2545 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2546 in, qpc_extension_and_pas_list); 2547 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2548 qpc_ext_and_pas_list, qpc_data_extension); 2549 2550 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2551 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2552 } 2553 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2554 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2555 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2556 MLX5_SET(qpc, qpc, log_page_size, 2557 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2558 if (attr->num_of_send_wqbbs) { 2559 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); 2560 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2561 MLX5_SET(qpc, qpc, log_sq_size, 2562 rte_log2_u32(attr->num_of_send_wqbbs)); 2563 } else { 2564 MLX5_SET(qpc, qpc, no_sq, 1); 2565 } 2566 if (attr->num_of_receive_wqes) { 2567 MLX5_ASSERT(RTE_IS_POWER_OF_2( 2568 attr->num_of_receive_wqes)); 2569 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2570 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2571 MLX5_LOG_RQ_STRIDE_SHIFT); 2572 MLX5_SET(qpc, qpc, log_rq_size, 2573 rte_log2_u32(attr->num_of_receive_wqes)); 2574 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2575 } else { 2576 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2577 } 2578 if (attr->dbr_umem_valid) { 2579 MLX5_SET(qpc, qpc, dbr_umem_valid, 2580 attr->dbr_umem_valid); 2581 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2582 } 2583 if (attr->cd_master) 2584 MLX5_SET(qpc, qpc, cd_master, attr->cd_master); 2585 if (attr->cd_slave_send) 2586 MLX5_SET(qpc, qpc, cd_slave_send, attr->cd_slave_send); 2587 if (attr->cd_slave_recv) 2588 MLX5_SET(qpc, qpc, cd_slave_receive, attr->cd_slave_recv); 2589 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2590 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2591 attr->wq_umem_offset); 2592 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2593 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2594 } else { 2595 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2596 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2597 MLX5_SET(qpc, qpc, no_sq, 1); 2598 } 2599 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2600 sizeof(out)); 2601 if (!qp_obj->obj) { 2602 DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0); 2603 mlx5_free(qp_obj); 2604 return NULL; 2605 } 2606 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2607 return qp_obj; 2608 } 2609 2610 /** 2611 * Modify QP using DevX API. 2612 * Currently supports only force loop-back QP. 2613 * 2614 * @param[in] qp 2615 * Pointer to QP object structure. 2616 * @param [in] qp_st_mod_op 2617 * The QP state modification operation. 2618 * @param [in] remote_qp_id 2619 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2620 * 2621 * @return 2622 * 0 on success, a negative errno value otherwise and rte_errno is set. 2623 */ 2624 int 2625 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2626 uint32_t remote_qp_id) 2627 { 2628 union { 2629 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2630 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2631 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2632 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; 2633 } in; 2634 union { 2635 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2636 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2637 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2638 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; 2639 } out; 2640 void *qpc; 2641 int ret; 2642 unsigned int inlen; 2643 unsigned int outlen; 2644 2645 memset(&in, 0, sizeof(in)); 2646 memset(&out, 0, sizeof(out)); 2647 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2648 switch (qp_st_mod_op) { 2649 case MLX5_CMD_OP_RST2INIT_QP: 2650 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2651 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2652 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2653 MLX5_SET(qpc, qpc, rre, 1); 2654 MLX5_SET(qpc, qpc, rwe, 1); 2655 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2656 inlen = sizeof(in.rst2init); 2657 outlen = sizeof(out.rst2init); 2658 break; 2659 case MLX5_CMD_OP_INIT2RTR_QP: 2660 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2661 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2662 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2663 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2664 MLX5_SET(qpc, qpc, mtu, 1); 2665 MLX5_SET(qpc, qpc, log_msg_max, 30); 2666 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2667 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2668 inlen = sizeof(in.init2rtr); 2669 outlen = sizeof(out.init2rtr); 2670 break; 2671 case MLX5_CMD_OP_RTR2RTS_QP: 2672 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2673 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2674 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16); 2675 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2676 MLX5_SET(qpc, qpc, retry_count, 7); 2677 MLX5_SET(qpc, qpc, rnr_retry, 7); 2678 inlen = sizeof(in.rtr2rts); 2679 outlen = sizeof(out.rtr2rts); 2680 break; 2681 case MLX5_CMD_OP_QP_2RST: 2682 MLX5_SET(2rst_qp_in, &in, qpn, qp->id); 2683 inlen = sizeof(in.qp2rst); 2684 outlen = sizeof(out.qp2rst); 2685 break; 2686 default: 2687 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2688 qp_st_mod_op); 2689 rte_errno = EINVAL; 2690 return -rte_errno; 2691 } 2692 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2693 if (ret) { 2694 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2695 rte_errno = errno; 2696 return -rte_errno; 2697 } 2698 return ret; 2699 } 2700 2701 struct mlx5_devx_obj * 2702 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2703 { 2704 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2705 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2706 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2707 sizeof(*couners_obj), 0, 2708 SOCKET_ID_ANY); 2709 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2710 2711 if (!couners_obj) { 2712 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2713 rte_errno = ENOMEM; 2714 return NULL; 2715 } 2716 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2717 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2718 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2719 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2720 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2721 sizeof(out)); 2722 if (!couners_obj->obj) { 2723 DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL, 2724 0); 2725 mlx5_free(couners_obj); 2726 return NULL; 2727 } 2728 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2729 return couners_obj; 2730 } 2731 2732 int 2733 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2734 struct mlx5_devx_virtio_q_couners_attr *attr) 2735 { 2736 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2737 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2738 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2739 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2740 virtio_q_counters); 2741 int ret; 2742 2743 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2744 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2745 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2746 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2747 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2748 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2749 sizeof(out)); 2750 if (ret) { 2751 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2752 rte_errno = errno; 2753 return -errno; 2754 } 2755 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2756 received_desc); 2757 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2758 completed_desc); 2759 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2760 error_cqes); 2761 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2762 bad_desc_errors); 2763 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2764 exceed_max_chain); 2765 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2766 invalid_buffer); 2767 return ret; 2768 } 2769 2770 /** 2771 * Create general object of type FLOW_HIT_ASO using DevX API. 2772 * 2773 * @param[in] ctx 2774 * Context returned from mlx5 open_device() glue function. 2775 * @param [in] pd 2776 * PD value to associate the FLOW_HIT_ASO object with. 2777 * 2778 * @return 2779 * The DevX object created, NULL otherwise and rte_errno is set. 2780 */ 2781 struct mlx5_devx_obj * 2782 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2783 { 2784 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2785 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2786 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2787 void *ptr = NULL; 2788 2789 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2790 0, SOCKET_ID_ANY); 2791 if (!flow_hit_aso_obj) { 2792 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2793 rte_errno = ENOMEM; 2794 return NULL; 2795 } 2796 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2797 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2798 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2799 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2800 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2801 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2802 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2803 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2804 out, sizeof(out)); 2805 if (!flow_hit_aso_obj->obj) { 2806 DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0); 2807 mlx5_free(flow_hit_aso_obj); 2808 return NULL; 2809 } 2810 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2811 return flow_hit_aso_obj; 2812 } 2813 2814 /* 2815 * Create PD using DevX API. 2816 * 2817 * @param[in] ctx 2818 * Context returned from mlx5 open_device() glue function. 2819 * 2820 * @return 2821 * The DevX object created, NULL otherwise and rte_errno is set. 2822 */ 2823 struct mlx5_devx_obj * 2824 mlx5_devx_cmd_alloc_pd(void *ctx) 2825 { 2826 struct mlx5_devx_obj *ppd = 2827 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2828 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2829 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2830 2831 if (!ppd) { 2832 DRV_LOG(ERR, "Failed to allocate PD data."); 2833 rte_errno = ENOMEM; 2834 return NULL; 2835 } 2836 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2837 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2838 out, sizeof(out)); 2839 if (!ppd->obj) { 2840 mlx5_free(ppd); 2841 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2842 rte_errno = errno; 2843 return NULL; 2844 } 2845 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2846 return ppd; 2847 } 2848 2849 /** 2850 * Create general object of type FLOW_METER_ASO using DevX API. 2851 * 2852 * @param[in] ctx 2853 * Context returned from mlx5 open_device() glue function. 2854 * @param [in] pd 2855 * PD value to associate the FLOW_METER_ASO object with. 2856 * @param [in] log_obj_size 2857 * log_obj_size define to allocate number of 2 * meters 2858 * in one FLOW_METER_ASO object. 2859 * 2860 * @return 2861 * The DevX object created, NULL otherwise and rte_errno is set. 2862 */ 2863 struct mlx5_devx_obj * 2864 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2865 uint32_t log_obj_size) 2866 { 2867 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2868 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2869 struct mlx5_devx_obj *flow_meter_aso_obj; 2870 void *ptr; 2871 2872 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2873 sizeof(*flow_meter_aso_obj), 2874 0, SOCKET_ID_ANY); 2875 if (!flow_meter_aso_obj) { 2876 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2877 rte_errno = ENOMEM; 2878 return NULL; 2879 } 2880 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2881 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2882 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2883 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2884 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2885 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2886 log_obj_size); 2887 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2888 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2889 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2890 ctx, in, sizeof(in), 2891 out, sizeof(out)); 2892 if (!flow_meter_aso_obj->obj) { 2893 DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0); 2894 mlx5_free(flow_meter_aso_obj); 2895 return NULL; 2896 } 2897 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2898 out, obj_id); 2899 return flow_meter_aso_obj; 2900 } 2901 2902 /* 2903 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2904 * 2905 * @param[in] ctx 2906 * Context returned from mlx5 open_device() glue function. 2907 * @param [in] pd 2908 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2909 * @param [in] log_obj_size 2910 * log_obj_size to allocate its power of 2 * objects 2911 * in one CONN_TRACK_OFFLOAD bulk allocation. 2912 * 2913 * @return 2914 * The DevX object created, NULL otherwise and rte_errno is set. 2915 */ 2916 struct mlx5_devx_obj * 2917 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2918 uint32_t log_obj_size) 2919 { 2920 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2921 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2922 struct mlx5_devx_obj *ct_aso_obj; 2923 void *ptr; 2924 2925 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2926 0, SOCKET_ID_ANY); 2927 if (!ct_aso_obj) { 2928 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2929 rte_errno = ENOMEM; 2930 return NULL; 2931 } 2932 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2933 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2934 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2935 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2936 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2937 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2938 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2939 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2940 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2941 out, sizeof(out)); 2942 if (!ct_aso_obj->obj) { 2943 DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0); 2944 mlx5_free(ct_aso_obj); 2945 return NULL; 2946 } 2947 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2948 return ct_aso_obj; 2949 } 2950 2951 /** 2952 * Create general object of type GENEVE TLV option using DevX API. 2953 * 2954 * @param[in] ctx 2955 * Context returned from mlx5 open_device() glue function. 2956 * @param[in] attr 2957 * Pointer to GENEVE TLV option attributes structure. 2958 * 2959 * @return 2960 * The DevX object created, NULL otherwise and rte_errno is set. 2961 */ 2962 struct mlx5_devx_obj * 2963 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2964 struct mlx5_devx_geneve_tlv_option_attr *attr) 2965 { 2966 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2967 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2968 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2969 sizeof(*geneve_tlv_opt_obj), 2970 0, SOCKET_ID_ANY); 2971 2972 if (!geneve_tlv_opt_obj) { 2973 DRV_LOG(ERR, "Failed to allocate GENEVE TLV option object."); 2974 rte_errno = ENOMEM; 2975 return NULL; 2976 } 2977 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2978 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2979 geneve_tlv_opt); 2980 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2981 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2982 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2983 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2984 MLX5_SET(geneve_tlv_option, opt, option_type, attr->option_type); 2985 MLX5_SET(geneve_tlv_option, opt, option_data_length, 2986 attr->option_data_len); 2987 if (attr->option_class_ignore) 2988 MLX5_SET(geneve_tlv_option, opt, option_class_ignore, 2989 attr->option_class_ignore); 2990 else 2991 MLX5_SET(geneve_tlv_option, opt, option_class, 2992 rte_be_to_cpu_16(attr->option_class)); 2993 if (attr->offset_valid) { 2994 MLX5_SET(geneve_tlv_option, opt, sample_offset_valid, 2995 attr->offset_valid); 2996 MLX5_SET(geneve_tlv_option, opt, sample_offset, 2997 attr->sample_offset); 2998 } 2999 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 3000 sizeof(in), out, 3001 sizeof(out)); 3002 if (!geneve_tlv_opt_obj->obj) { 3003 DEVX_DRV_LOG(ERR, out, "create GENEVE TLV option", NULL, 0); 3004 mlx5_free(geneve_tlv_opt_obj); 3005 return NULL; 3006 } 3007 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3008 return geneve_tlv_opt_obj; 3009 } 3010 3011 /** 3012 * Query GENEVE TLV option using DevX API. 3013 * 3014 * @param[in] ctx 3015 * Context used to create GENEVE TLV option object. 3016 * @param[in] geneve_tlv_opt_obj 3017 * DevX object of the GENEVE TLV option. 3018 * @param[out] attr 3019 * Pointer to match sample info attributes structure. 3020 * 3021 * @return 3022 * 0 on success, a negative errno otherwise and rte_errno is set. 3023 */ 3024 int 3025 mlx5_devx_cmd_query_geneve_tlv_option(void *ctx, 3026 struct mlx5_devx_obj *geneve_tlv_opt_obj, 3027 struct mlx5_devx_match_sample_info_query_attr *attr) 3028 { 3029 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 3030 uint32_t out[MLX5_ST_SZ_DW(query_geneve_tlv_option_out)] = {0}; 3031 void *hdr = MLX5_ADDR_OF(query_geneve_tlv_option_out, in, hdr); 3032 void *opt = MLX5_ADDR_OF(query_geneve_tlv_option_out, out, 3033 geneve_tlv_opt); 3034 int ret; 3035 3036 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 3037 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 3038 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 3039 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 3040 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, geneve_tlv_opt_obj->id); 3041 /* Call first query to get sample handle. */ 3042 ret = mlx5_glue->devx_obj_query(geneve_tlv_opt_obj->obj, in, sizeof(in), 3043 out, sizeof(out)); 3044 if (ret) { 3045 DRV_LOG(ERR, "Failed to query GENEVE TLV option using DevX."); 3046 rte_errno = errno; 3047 return -errno; 3048 } 3049 /* Call second query to get sample information. */ 3050 if (MLX5_GET(geneve_tlv_option, opt, sample_id_valid)) { 3051 uint32_t sample_id = MLX5_GET(geneve_tlv_option, opt, 3052 geneve_sample_field_id); 3053 3054 return mlx5_devx_cmd_match_sample_info_query(ctx, sample_id, 3055 attr); 3056 } 3057 DRV_LOG(DEBUG, "GENEVE TLV option sample isn't valid."); 3058 return 0; 3059 } 3060 3061 int 3062 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 3063 { 3064 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 3065 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 3066 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 3067 int rc; 3068 void *rq_ctx; 3069 3070 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 3071 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 3072 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 3073 if (rc) { 3074 rte_errno = errno; 3075 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 3076 "rc = %d, errno = %d.", rc, errno); 3077 return -rc; 3078 }; 3079 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 3080 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 3081 return 0; 3082 #else 3083 (void)wq; 3084 (void)counter_set_id; 3085 return -ENOTSUP; 3086 #endif 3087 } 3088 3089 /* 3090 * Allocate queue counters via devx interface. 3091 * 3092 * @param[in] ctx 3093 * Context returned from mlx5 open_device() glue function. 3094 * 3095 * @return 3096 * Pointer to counter object on success, a NULL value otherwise and 3097 * rte_errno is set. 3098 */ 3099 struct mlx5_devx_obj * 3100 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 3101 { 3102 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 3103 SOCKET_ID_ANY); 3104 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 3105 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 3106 3107 if (!dcs) { 3108 rte_errno = ENOMEM; 3109 return NULL; 3110 } 3111 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 3112 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 3113 sizeof(out)); 3114 if (!dcs->obj) { 3115 DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0); 3116 mlx5_free(dcs); 3117 return NULL; 3118 } 3119 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 3120 return dcs; 3121 } 3122 3123 /** 3124 * Query queue counters values. 3125 * 3126 * @param[in] dcs 3127 * devx object of the queue counter set. 3128 * @param[in] clear 3129 * Whether hardware should clear the counters after the query or not. 3130 * @param[out] out_of_buffers 3131 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 3132 * 3133 * @return 3134 * 0 on success, a negative value otherwise. 3135 */ 3136 int 3137 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 3138 uint32_t *out_of_buffers) 3139 { 3140 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 3141 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 3142 int rc; 3143 3144 MLX5_SET(query_q_counter_in, in, opcode, 3145 MLX5_CMD_OP_QUERY_Q_COUNTER); 3146 MLX5_SET(query_q_counter_in, in, op_mod, 0); 3147 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 3148 MLX5_SET(query_q_counter_in, in, clear, !!clear); 3149 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 3150 sizeof(out)); 3151 if (rc) { 3152 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 3153 rte_errno = rc; 3154 return -rc; 3155 } 3156 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 3157 return 0; 3158 } 3159 3160 /** 3161 * Create general object of type DEK using DevX API. 3162 * 3163 * @param[in] ctx 3164 * Context returned from mlx5 open_device() glue function. 3165 * @param [in] attr 3166 * Pointer to DEK attributes structure. 3167 * 3168 * @return 3169 * The DevX object created, NULL otherwise and rte_errno is set. 3170 */ 3171 struct mlx5_devx_obj * 3172 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 3173 { 3174 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 3175 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3176 struct mlx5_devx_obj *dek_obj = NULL; 3177 void *ptr = NULL, *key_addr = NULL; 3178 3179 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 3180 0, SOCKET_ID_ANY); 3181 if (dek_obj == NULL) { 3182 DRV_LOG(ERR, "Failed to allocate DEK object data"); 3183 rte_errno = ENOMEM; 3184 return NULL; 3185 } 3186 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 3187 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3188 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3189 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3190 MLX5_GENERAL_OBJ_TYPE_DEK); 3191 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 3192 MLX5_SET(dek, ptr, key_size, attr->key_size); 3193 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 3194 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 3195 MLX5_SET(dek, ptr, pd, attr->pd); 3196 MLX5_SET64(dek, ptr, opaque, attr->opaque); 3197 key_addr = MLX5_ADDR_OF(dek, ptr, key); 3198 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 3199 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3200 out, sizeof(out)); 3201 if (dek_obj->obj == NULL) { 3202 DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0); 3203 mlx5_free(dek_obj); 3204 return NULL; 3205 } 3206 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3207 return dek_obj; 3208 } 3209 3210 /** 3211 * Create general object of type IMPORT_KEK using DevX API. 3212 * 3213 * @param[in] ctx 3214 * Context returned from mlx5 open_device() glue function. 3215 * @param [in] attr 3216 * Pointer to IMPORT_KEK attributes structure. 3217 * 3218 * @return 3219 * The DevX object created, NULL otherwise and rte_errno is set. 3220 */ 3221 struct mlx5_devx_obj * 3222 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 3223 struct mlx5_devx_import_kek_attr *attr) 3224 { 3225 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 3226 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3227 struct mlx5_devx_obj *import_kek_obj = NULL; 3228 void *ptr = NULL, *key_addr = NULL; 3229 3230 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 3231 0, SOCKET_ID_ANY); 3232 if (import_kek_obj == NULL) { 3233 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 3234 rte_errno = ENOMEM; 3235 return NULL; 3236 } 3237 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 3238 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3239 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3240 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3241 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 3242 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 3243 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 3244 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 3245 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 3246 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3247 out, sizeof(out)); 3248 if (import_kek_obj->obj == NULL) { 3249 DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0); 3250 mlx5_free(import_kek_obj); 3251 return NULL; 3252 } 3253 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3254 return import_kek_obj; 3255 } 3256 3257 /** 3258 * Create general object of type CREDENTIAL using DevX API. 3259 * 3260 * @param[in] ctx 3261 * Context returned from mlx5 open_device() glue function. 3262 * @param [in] attr 3263 * Pointer to CREDENTIAL attributes structure. 3264 * 3265 * @return 3266 * The DevX object created, NULL otherwise and rte_errno is set. 3267 */ 3268 struct mlx5_devx_obj * 3269 mlx5_devx_cmd_create_credential_obj(void *ctx, 3270 struct mlx5_devx_credential_attr *attr) 3271 { 3272 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 3273 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3274 struct mlx5_devx_obj *credential_obj = NULL; 3275 void *ptr = NULL, *credential_addr = NULL; 3276 3277 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 3278 0, SOCKET_ID_ANY); 3279 if (credential_obj == NULL) { 3280 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 3281 rte_errno = ENOMEM; 3282 return NULL; 3283 } 3284 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 3285 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3286 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3287 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3288 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 3289 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 3290 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 3291 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 3292 memcpy(credential_addr, (void *)(attr->credential), 3293 MLX5_CRYPTO_CREDENTIAL_SIZE); 3294 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3295 out, sizeof(out)); 3296 if (credential_obj->obj == NULL) { 3297 DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0); 3298 mlx5_free(credential_obj); 3299 return NULL; 3300 } 3301 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3302 return credential_obj; 3303 } 3304 3305 /** 3306 * Create general object of type CRYPTO_LOGIN using DevX API. 3307 * 3308 * @param[in] ctx 3309 * Context returned from mlx5 open_device() glue function. 3310 * @param [in] attr 3311 * Pointer to CRYPTO_LOGIN attributes structure. 3312 * 3313 * @return 3314 * The DevX object created, NULL otherwise and rte_errno is set. 3315 */ 3316 struct mlx5_devx_obj * 3317 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 3318 struct mlx5_devx_crypto_login_attr *attr) 3319 { 3320 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 3321 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3322 struct mlx5_devx_obj *crypto_login_obj = NULL; 3323 void *ptr = NULL, *credential_addr = NULL; 3324 3325 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 3326 0, SOCKET_ID_ANY); 3327 if (crypto_login_obj == NULL) { 3328 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 3329 rte_errno = ENOMEM; 3330 return NULL; 3331 } 3332 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 3333 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3334 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3335 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3336 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 3337 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 3338 MLX5_SET(crypto_login, ptr, credential_pointer, 3339 attr->credential_pointer); 3340 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 3341 attr->session_import_kek_ptr); 3342 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 3343 memcpy(credential_addr, (void *)(attr->credential), 3344 MLX5_CRYPTO_CREDENTIAL_SIZE); 3345 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3346 out, sizeof(out)); 3347 if (crypto_login_obj->obj == NULL) { 3348 DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0); 3349 mlx5_free(crypto_login_obj); 3350 return NULL; 3351 } 3352 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3353 return crypto_login_obj; 3354 } 3355 3356 /** 3357 * Query LAG context. 3358 * 3359 * @param[in] ctx 3360 * Pointer to ibv_context, returned from mlx5dv_open_device. 3361 * @param[out] lag_ctx 3362 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 3363 * 3364 * @return 3365 * 0 on success, a negative value otherwise. 3366 */ 3367 int 3368 mlx5_devx_cmd_query_lag(void *ctx, 3369 struct mlx5_devx_lag_context *lag_ctx) 3370 { 3371 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 3372 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 3373 void *lctx; 3374 int rc; 3375 3376 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 3377 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 3378 if (rc) 3379 goto error; 3380 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 3381 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 3382 fdb_selection_mode); 3383 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 3384 port_select_mode); 3385 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 3386 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 3387 tx_remap_affinity_2); 3388 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 3389 tx_remap_affinity_1); 3390 return 0; 3391 error: 3392 rc = (rc > 0) ? -rc : rc; 3393 return rc; 3394 } 3395