1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_bus_auxiliary.h> 24 #include <rte_common.h> 25 #include <rte_kvargs.h> 26 #include <rte_rwlock.h> 27 #include <rte_spinlock.h> 28 #include <rte_string_fns.h> 29 #include <rte_alarm.h> 30 #include <rte_eal_paging.h> 31 32 #include <mlx5_glue.h> 33 #include <mlx5_devx_cmds.h> 34 #include <mlx5_common.h> 35 #include <mlx5_common_mp.h> 36 #include <mlx5_common_mr.h> 37 #include <mlx5_malloc.h> 38 39 #include "mlx5_defs.h" 40 #include "mlx5.h" 41 #include "mlx5_common_os.h" 42 #include "mlx5_utils.h" 43 #include "mlx5_rxtx.h" 44 #include "mlx5_rx.h" 45 #include "mlx5_tx.h" 46 #include "mlx5_autoconf.h" 47 #include "mlx5_mr.h" 48 #include "mlx5_flow.h" 49 #include "rte_pmd_mlx5.h" 50 #include "mlx5_verbs.h" 51 #include "mlx5_nl.h" 52 #include "mlx5_devx.h" 53 54 #ifndef HAVE_IBV_MLX5_MOD_MPW 55 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 56 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 57 #endif 58 59 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 60 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 61 #endif 62 63 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 64 65 /* Spinlock for mlx5_shared_data allocation. */ 66 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 67 68 /* Process local data for secondary processes. */ 69 static struct mlx5_local_data mlx5_local_data; 70 71 /* rte flow indexed pool configuration. */ 72 static struct mlx5_indexed_pool_config icfg[] = { 73 { 74 .size = sizeof(struct rte_flow), 75 .trunk_size = 64, 76 .need_lock = 1, 77 .release_mem_en = 0, 78 .malloc = mlx5_malloc, 79 .free = mlx5_free, 80 .per_core_cache = 0, 81 .type = "ctl_flow_ipool", 82 }, 83 { 84 .size = sizeof(struct rte_flow), 85 .trunk_size = 64, 86 .grow_trunk = 3, 87 .grow_shift = 2, 88 .need_lock = 1, 89 .release_mem_en = 0, 90 .malloc = mlx5_malloc, 91 .free = mlx5_free, 92 .per_core_cache = 1 << 14, 93 .type = "rte_flow_ipool", 94 }, 95 { 96 .size = sizeof(struct rte_flow), 97 .trunk_size = 64, 98 .grow_trunk = 3, 99 .grow_shift = 2, 100 .need_lock = 1, 101 .release_mem_en = 0, 102 .malloc = mlx5_malloc, 103 .free = mlx5_free, 104 .per_core_cache = 0, 105 .type = "mcp_flow_ipool", 106 }, 107 }; 108 109 /** 110 * Set the completion channel file descriptor interrupt as non-blocking. 111 * 112 * @param[in] rxq_obj 113 * Pointer to RQ channel object, which includes the channel fd 114 * 115 * @param[out] fd 116 * The file descriptor (representing the intetrrupt) used in this channel. 117 * 118 * @return 119 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 120 */ 121 int 122 mlx5_os_set_nonblock_channel_fd(int fd) 123 { 124 int flags; 125 126 flags = fcntl(fd, F_GETFL); 127 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 128 } 129 130 /** 131 * Get mlx5 device attributes. The glue function query_device_ex() is called 132 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 133 * device attributes from the glue out parameter. 134 * 135 * @param dev 136 * Pointer to ibv context. 137 * 138 * @param device_attr 139 * Pointer to mlx5 device attributes. 140 * 141 * @return 142 * 0 on success, non zero error number otherwise 143 */ 144 int 145 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 146 { 147 int err; 148 struct ibv_device_attr_ex attr_ex; 149 memset(device_attr, 0, sizeof(*device_attr)); 150 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 151 if (err) 152 return err; 153 154 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 155 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 156 device_attr->max_sge = attr_ex.orig_attr.max_sge; 157 device_attr->max_cq = attr_ex.orig_attr.max_cq; 158 device_attr->max_cqe = attr_ex.orig_attr.max_cqe; 159 device_attr->max_mr = attr_ex.orig_attr.max_mr; 160 device_attr->max_pd = attr_ex.orig_attr.max_pd; 161 device_attr->max_qp = attr_ex.orig_attr.max_qp; 162 device_attr->max_srq = attr_ex.orig_attr.max_srq; 163 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr; 164 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 165 device_attr->max_rwq_indirection_table_size = 166 attr_ex.rss_caps.max_rwq_indirection_table_size; 167 device_attr->max_tso = attr_ex.tso_caps.max_tso; 168 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 169 170 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 171 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 172 if (err) 173 return err; 174 175 device_attr->flags = dv_attr.flags; 176 device_attr->comp_mask = dv_attr.comp_mask; 177 #ifdef HAVE_IBV_MLX5_MOD_SWP 178 device_attr->sw_parsing_offloads = 179 dv_attr.sw_parsing_caps.sw_parsing_offloads; 180 #endif 181 device_attr->min_single_stride_log_num_of_bytes = 182 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 183 device_attr->max_single_stride_log_num_of_bytes = 184 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 185 device_attr->min_single_wqe_log_num_of_strides = 186 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 187 device_attr->max_single_wqe_log_num_of_strides = 188 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 189 device_attr->stride_supported_qpts = 190 dv_attr.striding_rq_caps.supported_qpts; 191 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 192 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 193 #endif 194 strlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver, 195 sizeof(device_attr->fw_ver)); 196 197 return err; 198 } 199 200 /** 201 * Verbs callback to allocate a memory. This function should allocate the space 202 * according to the size provided residing inside a huge page. 203 * Please note that all allocation must respect the alignment from libmlx5 204 * (i.e. currently rte_mem_page_size()). 205 * 206 * @param[in] size 207 * The size in bytes of the memory to allocate. 208 * @param[in] data 209 * A pointer to the callback data. 210 * 211 * @return 212 * Allocated buffer, NULL otherwise and rte_errno is set. 213 */ 214 static void * 215 mlx5_alloc_verbs_buf(size_t size, void *data) 216 { 217 struct mlx5_dev_ctx_shared *sh = data; 218 void *ret; 219 size_t alignment = rte_mem_page_size(); 220 if (alignment == (size_t)-1) { 221 DRV_LOG(ERR, "Failed to get mem page size"); 222 rte_errno = ENOMEM; 223 return NULL; 224 } 225 226 MLX5_ASSERT(data != NULL); 227 ret = mlx5_malloc(0, size, alignment, sh->numa_node); 228 if (!ret && size) 229 rte_errno = ENOMEM; 230 return ret; 231 } 232 233 /** 234 * Detect misc5 support or not 235 * 236 * @param[in] priv 237 * Device private data pointer 238 */ 239 #ifdef HAVE_MLX5DV_DR 240 static void 241 __mlx5_discovery_misc5_cap(struct mlx5_priv *priv) 242 { 243 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 244 /* Dummy VxLAN matcher to detect rdma-core misc5 cap 245 * Case: IPv4--->UDP--->VxLAN--->vni 246 */ 247 void *tbl; 248 struct mlx5_flow_dv_match_params matcher_mask; 249 void *match_m; 250 void *matcher; 251 void *headers_m; 252 void *misc5_m; 253 uint32_t *tunnel_header_m; 254 struct mlx5dv_flow_matcher_attr dv_attr; 255 256 memset(&matcher_mask, 0, sizeof(matcher_mask)); 257 matcher_mask.size = sizeof(matcher_mask.buf); 258 match_m = matcher_mask.buf; 259 headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers); 260 misc5_m = MLX5_ADDR_OF(fte_match_param, 261 match_m, misc_parameters_5); 262 tunnel_header_m = (uint32_t *) 263 MLX5_ADDR_OF(fte_match_set_misc5, 264 misc5_m, tunnel_header_1); 265 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff); 266 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4); 267 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff); 268 *tunnel_header_m = 0xffffff; 269 270 tbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1); 271 if (!tbl) { 272 DRV_LOG(INFO, "No SW steering support"); 273 return; 274 } 275 dv_attr.type = IBV_FLOW_ATTR_NORMAL, 276 dv_attr.match_mask = (void *)&matcher_mask, 277 dv_attr.match_criteria_enable = 278 (1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) | 279 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT); 280 dv_attr.priority = 3; 281 #ifdef HAVE_MLX5DV_DR_ESWITCH 282 void *misc2_m; 283 if (priv->config.dv_esw_en) { 284 /* FDB enabled reg_c_0 */ 285 dv_attr.match_criteria_enable |= 286 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT); 287 misc2_m = MLX5_ADDR_OF(fte_match_param, 288 match_m, misc_parameters_2); 289 MLX5_SET(fte_match_set_misc2, misc2_m, 290 metadata_reg_c_0, 0xffff); 291 } 292 #endif 293 matcher = mlx5_glue->dv_create_flow_matcher(priv->sh->ctx, 294 &dv_attr, tbl); 295 if (matcher) { 296 priv->sh->misc5_cap = 1; 297 mlx5_glue->dv_destroy_flow_matcher(matcher); 298 } 299 mlx5_glue->dr_destroy_flow_tbl(tbl); 300 #else 301 RTE_SET_USED(priv); 302 #endif 303 } 304 #endif 305 306 /** 307 * Verbs callback to free a memory. 308 * 309 * @param[in] ptr 310 * A pointer to the memory to free. 311 * @param[in] data 312 * A pointer to the callback data. 313 */ 314 static void 315 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 316 { 317 MLX5_ASSERT(data != NULL); 318 mlx5_free(ptr); 319 } 320 321 /** 322 * Initialize DR related data within private structure. 323 * Routine checks the reference counter and does actual 324 * resources creation/initialization only if counter is zero. 325 * 326 * @param[in] priv 327 * Pointer to the private device data structure. 328 * 329 * @return 330 * Zero on success, positive error code otherwise. 331 */ 332 static int 333 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 334 { 335 struct mlx5_dev_ctx_shared *sh = priv->sh; 336 char s[MLX5_NAME_SIZE] __rte_unused; 337 int err; 338 339 MLX5_ASSERT(sh && sh->refcnt); 340 if (sh->refcnt > 1) 341 return 0; 342 err = mlx5_alloc_table_hash_list(priv); 343 if (err) 344 goto error; 345 /* The resources below are only valid with DV support. */ 346 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 347 /* Init port id action list. */ 348 snprintf(s, sizeof(s), "%s_port_id_action_list", sh->ibdev_name); 349 sh->port_id_action_list = mlx5_list_create(s, sh, true, 350 flow_dv_port_id_create_cb, 351 flow_dv_port_id_match_cb, 352 flow_dv_port_id_remove_cb, 353 flow_dv_port_id_clone_cb, 354 flow_dv_port_id_clone_free_cb); 355 if (!sh->port_id_action_list) 356 goto error; 357 /* Init push vlan action list. */ 358 snprintf(s, sizeof(s), "%s_push_vlan_action_list", sh->ibdev_name); 359 sh->push_vlan_action_list = mlx5_list_create(s, sh, true, 360 flow_dv_push_vlan_create_cb, 361 flow_dv_push_vlan_match_cb, 362 flow_dv_push_vlan_remove_cb, 363 flow_dv_push_vlan_clone_cb, 364 flow_dv_push_vlan_clone_free_cb); 365 if (!sh->push_vlan_action_list) 366 goto error; 367 /* Init sample action list. */ 368 snprintf(s, sizeof(s), "%s_sample_action_list", sh->ibdev_name); 369 sh->sample_action_list = mlx5_list_create(s, sh, true, 370 flow_dv_sample_create_cb, 371 flow_dv_sample_match_cb, 372 flow_dv_sample_remove_cb, 373 flow_dv_sample_clone_cb, 374 flow_dv_sample_clone_free_cb); 375 if (!sh->sample_action_list) 376 goto error; 377 /* Init dest array action list. */ 378 snprintf(s, sizeof(s), "%s_dest_array_list", sh->ibdev_name); 379 sh->dest_array_list = mlx5_list_create(s, sh, true, 380 flow_dv_dest_array_create_cb, 381 flow_dv_dest_array_match_cb, 382 flow_dv_dest_array_remove_cb, 383 flow_dv_dest_array_clone_cb, 384 flow_dv_dest_array_clone_free_cb); 385 if (!sh->dest_array_list) 386 goto error; 387 #endif 388 #ifdef HAVE_MLX5DV_DR 389 void *domain; 390 391 /* Reference counter is zero, we should initialize structures. */ 392 domain = mlx5_glue->dr_create_domain(sh->ctx, 393 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 394 if (!domain) { 395 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 396 err = errno; 397 goto error; 398 } 399 sh->rx_domain = domain; 400 domain = mlx5_glue->dr_create_domain(sh->ctx, 401 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 402 if (!domain) { 403 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 404 err = errno; 405 goto error; 406 } 407 sh->tx_domain = domain; 408 #ifdef HAVE_MLX5DV_DR_ESWITCH 409 if (priv->config.dv_esw_en) { 410 domain = mlx5_glue->dr_create_domain 411 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 412 if (!domain) { 413 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 414 err = errno; 415 goto error; 416 } 417 sh->fdb_domain = domain; 418 } 419 /* 420 * The drop action is just some dummy placeholder in rdma-core. It 421 * does not belong to domains and has no any attributes, and, can be 422 * shared by the entire device. 423 */ 424 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop(); 425 if (!sh->dr_drop_action) { 426 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop"); 427 err = errno; 428 goto error; 429 } 430 #endif 431 if (!sh->tunnel_hub && priv->config.dv_miss_info) 432 err = mlx5_alloc_tunnel_hub(sh); 433 if (err) { 434 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 435 goto error; 436 } 437 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 438 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 439 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 440 if (sh->fdb_domain) 441 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 442 } 443 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 444 if (!priv->config.allow_duplicate_pattern) { 445 #ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE 446 DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?"); 447 #endif 448 mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0); 449 mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0); 450 if (sh->fdb_domain) 451 mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0); 452 } 453 454 __mlx5_discovery_misc5_cap(priv); 455 #endif /* HAVE_MLX5DV_DR */ 456 sh->default_miss_action = 457 mlx5_glue->dr_create_flow_action_default_miss(); 458 if (!sh->default_miss_action) 459 DRV_LOG(WARNING, "Default miss action is not supported."); 460 return 0; 461 error: 462 /* Rollback the created objects. */ 463 if (sh->rx_domain) { 464 mlx5_glue->dr_destroy_domain(sh->rx_domain); 465 sh->rx_domain = NULL; 466 } 467 if (sh->tx_domain) { 468 mlx5_glue->dr_destroy_domain(sh->tx_domain); 469 sh->tx_domain = NULL; 470 } 471 if (sh->fdb_domain) { 472 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 473 sh->fdb_domain = NULL; 474 } 475 if (sh->dr_drop_action) { 476 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 477 sh->dr_drop_action = NULL; 478 } 479 if (sh->pop_vlan_action) { 480 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 481 sh->pop_vlan_action = NULL; 482 } 483 if (sh->encaps_decaps) { 484 mlx5_hlist_destroy(sh->encaps_decaps); 485 sh->encaps_decaps = NULL; 486 } 487 if (sh->modify_cmds) { 488 mlx5_hlist_destroy(sh->modify_cmds); 489 sh->modify_cmds = NULL; 490 } 491 if (sh->tag_table) { 492 /* tags should be destroyed with flow before. */ 493 mlx5_hlist_destroy(sh->tag_table); 494 sh->tag_table = NULL; 495 } 496 if (sh->tunnel_hub) { 497 mlx5_release_tunnel_hub(sh, priv->dev_port); 498 sh->tunnel_hub = NULL; 499 } 500 mlx5_free_table_hash_list(priv); 501 if (sh->port_id_action_list) { 502 mlx5_list_destroy(sh->port_id_action_list); 503 sh->port_id_action_list = NULL; 504 } 505 if (sh->push_vlan_action_list) { 506 mlx5_list_destroy(sh->push_vlan_action_list); 507 sh->push_vlan_action_list = NULL; 508 } 509 if (sh->sample_action_list) { 510 mlx5_list_destroy(sh->sample_action_list); 511 sh->sample_action_list = NULL; 512 } 513 if (sh->dest_array_list) { 514 mlx5_list_destroy(sh->dest_array_list); 515 sh->dest_array_list = NULL; 516 } 517 return err; 518 } 519 520 /** 521 * Destroy DR related data within private structure. 522 * 523 * @param[in] priv 524 * Pointer to the private device data structure. 525 */ 526 void 527 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 528 { 529 struct mlx5_dev_ctx_shared *sh = priv->sh; 530 531 MLX5_ASSERT(sh && sh->refcnt); 532 if (sh->refcnt > 1) 533 return; 534 #ifdef HAVE_MLX5DV_DR 535 if (sh->rx_domain) { 536 mlx5_glue->dr_destroy_domain(sh->rx_domain); 537 sh->rx_domain = NULL; 538 } 539 if (sh->tx_domain) { 540 mlx5_glue->dr_destroy_domain(sh->tx_domain); 541 sh->tx_domain = NULL; 542 } 543 #ifdef HAVE_MLX5DV_DR_ESWITCH 544 if (sh->fdb_domain) { 545 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 546 sh->fdb_domain = NULL; 547 } 548 if (sh->dr_drop_action) { 549 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 550 sh->dr_drop_action = NULL; 551 } 552 #endif 553 if (sh->pop_vlan_action) { 554 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 555 sh->pop_vlan_action = NULL; 556 } 557 #endif /* HAVE_MLX5DV_DR */ 558 if (sh->default_miss_action) 559 mlx5_glue->destroy_flow_action 560 (sh->default_miss_action); 561 if (sh->encaps_decaps) { 562 mlx5_hlist_destroy(sh->encaps_decaps); 563 sh->encaps_decaps = NULL; 564 } 565 if (sh->modify_cmds) { 566 mlx5_hlist_destroy(sh->modify_cmds); 567 sh->modify_cmds = NULL; 568 } 569 if (sh->tag_table) { 570 /* tags should be destroyed with flow before. */ 571 mlx5_hlist_destroy(sh->tag_table); 572 sh->tag_table = NULL; 573 } 574 if (sh->tunnel_hub) { 575 mlx5_release_tunnel_hub(sh, priv->dev_port); 576 sh->tunnel_hub = NULL; 577 } 578 mlx5_free_table_hash_list(priv); 579 if (sh->port_id_action_list) { 580 mlx5_list_destroy(sh->port_id_action_list); 581 sh->port_id_action_list = NULL; 582 } 583 if (sh->push_vlan_action_list) { 584 mlx5_list_destroy(sh->push_vlan_action_list); 585 sh->push_vlan_action_list = NULL; 586 } 587 if (sh->sample_action_list) { 588 mlx5_list_destroy(sh->sample_action_list); 589 sh->sample_action_list = NULL; 590 } 591 if (sh->dest_array_list) { 592 mlx5_list_destroy(sh->dest_array_list); 593 sh->dest_array_list = NULL; 594 } 595 } 596 597 /** 598 * Initialize shared data between primary and secondary process. 599 * 600 * A memzone is reserved by primary process and secondary processes attach to 601 * the memzone. 602 * 603 * @return 604 * 0 on success, a negative errno value otherwise and rte_errno is set. 605 */ 606 static int 607 mlx5_init_shared_data(void) 608 { 609 const struct rte_memzone *mz; 610 int ret = 0; 611 612 rte_spinlock_lock(&mlx5_shared_data_lock); 613 if (mlx5_shared_data == NULL) { 614 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 615 /* Allocate shared memory. */ 616 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 617 sizeof(*mlx5_shared_data), 618 SOCKET_ID_ANY, 0); 619 if (mz == NULL) { 620 DRV_LOG(ERR, 621 "Cannot allocate mlx5 shared data"); 622 ret = -rte_errno; 623 goto error; 624 } 625 mlx5_shared_data = mz->addr; 626 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 627 rte_spinlock_init(&mlx5_shared_data->lock); 628 } else { 629 /* Lookup allocated shared memory. */ 630 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 631 if (mz == NULL) { 632 DRV_LOG(ERR, 633 "Cannot attach mlx5 shared data"); 634 ret = -rte_errno; 635 goto error; 636 } 637 mlx5_shared_data = mz->addr; 638 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 639 } 640 } 641 error: 642 rte_spinlock_unlock(&mlx5_shared_data_lock); 643 return ret; 644 } 645 646 /** 647 * PMD global initialization. 648 * 649 * Independent from individual device, this function initializes global 650 * per-PMD data structures distinguishing primary and secondary processes. 651 * Hence, each initialization is called once per a process. 652 * 653 * @return 654 * 0 on success, a negative errno value otherwise and rte_errno is set. 655 */ 656 static int 657 mlx5_init_once(void) 658 { 659 struct mlx5_shared_data *sd; 660 struct mlx5_local_data *ld = &mlx5_local_data; 661 int ret = 0; 662 663 if (mlx5_init_shared_data()) 664 return -rte_errno; 665 sd = mlx5_shared_data; 666 MLX5_ASSERT(sd); 667 rte_spinlock_lock(&sd->lock); 668 switch (rte_eal_process_type()) { 669 case RTE_PROC_PRIMARY: 670 if (sd->init_done) 671 break; 672 LIST_INIT(&sd->mem_event_cb_list); 673 rte_rwlock_init(&sd->mem_event_rwlock); 674 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 675 mlx5_mr_mem_event_cb, NULL); 676 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 677 mlx5_mp_os_primary_handle); 678 if (ret) 679 goto out; 680 sd->init_done = true; 681 break; 682 case RTE_PROC_SECONDARY: 683 if (ld->init_done) 684 break; 685 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 686 mlx5_mp_os_secondary_handle); 687 if (ret) 688 goto out; 689 ++sd->secondary_cnt; 690 ld->init_done = true; 691 break; 692 default: 693 break; 694 } 695 out: 696 rte_spinlock_unlock(&sd->lock); 697 return ret; 698 } 699 700 /** 701 * Create the Tx queue DevX/Verbs object. 702 * 703 * @param dev 704 * Pointer to Ethernet device. 705 * @param idx 706 * Queue index in DPDK Tx queue array. 707 * 708 * @return 709 * 0 on success, a negative errno value otherwise and rte_errno is set. 710 */ 711 static int 712 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 713 { 714 struct mlx5_priv *priv = dev->data->dev_private; 715 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 716 struct mlx5_txq_ctrl *txq_ctrl = 717 container_of(txq_data, struct mlx5_txq_ctrl, txq); 718 719 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 720 return mlx5_txq_devx_obj_new(dev, idx); 721 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 722 if (!priv->config.dv_esw_en) 723 return mlx5_txq_devx_obj_new(dev, idx); 724 #endif 725 return mlx5_txq_ibv_obj_new(dev, idx); 726 } 727 728 /** 729 * Release an Tx DevX/verbs queue object. 730 * 731 * @param txq_obj 732 * DevX/Verbs Tx queue object. 733 */ 734 static void 735 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 736 { 737 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 738 mlx5_txq_devx_obj_release(txq_obj); 739 return; 740 } 741 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 742 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { 743 mlx5_txq_devx_obj_release(txq_obj); 744 return; 745 } 746 #endif 747 mlx5_txq_ibv_obj_release(txq_obj); 748 } 749 750 /** 751 * DV flow counter mode detect and config. 752 * 753 * @param dev 754 * Pointer to rte_eth_dev structure. 755 * 756 */ 757 static void 758 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 759 { 760 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 761 struct mlx5_priv *priv = dev->data->dev_private; 762 struct mlx5_dev_ctx_shared *sh = priv->sh; 763 bool fallback; 764 765 #ifndef HAVE_IBV_DEVX_ASYNC 766 fallback = true; 767 #else 768 fallback = false; 769 if (!priv->config.devx || !priv->config.dv_flow_en || 770 !priv->config.hca_attr.flow_counters_dump || 771 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 772 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 773 fallback = true; 774 #endif 775 if (fallback) 776 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 777 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 778 priv->config.hca_attr.flow_counters_dump, 779 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 780 /* Initialize fallback mode only on the port initializes sh. */ 781 if (sh->refcnt == 1) 782 sh->cmng.counter_fallback = fallback; 783 else if (fallback != sh->cmng.counter_fallback) 784 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 785 "with others:%d.", PORT_ID(priv), fallback); 786 #endif 787 } 788 789 /** 790 * DR flow drop action support detect. 791 * 792 * @param dev 793 * Pointer to rte_eth_dev structure. 794 * 795 */ 796 static void 797 mlx5_flow_drop_action_config(struct rte_eth_dev *dev __rte_unused) 798 { 799 #ifdef HAVE_MLX5DV_DR 800 struct mlx5_priv *priv = dev->data->dev_private; 801 802 if (!priv->config.dv_flow_en || !priv->sh->dr_drop_action) 803 return; 804 /** 805 * DR supports drop action placeholder when it is supported; 806 * otherwise, use the queue drop action. 807 */ 808 if (mlx5_flow_discover_dr_action_support(dev)) 809 priv->root_drop_action = priv->drop_queue.hrxq->action; 810 else 811 priv->root_drop_action = priv->sh->dr_drop_action; 812 #endif 813 } 814 815 static void 816 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 817 { 818 struct mlx5_priv *priv = dev->data->dev_private; 819 void *ctx = priv->sh->ctx; 820 821 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 822 if (!priv->q_counters) { 823 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 824 struct ibv_wq *wq; 825 826 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 827 "by DevX - fall-back to use the kernel driver global " 828 "queue counter.", dev->data->port_id); 829 /* Create WQ by kernel and query its queue counter ID. */ 830 if (cq) { 831 wq = mlx5_glue->create_wq(ctx, 832 &(struct ibv_wq_init_attr){ 833 .wq_type = IBV_WQT_RQ, 834 .max_wr = 1, 835 .max_sge = 1, 836 .pd = priv->sh->pd, 837 .cq = cq, 838 }); 839 if (wq) { 840 /* Counter is assigned only on RDY state. */ 841 int ret = mlx5_glue->modify_wq(wq, 842 &(struct ibv_wq_attr){ 843 .attr_mask = IBV_WQ_ATTR_STATE, 844 .wq_state = IBV_WQS_RDY, 845 }); 846 847 if (ret == 0) 848 mlx5_devx_cmd_wq_query(wq, 849 &priv->counter_set_id); 850 claim_zero(mlx5_glue->destroy_wq(wq)); 851 } 852 claim_zero(mlx5_glue->destroy_cq(cq)); 853 } 854 } else { 855 priv->counter_set_id = priv->q_counters->id; 856 } 857 if (priv->counter_set_id == 0) 858 DRV_LOG(INFO, "Part of the port %d statistics will not be " 859 "available.", dev->data->port_id); 860 } 861 862 /** 863 * Check if representor spawn info match devargs. 864 * 865 * @param spawn 866 * Verbs device parameters (name, port, switch_info) to spawn. 867 * @param eth_da 868 * Device devargs to probe. 869 * 870 * @return 871 * Match result. 872 */ 873 static bool 874 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 875 struct rte_eth_devargs *eth_da) 876 { 877 struct mlx5_switch_info *switch_info = &spawn->info; 878 unsigned int p, f; 879 uint16_t id; 880 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 881 eth_da->type); 882 883 switch (eth_da->type) { 884 case RTE_ETH_REPRESENTOR_SF: 885 if (!(spawn->info.port_name == -1 && 886 switch_info->name_type == 887 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 888 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 889 rte_errno = EBUSY; 890 return false; 891 } 892 break; 893 case RTE_ETH_REPRESENTOR_VF: 894 /* Allows HPF representor index -1 as exception. */ 895 if (!(spawn->info.port_name == -1 && 896 switch_info->name_type == 897 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 898 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 899 rte_errno = EBUSY; 900 return false; 901 } 902 break; 903 case RTE_ETH_REPRESENTOR_NONE: 904 rte_errno = EBUSY; 905 return false; 906 default: 907 rte_errno = ENOTSUP; 908 DRV_LOG(ERR, "unsupported representor type"); 909 return false; 910 } 911 /* Check representor ID: */ 912 for (p = 0; p < eth_da->nb_ports; ++p) { 913 if (spawn->pf_bond < 0) { 914 /* For non-LAG mode, allow and ignore pf. */ 915 switch_info->pf_num = eth_da->ports[p]; 916 repr_id = mlx5_representor_id_encode(switch_info, 917 eth_da->type); 918 } 919 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 920 id = MLX5_REPRESENTOR_ID 921 (eth_da->ports[p], eth_da->type, 922 eth_da->representor_ports[f]); 923 if (repr_id == id) 924 return true; 925 } 926 } 927 rte_errno = EBUSY; 928 return false; 929 } 930 931 932 /** 933 * Spawn an Ethernet device from Verbs information. 934 * 935 * @param dpdk_dev 936 * Backing DPDK device. 937 * @param spawn 938 * Verbs device parameters (name, port, switch_info) to spawn. 939 * @param config 940 * Device configuration parameters. 941 * @param config 942 * Device arguments. 943 * 944 * @return 945 * A valid Ethernet device object on success, NULL otherwise and rte_errno 946 * is set. The following errors are defined: 947 * 948 * EBUSY: device is not supposed to be spawned. 949 * EEXIST: device is already spawned 950 */ 951 static struct rte_eth_dev * 952 mlx5_dev_spawn(struct rte_device *dpdk_dev, 953 struct mlx5_dev_spawn_data *spawn, 954 struct mlx5_dev_config *config, 955 struct rte_eth_devargs *eth_da) 956 { 957 const struct mlx5_switch_info *switch_info = &spawn->info; 958 struct mlx5_dev_ctx_shared *sh = NULL; 959 struct ibv_port_attr port_attr; 960 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 961 struct rte_eth_dev *eth_dev = NULL; 962 struct mlx5_priv *priv = NULL; 963 int err = 0; 964 unsigned int hw_padding = 0; 965 unsigned int mps; 966 unsigned int tunnel_en = 0; 967 unsigned int mpls_en = 0; 968 unsigned int swp = 0; 969 unsigned int mprq = 0; 970 unsigned int mprq_min_stride_size_n = 0; 971 unsigned int mprq_max_stride_size_n = 0; 972 unsigned int mprq_min_stride_num_n = 0; 973 unsigned int mprq_max_stride_num_n = 0; 974 struct rte_ether_addr mac; 975 char name[RTE_ETH_NAME_MAX_LEN]; 976 int own_domain_id = 0; 977 uint16_t port_id; 978 struct mlx5_port_info vport_info = { .query_flags = 0 }; 979 int i; 980 981 /* Determine if this port representor is supposed to be spawned. */ 982 if (switch_info->representor && dpdk_dev->devargs && 983 !mlx5_representor_match(spawn, eth_da)) 984 return NULL; 985 /* Build device name. */ 986 if (spawn->pf_bond < 0) { 987 /* Single device. */ 988 if (!switch_info->representor) 989 strlcpy(name, dpdk_dev->name, sizeof(name)); 990 else 991 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 992 dpdk_dev->name, 993 switch_info->name_type == 994 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 995 switch_info->port_name); 996 } else { 997 /* Bonding device. */ 998 if (!switch_info->representor) { 999 err = snprintf(name, sizeof(name), "%s_%s", 1000 dpdk_dev->name, 1001 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1002 } else { 1003 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 1004 dpdk_dev->name, 1005 mlx5_os_get_dev_device_name(spawn->phys_dev), 1006 switch_info->ctrl_num, 1007 switch_info->pf_num, 1008 switch_info->name_type == 1009 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 1010 switch_info->port_name); 1011 } 1012 } 1013 if (err >= (int)sizeof(name)) 1014 DRV_LOG(WARNING, "device name overflow %s", name); 1015 /* check if the device is already spawned */ 1016 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 1017 rte_errno = EEXIST; 1018 return NULL; 1019 } 1020 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 1021 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 1022 struct mlx5_mp_id mp_id; 1023 1024 eth_dev = rte_eth_dev_attach_secondary(name); 1025 if (eth_dev == NULL) { 1026 DRV_LOG(ERR, "can not attach rte ethdev"); 1027 rte_errno = ENOMEM; 1028 return NULL; 1029 } 1030 eth_dev->device = dpdk_dev; 1031 eth_dev->dev_ops = &mlx5_dev_sec_ops; 1032 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1033 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1034 err = mlx5_proc_priv_init(eth_dev); 1035 if (err) 1036 return NULL; 1037 mp_id.port_id = eth_dev->data->port_id; 1038 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1039 /* Receive command fd from primary process */ 1040 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 1041 if (err < 0) 1042 goto err_secondary; 1043 /* Remap UAR for Tx queues. */ 1044 err = mlx5_tx_uar_init_secondary(eth_dev, err); 1045 if (err) 1046 goto err_secondary; 1047 /* 1048 * Ethdev pointer is still required as input since 1049 * the primary device is not accessible from the 1050 * secondary process. 1051 */ 1052 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 1053 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 1054 return eth_dev; 1055 err_secondary: 1056 mlx5_dev_close(eth_dev); 1057 return NULL; 1058 } 1059 /* 1060 * Some parameters ("tx_db_nc" in particularly) are needed in 1061 * advance to create dv/verbs device context. We proceed the 1062 * devargs here to get ones, and later proceed devargs again 1063 * to override some hardware settings. 1064 */ 1065 err = mlx5_args(config, dpdk_dev->devargs); 1066 if (err) { 1067 err = rte_errno; 1068 DRV_LOG(ERR, "failed to process device arguments: %s", 1069 strerror(rte_errno)); 1070 goto error; 1071 } 1072 if (config->dv_miss_info) { 1073 if (switch_info->master || switch_info->representor) 1074 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 1075 } 1076 mlx5_malloc_mem_select(config->sys_mem_en); 1077 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 1078 if (!sh) 1079 return NULL; 1080 config->devx = sh->devx; 1081 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 1082 config->dest_tir = 1; 1083 #endif 1084 #ifdef HAVE_IBV_MLX5_MOD_SWP 1085 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 1086 #endif 1087 /* 1088 * Multi-packet send is supported by ConnectX-4 Lx PF as well 1089 * as all ConnectX-5 devices. 1090 */ 1091 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1092 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 1093 #endif 1094 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1095 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 1096 #endif 1097 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 1098 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 1099 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 1100 DRV_LOG(DEBUG, "enhanced MPW is supported"); 1101 mps = MLX5_MPW_ENHANCED; 1102 } else { 1103 DRV_LOG(DEBUG, "MPW is supported"); 1104 mps = MLX5_MPW; 1105 } 1106 } else { 1107 DRV_LOG(DEBUG, "MPW isn't supported"); 1108 mps = MLX5_MPW_DISABLED; 1109 } 1110 #ifdef HAVE_IBV_MLX5_MOD_SWP 1111 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 1112 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 1113 DRV_LOG(DEBUG, "SWP support: %u", swp); 1114 #endif 1115 config->swp = !!swp; 1116 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1117 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 1118 struct mlx5dv_striding_rq_caps mprq_caps = 1119 dv_attr.striding_rq_caps; 1120 1121 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 1122 mprq_caps.min_single_stride_log_num_of_bytes); 1123 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 1124 mprq_caps.max_single_stride_log_num_of_bytes); 1125 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 1126 mprq_caps.min_single_wqe_log_num_of_strides); 1127 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 1128 mprq_caps.max_single_wqe_log_num_of_strides); 1129 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 1130 mprq_caps.supported_qpts); 1131 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 1132 mprq = 1; 1133 mprq_min_stride_size_n = 1134 mprq_caps.min_single_stride_log_num_of_bytes; 1135 mprq_max_stride_size_n = 1136 mprq_caps.max_single_stride_log_num_of_bytes; 1137 mprq_min_stride_num_n = 1138 mprq_caps.min_single_wqe_log_num_of_strides; 1139 mprq_max_stride_num_n = 1140 mprq_caps.max_single_wqe_log_num_of_strides; 1141 } 1142 #endif 1143 /* Rx CQE compression is enabled by default. */ 1144 config->cqe_comp = 1; 1145 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1146 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 1147 tunnel_en = ((dv_attr.tunnel_offloads_caps & 1148 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 1149 (dv_attr.tunnel_offloads_caps & 1150 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 1151 (dv_attr.tunnel_offloads_caps & 1152 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 1153 } 1154 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 1155 tunnel_en ? "" : "not "); 1156 #else 1157 DRV_LOG(WARNING, 1158 "tunnel offloading disabled due to old OFED/rdma-core version"); 1159 #endif 1160 config->tunnel_en = tunnel_en; 1161 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1162 mpls_en = ((dv_attr.tunnel_offloads_caps & 1163 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1164 (dv_attr.tunnel_offloads_caps & 1165 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1166 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1167 mpls_en ? "" : "not "); 1168 #else 1169 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1170 " old OFED/rdma-core version or firmware configuration"); 1171 #endif 1172 config->mpls_en = mpls_en; 1173 /* Check port status. */ 1174 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 1175 if (err) { 1176 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1177 goto error; 1178 } 1179 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1180 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1181 err = EINVAL; 1182 goto error; 1183 } 1184 if (port_attr.state != IBV_PORT_ACTIVE) 1185 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 1186 mlx5_glue->port_state_str(port_attr.state), 1187 port_attr.state); 1188 /* Allocate private eth device data. */ 1189 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1190 sizeof(*priv), 1191 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1192 if (priv == NULL) { 1193 DRV_LOG(ERR, "priv allocation failure"); 1194 err = ENOMEM; 1195 goto error; 1196 } 1197 priv->sh = sh; 1198 priv->dev_port = spawn->phys_port; 1199 priv->pci_dev = spawn->pci_dev; 1200 priv->mtu = RTE_ETHER_MTU; 1201 /* Some internal functions rely on Netlink sockets, open them now. */ 1202 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 1203 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1204 priv->representor = !!switch_info->representor; 1205 priv->master = !!switch_info->master; 1206 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1207 priv->vport_meta_tag = 0; 1208 priv->vport_meta_mask = 0; 1209 priv->pf_bond = spawn->pf_bond; 1210 1211 DRV_LOG(DEBUG, 1212 "dev_port=%u bus=%s pci=%s master=%d representor=%d pf_bond=%d\n", 1213 priv->dev_port, dpdk_dev->bus->name, 1214 priv->pci_dev ? priv->pci_dev->name : "NONE", 1215 priv->master, priv->representor, priv->pf_bond); 1216 1217 /* 1218 * If we have E-Switch we should determine the vport attributes. 1219 * E-Switch may use either source vport field or reg_c[0] metadata 1220 * register to match on vport index. The engaged part of metadata 1221 * register is defined by mask. 1222 */ 1223 if (switch_info->representor || switch_info->master) { 1224 err = mlx5_glue->devx_port_query(sh->ctx, 1225 spawn->phys_port, 1226 &vport_info); 1227 if (err) { 1228 DRV_LOG(WARNING, 1229 "can't query devx port %d on device %s", 1230 spawn->phys_port, 1231 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1232 vport_info.query_flags = 0; 1233 } 1234 } 1235 if (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) { 1236 priv->vport_meta_tag = vport_info.vport_meta_tag; 1237 priv->vport_meta_mask = vport_info.vport_meta_mask; 1238 if (!priv->vport_meta_mask) { 1239 DRV_LOG(ERR, "vport zero mask for port %d" 1240 " on bonding device %s", 1241 spawn->phys_port, 1242 mlx5_os_get_dev_device_name 1243 (spawn->phys_dev)); 1244 err = ENOTSUP; 1245 goto error; 1246 } 1247 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1248 DRV_LOG(ERR, "invalid vport tag for port %d" 1249 " on bonding device %s", 1250 spawn->phys_port, 1251 mlx5_os_get_dev_device_name 1252 (spawn->phys_dev)); 1253 err = ENOTSUP; 1254 goto error; 1255 } 1256 } 1257 if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) { 1258 priv->vport_id = vport_info.vport_id; 1259 } else if (spawn->pf_bond >= 0 && 1260 (switch_info->representor || switch_info->master)) { 1261 DRV_LOG(ERR, "can't deduce vport index for port %d" 1262 " on bonding device %s", 1263 spawn->phys_port, 1264 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1265 err = ENOTSUP; 1266 goto error; 1267 } else { 1268 /* 1269 * Suppose vport index in compatible way. Kernel/rdma_core 1270 * support single E-Switch per PF configurations only and 1271 * vport_id field contains the vport index for associated VF, 1272 * which is deduced from representor port name. 1273 * For example, let's have the IB device port 10, it has 1274 * attached network device eth0, which has port name attribute 1275 * pf0vf2, we can deduce the VF number as 2, and set vport index 1276 * as 3 (2+1). This assigning schema should be changed if the 1277 * multiple E-Switch instances per PF configurations or/and PCI 1278 * subfunctions are added. 1279 */ 1280 priv->vport_id = switch_info->representor ? 1281 switch_info->port_name + 1 : -1; 1282 } 1283 priv->representor_id = mlx5_representor_id_encode(switch_info, 1284 eth_da->type); 1285 /* 1286 * Look for sibling devices in order to reuse their switch domain 1287 * if any, otherwise allocate one. 1288 */ 1289 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1290 const struct mlx5_priv *opriv = 1291 rte_eth_devices[port_id].data->dev_private; 1292 1293 if (!opriv || 1294 opriv->sh != priv->sh || 1295 opriv->domain_id == 1296 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1297 continue; 1298 priv->domain_id = opriv->domain_id; 1299 DRV_LOG(DEBUG, "dev_port-%u inherit domain_id=%u\n", 1300 priv->dev_port, priv->domain_id); 1301 break; 1302 } 1303 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1304 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1305 if (err) { 1306 err = rte_errno; 1307 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1308 strerror(rte_errno)); 1309 goto error; 1310 } 1311 own_domain_id = 1; 1312 DRV_LOG(DEBUG, "dev_port-%u new domain_id=%u\n", 1313 priv->dev_port, priv->domain_id); 1314 } 1315 /* Override some values set by hardware configuration. */ 1316 mlx5_args(config, dpdk_dev->devargs); 1317 err = mlx5_dev_check_sibling_config(priv, config, dpdk_dev); 1318 if (err) 1319 goto error; 1320 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1321 IBV_DEVICE_RAW_IP_CSUM); 1322 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1323 (config->hw_csum ? "" : "not ")); 1324 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1325 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1326 DRV_LOG(DEBUG, "counters are not supported"); 1327 #endif 1328 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1329 if (config->dv_flow_en) { 1330 DRV_LOG(WARNING, "DV flow is not supported"); 1331 config->dv_flow_en = 0; 1332 } 1333 #endif 1334 if (spawn->max_port > UINT8_MAX) { 1335 /* Verbs can't support ports larger than 255 by design. */ 1336 DRV_LOG(ERR, "can't support IB ports > UINT8_MAX"); 1337 err = EINVAL; 1338 goto error; 1339 } 1340 config->ind_table_max_size = 1341 sh->device_attr.max_rwq_indirection_table_size; 1342 /* 1343 * Remove this check once DPDK supports larger/variable 1344 * indirection tables. 1345 */ 1346 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1347 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1348 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1349 config->ind_table_max_size); 1350 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1351 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1352 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1353 (config->hw_vlan_strip ? "" : "not ")); 1354 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1355 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1356 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1357 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1358 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1359 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1360 IBV_DEVICE_PCI_WRITE_END_PADDING); 1361 #endif 1362 if (config->hw_padding && !hw_padding) { 1363 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1364 config->hw_padding = 0; 1365 } else if (config->hw_padding) { 1366 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1367 } 1368 config->tso = (sh->device_attr.max_tso > 0 && 1369 (sh->device_attr.tso_supported_qpts & 1370 (1 << IBV_QPT_RAW_PACKET))); 1371 if (config->tso) 1372 config->tso_max_payload_sz = sh->device_attr.max_tso; 1373 /* 1374 * MPW is disabled by default, while the Enhanced MPW is enabled 1375 * by default. 1376 */ 1377 if (config->mps == MLX5_ARG_UNSET) 1378 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1379 MLX5_MPW_DISABLED; 1380 else 1381 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1382 DRV_LOG(INFO, "%sMPS is %s", 1383 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1384 config->mps == MLX5_MPW ? "legacy " : "", 1385 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1386 if (config->devx) { 1387 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1388 if (err) { 1389 err = -err; 1390 goto error; 1391 } 1392 /* Check relax ordering support. */ 1393 if (!haswell_broadwell_cpu) { 1394 sh->cmng.relaxed_ordering_write = 1395 config->hca_attr.relaxed_ordering_write; 1396 sh->cmng.relaxed_ordering_read = 1397 config->hca_attr.relaxed_ordering_read; 1398 } else { 1399 sh->cmng.relaxed_ordering_read = 0; 1400 sh->cmng.relaxed_ordering_write = 0; 1401 } 1402 sh->rq_ts_format = config->hca_attr.rq_ts_format; 1403 sh->sq_ts_format = config->hca_attr.sq_ts_format; 1404 sh->steering_format_version = 1405 config->hca_attr.steering_format_version; 1406 sh->qp_ts_format = config->hca_attr.qp_ts_format; 1407 /* Check for LRO support. */ 1408 if (config->dest_tir && config->hca_attr.lro_cap && 1409 config->dv_flow_en) { 1410 /* TBD check tunnel lro caps. */ 1411 config->lro.supported = config->hca_attr.lro_cap; 1412 DRV_LOG(DEBUG, "Device supports LRO"); 1413 /* 1414 * If LRO timeout is not configured by application, 1415 * use the minimal supported value. 1416 */ 1417 if (!config->lro.timeout) 1418 config->lro.timeout = 1419 config->hca_attr.lro_timer_supported_periods[0]; 1420 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1421 config->lro.timeout); 1422 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1423 "required for coalescing is %d bytes", 1424 config->hca_attr.lro_min_mss_size); 1425 } 1426 #if defined(HAVE_MLX5DV_DR) && \ 1427 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1428 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1429 if (config->hca_attr.qos.sup && 1430 config->hca_attr.qos.flow_meter_old && 1431 config->dv_flow_en) { 1432 uint8_t reg_c_mask = 1433 config->hca_attr.qos.flow_meter_reg_c_ids; 1434 /* 1435 * Meter needs two REG_C's for color match and pre-sfx 1436 * flow match. Here get the REG_C for color match. 1437 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1438 */ 1439 reg_c_mask &= 0xfc; 1440 if (__builtin_popcount(reg_c_mask) < 1) { 1441 priv->mtr_en = 0; 1442 DRV_LOG(WARNING, "No available register for" 1443 " meter."); 1444 } else { 1445 /* 1446 * The meter color register is used by the 1447 * flow-hit feature as well. 1448 * The flow-hit feature must use REG_C_3 1449 * Prefer REG_C_3 if it is available. 1450 */ 1451 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1452 priv->mtr_color_reg = REG_C_3; 1453 else 1454 priv->mtr_color_reg = ffs(reg_c_mask) 1455 - 1 + REG_C_0; 1456 priv->mtr_en = 1; 1457 priv->mtr_reg_share = 1458 config->hca_attr.qos.flow_meter; 1459 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1460 priv->mtr_color_reg); 1461 } 1462 } 1463 if (config->hca_attr.qos.sup && 1464 config->hca_attr.qos.flow_meter_aso_sup) { 1465 uint32_t log_obj_size = 1466 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); 1467 if (log_obj_size >= 1468 config->hca_attr.qos.log_meter_aso_granularity && 1469 log_obj_size <= 1470 config->hca_attr.qos.log_meter_aso_max_alloc) 1471 sh->meter_aso_en = 1; 1472 } 1473 if (priv->mtr_en) { 1474 err = mlx5_aso_flow_mtrs_mng_init(priv->sh); 1475 if (err) { 1476 err = -err; 1477 goto error; 1478 } 1479 } 1480 if (config->hca_attr.flow.tunnel_header_0_1) 1481 sh->tunnel_header_0_1 = 1; 1482 #endif 1483 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1484 if (config->hca_attr.flow_hit_aso && 1485 priv->mtr_color_reg == REG_C_3) { 1486 sh->flow_hit_aso_en = 1; 1487 err = mlx5_flow_aso_age_mng_init(sh); 1488 if (err) { 1489 err = -err; 1490 goto error; 1491 } 1492 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1493 } 1494 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1495 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ 1496 defined(HAVE_MLX5_DR_ACTION_ASO_CT) 1497 if (config->hca_attr.ct_offload && 1498 priv->mtr_color_reg == REG_C_3) { 1499 err = mlx5_flow_aso_ct_mng_init(sh); 1500 if (err) { 1501 err = -err; 1502 goto error; 1503 } 1504 DRV_LOG(DEBUG, "CT ASO is supported."); 1505 sh->ct_aso_en = 1; 1506 } 1507 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ 1508 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1509 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1510 config->dv_flow_en) { 1511 priv->sampler_en = 1; 1512 DRV_LOG(DEBUG, "Sampler enabled!"); 1513 } else { 1514 priv->sampler_en = 0; 1515 if (!config->hca_attr.log_max_ft_sampler_num) 1516 DRV_LOG(WARNING, 1517 "No available register for sampler."); 1518 else 1519 DRV_LOG(DEBUG, "DV flow is not supported!"); 1520 } 1521 #endif 1522 } 1523 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && 1524 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { 1525 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); 1526 config->cqe_comp = 0; 1527 } 1528 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 1529 (!config->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) { 1530 DRV_LOG(WARNING, "Flow Tag CQE compression" 1531 " format isn't supported."); 1532 config->cqe_comp = 0; 1533 } 1534 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 1535 (!config->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) { 1536 DRV_LOG(WARNING, "L3/L4 Header CQE compression" 1537 " format isn't supported."); 1538 config->cqe_comp = 0; 1539 } 1540 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", 1541 config->cqe_comp ? "" : "not "); 1542 if (config->tx_pp) { 1543 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1544 config->hca_attr.dev_freq_khz); 1545 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1546 config->hca_attr.qos.packet_pacing ? "" : "not "); 1547 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1548 config->hca_attr.cross_channel ? "" : "not "); 1549 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1550 config->hca_attr.wqe_index_ignore ? "" : "not "); 1551 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1552 config->hca_attr.non_wire_sq ? "" : "not "); 1553 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1554 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1555 config->hca_attr.log_max_static_sq_wq); 1556 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1557 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1558 if (!config->devx) { 1559 DRV_LOG(ERR, "DevX is required for packet pacing"); 1560 err = ENODEV; 1561 goto error; 1562 } 1563 if (!config->hca_attr.qos.packet_pacing) { 1564 DRV_LOG(ERR, "Packet pacing is not supported"); 1565 err = ENODEV; 1566 goto error; 1567 } 1568 if (!config->hca_attr.cross_channel) { 1569 DRV_LOG(ERR, "Cross channel operations are" 1570 " required for packet pacing"); 1571 err = ENODEV; 1572 goto error; 1573 } 1574 if (!config->hca_attr.wqe_index_ignore) { 1575 DRV_LOG(ERR, "WQE index ignore feature is" 1576 " required for packet pacing"); 1577 err = ENODEV; 1578 goto error; 1579 } 1580 if (!config->hca_attr.non_wire_sq) { 1581 DRV_LOG(ERR, "Non-wire SQ feature is" 1582 " required for packet pacing"); 1583 err = ENODEV; 1584 goto error; 1585 } 1586 if (!config->hca_attr.log_max_static_sq_wq) { 1587 DRV_LOG(ERR, "Static WQE SQ feature is" 1588 " required for packet pacing"); 1589 err = ENODEV; 1590 goto error; 1591 } 1592 if (!config->hca_attr.qos.wqe_rate_pp) { 1593 DRV_LOG(ERR, "WQE rate mode is required" 1594 " for packet pacing"); 1595 err = ENODEV; 1596 goto error; 1597 } 1598 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1599 DRV_LOG(ERR, "DevX does not provide UAR offset," 1600 " can't create queues for packet pacing"); 1601 err = ENODEV; 1602 goto error; 1603 #endif 1604 } 1605 if (config->devx) { 1606 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1607 1608 err = config->hca_attr.access_register_user ? 1609 mlx5_devx_cmd_register_read 1610 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1611 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1612 if (!err) { 1613 uint32_t ts_mode; 1614 1615 /* MTUTC register is read successfully. */ 1616 ts_mode = MLX5_GET(register_mtutc, reg, 1617 time_stamp_mode); 1618 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1619 config->rt_timestamp = 1; 1620 } else { 1621 /* Kernel does not support register reading. */ 1622 if (config->hca_attr.dev_freq_khz == 1623 (NS_PER_S / MS_PER_S)) 1624 config->rt_timestamp = 1; 1625 } 1626 } 1627 /* 1628 * If HW has bug working with tunnel packet decapsulation and 1629 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1630 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1631 */ 1632 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1633 config->hw_fcs_strip = 0; 1634 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1635 (config->hw_fcs_strip ? "" : "not ")); 1636 if (config->mprq.enabled && mprq) { 1637 if (config->mprq.stride_num_n && 1638 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1639 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1640 config->mprq.stride_num_n = 1641 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1642 mprq_min_stride_num_n), 1643 mprq_max_stride_num_n); 1644 DRV_LOG(WARNING, 1645 "the number of strides" 1646 " for Multi-Packet RQ is out of range," 1647 " setting default value (%u)", 1648 1 << config->mprq.stride_num_n); 1649 } 1650 if (config->mprq.stride_size_n && 1651 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1652 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1653 config->mprq.stride_size_n = 1654 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1655 mprq_min_stride_size_n), 1656 mprq_max_stride_size_n); 1657 DRV_LOG(WARNING, 1658 "the size of a stride" 1659 " for Multi-Packet RQ is out of range," 1660 " setting default value (%u)", 1661 1 << config->mprq.stride_size_n); 1662 } 1663 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1664 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1665 } else if (config->mprq.enabled && !mprq) { 1666 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1667 config->mprq.enabled = 0; 1668 } 1669 if (config->max_dump_files_num == 0) 1670 config->max_dump_files_num = 128; 1671 eth_dev = rte_eth_dev_allocate(name); 1672 if (eth_dev == NULL) { 1673 DRV_LOG(ERR, "can not allocate rte ethdev"); 1674 err = ENOMEM; 1675 goto error; 1676 } 1677 if (priv->representor) { 1678 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1679 eth_dev->data->representor_id = priv->representor_id; 1680 } 1681 priv->mp_id.port_id = eth_dev->data->port_id; 1682 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1683 /* 1684 * Store associated network device interface index. This index 1685 * is permanent throughout the lifetime of device. So, we may store 1686 * the ifindex here and use the cached value further. 1687 */ 1688 MLX5_ASSERT(spawn->ifindex); 1689 priv->if_index = spawn->ifindex; 1690 eth_dev->data->dev_private = priv; 1691 priv->dev_data = eth_dev->data; 1692 eth_dev->data->mac_addrs = priv->mac; 1693 eth_dev->device = dpdk_dev; 1694 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1695 /* Configure the first MAC address by default. */ 1696 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1697 DRV_LOG(ERR, 1698 "port %u cannot get MAC address, is mlx5_en" 1699 " loaded? (errno: %s)", 1700 eth_dev->data->port_id, strerror(rte_errno)); 1701 err = ENODEV; 1702 goto error; 1703 } 1704 DRV_LOG(INFO, 1705 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1706 eth_dev->data->port_id, 1707 mac.addr_bytes[0], mac.addr_bytes[1], 1708 mac.addr_bytes[2], mac.addr_bytes[3], 1709 mac.addr_bytes[4], mac.addr_bytes[5]); 1710 #ifdef RTE_LIBRTE_MLX5_DEBUG 1711 { 1712 char ifname[MLX5_NAMESIZE]; 1713 1714 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1715 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1716 eth_dev->data->port_id, ifname); 1717 else 1718 DRV_LOG(DEBUG, "port %u ifname is unknown", 1719 eth_dev->data->port_id); 1720 } 1721 #endif 1722 /* Get actual MTU if possible. */ 1723 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1724 if (err) { 1725 err = rte_errno; 1726 goto error; 1727 } 1728 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1729 priv->mtu); 1730 /* Initialize burst functions to prevent crashes before link-up. */ 1731 eth_dev->rx_pkt_burst = removed_rx_burst; 1732 eth_dev->tx_pkt_burst = removed_tx_burst; 1733 eth_dev->dev_ops = &mlx5_dev_ops; 1734 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1735 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1736 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1737 /* Register MAC address. */ 1738 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1739 if (config->vf && config->vf_nl_en) 1740 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1741 mlx5_ifindex(eth_dev), 1742 eth_dev->data->mac_addrs, 1743 MLX5_MAX_MAC_ADDRESSES); 1744 priv->ctrl_flows = 0; 1745 rte_spinlock_init(&priv->flow_list_lock); 1746 TAILQ_INIT(&priv->flow_meters); 1747 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR); 1748 if (!priv->mtr_profile_tbl) 1749 goto error; 1750 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1751 mlx5_glue->dv_set_context_attr(sh->ctx, 1752 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1753 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1754 .alloc = &mlx5_alloc_verbs_buf, 1755 .free = &mlx5_free_verbs_buf, 1756 .data = sh, 1757 })); 1758 /* Bring Ethernet device up. */ 1759 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1760 eth_dev->data->port_id); 1761 mlx5_set_link_up(eth_dev); 1762 /* 1763 * Even though the interrupt handler is not installed yet, 1764 * interrupts will still trigger on the async_fd from 1765 * Verbs context returned by ibv_open_device(). 1766 */ 1767 mlx5_link_update(eth_dev, 0); 1768 #ifdef HAVE_MLX5DV_DR_ESWITCH 1769 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1770 (switch_info->representor || switch_info->master))) 1771 config->dv_esw_en = 0; 1772 #else 1773 config->dv_esw_en = 0; 1774 #endif 1775 /* Detect minimal data bytes to inline. */ 1776 mlx5_set_min_inline(spawn, config); 1777 /* Store device configuration on private structure. */ 1778 priv->config = *config; 1779 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 1780 icfg[i].release_mem_en = !!config->reclaim_mode; 1781 if (config->reclaim_mode) 1782 icfg[i].per_core_cache = 0; 1783 priv->flows[i] = mlx5_ipool_create(&icfg[i]); 1784 if (!priv->flows[i]) 1785 goto error; 1786 } 1787 /* Create context for virtual machine VLAN workaround. */ 1788 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1789 if (config->dv_flow_en) { 1790 err = mlx5_alloc_shared_dr(priv); 1791 if (err) 1792 goto error; 1793 } 1794 if (config->devx && config->dv_flow_en && config->dest_tir) { 1795 priv->obj_ops = devx_obj_ops; 1796 priv->obj_ops.drop_action_create = 1797 ibv_obj_ops.drop_action_create; 1798 priv->obj_ops.drop_action_destroy = 1799 ibv_obj_ops.drop_action_destroy; 1800 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1801 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1802 #else 1803 if (config->dv_esw_en) 1804 priv->obj_ops.txq_obj_modify = 1805 ibv_obj_ops.txq_obj_modify; 1806 #endif 1807 /* Use specific wrappers for Tx object. */ 1808 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1809 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1810 mlx5_queue_counter_id_prepare(eth_dev); 1811 priv->obj_ops.lb_dummy_queue_create = 1812 mlx5_rxq_ibv_obj_dummy_lb_create; 1813 priv->obj_ops.lb_dummy_queue_release = 1814 mlx5_rxq_ibv_obj_dummy_lb_release; 1815 } else { 1816 priv->obj_ops = ibv_obj_ops; 1817 } 1818 if (config->tx_pp && 1819 (priv->config.dv_esw_en || 1820 priv->obj_ops.txq_obj_new != mlx5_os_txq_obj_new)) { 1821 /* 1822 * HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support 1823 * packet pacing and already checked above. 1824 * Hence, we should only make sure the SQs will be created 1825 * with DevX, not with Verbs. 1826 * Verbs allocates the SQ UAR on its own and it can't be shared 1827 * with Clock Queue UAR as required for Tx scheduling. 1828 */ 1829 DRV_LOG(ERR, "Verbs SQs, UAR can't be shared as required for packet pacing"); 1830 err = ENODEV; 1831 goto error; 1832 } 1833 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1834 if (!priv->drop_queue.hrxq) 1835 goto error; 1836 /* Supported Verbs flow priority number detection. */ 1837 err = mlx5_flow_discover_priorities(eth_dev); 1838 if (err < 0) { 1839 err = -err; 1840 goto error; 1841 } 1842 priv->config.flow_prio = err; 1843 if (!priv->config.dv_esw_en && 1844 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1845 DRV_LOG(WARNING, "metadata mode %u is not supported " 1846 "(no E-Switch)", priv->config.dv_xmeta_en); 1847 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1848 } 1849 mlx5_set_metadata_mask(eth_dev); 1850 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1851 !priv->sh->dv_regc0_mask) { 1852 DRV_LOG(ERR, "metadata mode %u is not supported " 1853 "(no metadata reg_c[0] is available)", 1854 priv->config.dv_xmeta_en); 1855 err = ENOTSUP; 1856 goto error; 1857 } 1858 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true, 1859 mlx5_hrxq_create_cb, 1860 mlx5_hrxq_match_cb, 1861 mlx5_hrxq_remove_cb, 1862 mlx5_hrxq_clone_cb, 1863 mlx5_hrxq_clone_free_cb); 1864 if (!priv->hrxqs) 1865 goto error; 1866 rte_rwlock_init(&priv->ind_tbls_lock); 1867 /* Query availability of metadata reg_c's. */ 1868 err = mlx5_flow_discover_mreg_c(eth_dev); 1869 if (err < 0) { 1870 err = -err; 1871 goto error; 1872 } 1873 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1874 DRV_LOG(DEBUG, 1875 "port %u extensive metadata register is not supported", 1876 eth_dev->data->port_id); 1877 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1878 DRV_LOG(ERR, "metadata mode %u is not supported " 1879 "(no metadata registers available)", 1880 priv->config.dv_xmeta_en); 1881 err = ENOTSUP; 1882 goto error; 1883 } 1884 } 1885 if (priv->config.dv_flow_en && 1886 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1887 mlx5_flow_ext_mreg_supported(eth_dev) && 1888 priv->sh->dv_regc0_mask) { 1889 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1890 MLX5_FLOW_MREG_HTABLE_SZ, 1891 false, true, eth_dev, 1892 flow_dv_mreg_create_cb, 1893 flow_dv_mreg_match_cb, 1894 flow_dv_mreg_remove_cb, 1895 flow_dv_mreg_clone_cb, 1896 flow_dv_mreg_clone_free_cb); 1897 if (!priv->mreg_cp_tbl) { 1898 err = ENOMEM; 1899 goto error; 1900 } 1901 } 1902 rte_spinlock_init(&priv->shared_act_sl); 1903 mlx5_flow_counter_mode_config(eth_dev); 1904 mlx5_flow_drop_action_config(eth_dev); 1905 if (priv->config.dv_flow_en) 1906 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1907 return eth_dev; 1908 error: 1909 if (priv) { 1910 if (priv->mreg_cp_tbl) 1911 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1912 if (priv->sh) 1913 mlx5_os_free_shared_dr(priv); 1914 if (priv->nl_socket_route >= 0) 1915 close(priv->nl_socket_route); 1916 if (priv->nl_socket_rdma >= 0) 1917 close(priv->nl_socket_rdma); 1918 if (priv->vmwa_context) 1919 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1920 if (eth_dev && priv->drop_queue.hrxq) 1921 mlx5_drop_action_destroy(eth_dev); 1922 if (priv->mtr_profile_tbl) 1923 mlx5_l3t_destroy(priv->mtr_profile_tbl); 1924 if (own_domain_id) 1925 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1926 if (priv->hrxqs) 1927 mlx5_list_destroy(priv->hrxqs); 1928 mlx5_free(priv); 1929 if (eth_dev != NULL) 1930 eth_dev->data->dev_private = NULL; 1931 } 1932 if (eth_dev != NULL) { 1933 /* mac_addrs must not be freed alone because part of 1934 * dev_private 1935 **/ 1936 eth_dev->data->mac_addrs = NULL; 1937 rte_eth_dev_release_port(eth_dev); 1938 } 1939 if (sh) 1940 mlx5_free_shared_dev_ctx(sh); 1941 MLX5_ASSERT(err > 0); 1942 rte_errno = err; 1943 return NULL; 1944 } 1945 1946 /** 1947 * Comparison callback to sort device data. 1948 * 1949 * This is meant to be used with qsort(). 1950 * 1951 * @param a[in] 1952 * Pointer to pointer to first data object. 1953 * @param b[in] 1954 * Pointer to pointer to second data object. 1955 * 1956 * @return 1957 * 0 if both objects are equal, less than 0 if the first argument is less 1958 * than the second, greater than 0 otherwise. 1959 */ 1960 static int 1961 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1962 { 1963 const struct mlx5_switch_info *si_a = 1964 &((const struct mlx5_dev_spawn_data *)a)->info; 1965 const struct mlx5_switch_info *si_b = 1966 &((const struct mlx5_dev_spawn_data *)b)->info; 1967 int ret; 1968 1969 /* Master device first. */ 1970 ret = si_b->master - si_a->master; 1971 if (ret) 1972 return ret; 1973 /* Then representor devices. */ 1974 ret = si_b->representor - si_a->representor; 1975 if (ret) 1976 return ret; 1977 /* Unidentified devices come last in no specific order. */ 1978 if (!si_a->representor) 1979 return 0; 1980 /* Order representors by name. */ 1981 return si_a->port_name - si_b->port_name; 1982 } 1983 1984 /** 1985 * Match PCI information for possible slaves of bonding device. 1986 * 1987 * @param[in] ibv_dev 1988 * Pointer to Infiniband device structure. 1989 * @param[in] pci_dev 1990 * Pointer to primary PCI address structure to match. 1991 * @param[in] nl_rdma 1992 * Netlink RDMA group socket handle. 1993 * @param[in] owner 1994 * Rerepsentor owner PF index. 1995 * @param[out] bond_info 1996 * Pointer to bonding information. 1997 * 1998 * @return 1999 * negative value if no bonding device found, otherwise 2000 * positive index of slave PF in bonding. 2001 */ 2002 static int 2003 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 2004 const struct rte_pci_addr *pci_dev, 2005 int nl_rdma, uint16_t owner, 2006 struct mlx5_bond_info *bond_info) 2007 { 2008 char ifname[IF_NAMESIZE + 1]; 2009 unsigned int ifindex; 2010 unsigned int np, i; 2011 FILE *bond_file = NULL, *file; 2012 int pf = -1; 2013 int ret; 2014 2015 /* 2016 * Try to get master device name. If something goes 2017 * wrong suppose the lack of kernel support and no 2018 * bonding devices. 2019 */ 2020 memset(bond_info, 0, sizeof(*bond_info)); 2021 if (nl_rdma < 0) 2022 return -1; 2023 if (!strstr(ibv_dev->name, "bond")) 2024 return -1; 2025 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 2026 if (!np) 2027 return -1; 2028 /* 2029 * The Master device might not be on the predefined 2030 * port (not on port index 1, it is not garanted), 2031 * we have to scan all Infiniband device port and 2032 * find master. 2033 */ 2034 for (i = 1; i <= np; ++i) { 2035 /* Check whether Infiniband port is populated. */ 2036 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 2037 if (!ifindex) 2038 continue; 2039 if (!if_indextoname(ifindex, ifname)) 2040 continue; 2041 /* Try to read bonding slave names from sysfs. */ 2042 MKSTR(slaves, 2043 "/sys/class/net/%s/master/bonding/slaves", ifname); 2044 bond_file = fopen(slaves, "r"); 2045 if (bond_file) 2046 break; 2047 } 2048 if (!bond_file) 2049 return -1; 2050 /* Use safe format to check maximal buffer length. */ 2051 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 2052 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 2053 char tmp_str[IF_NAMESIZE + 32]; 2054 struct rte_pci_addr pci_addr; 2055 struct mlx5_switch_info info; 2056 2057 /* Process slave interface names in the loop. */ 2058 snprintf(tmp_str, sizeof(tmp_str), 2059 "/sys/class/net/%s", ifname); 2060 if (mlx5_get_pci_addr(tmp_str, &pci_addr)) { 2061 DRV_LOG(WARNING, "can not get PCI address" 2062 " for netdev \"%s\"", ifname); 2063 continue; 2064 } 2065 /* Slave interface PCI address match found. */ 2066 snprintf(tmp_str, sizeof(tmp_str), 2067 "/sys/class/net/%s/phys_port_name", ifname); 2068 file = fopen(tmp_str, "rb"); 2069 if (!file) 2070 break; 2071 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 2072 if (fscanf(file, "%32s", tmp_str) == 1) 2073 mlx5_translate_port_name(tmp_str, &info); 2074 fclose(file); 2075 /* Only process PF ports. */ 2076 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 2077 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 2078 continue; 2079 /* Check max bonding member. */ 2080 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 2081 DRV_LOG(WARNING, "bonding index out of range, " 2082 "please increase MLX5_BOND_MAX_PORTS: %s", 2083 tmp_str); 2084 break; 2085 } 2086 /* Match PCI address, allows BDF0+pfx or BDFx+pfx. */ 2087 if (pci_dev->domain == pci_addr.domain && 2088 pci_dev->bus == pci_addr.bus && 2089 pci_dev->devid == pci_addr.devid && 2090 ((pci_dev->function == 0 && 2091 pci_dev->function + owner == pci_addr.function) || 2092 (pci_dev->function == owner && 2093 pci_addr.function == owner))) 2094 pf = info.port_name; 2095 /* Get ifindex. */ 2096 snprintf(tmp_str, sizeof(tmp_str), 2097 "/sys/class/net/%s/ifindex", ifname); 2098 file = fopen(tmp_str, "rb"); 2099 if (!file) 2100 break; 2101 ret = fscanf(file, "%u", &ifindex); 2102 fclose(file); 2103 if (ret != 1) 2104 break; 2105 /* Save bonding info. */ 2106 strncpy(bond_info->ports[info.port_name].ifname, ifname, 2107 sizeof(bond_info->ports[0].ifname)); 2108 bond_info->ports[info.port_name].pci_addr = pci_addr; 2109 bond_info->ports[info.port_name].ifindex = ifindex; 2110 bond_info->n_port++; 2111 } 2112 if (pf >= 0) { 2113 /* Get bond interface info */ 2114 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 2115 bond_info->ifname); 2116 if (ret) 2117 DRV_LOG(ERR, "unable to get bond info: %s", 2118 strerror(rte_errno)); 2119 else 2120 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 2121 ifindex, bond_info->ifindex, bond_info->ifname); 2122 } 2123 return pf; 2124 } 2125 2126 static void 2127 mlx5_os_config_default(struct mlx5_dev_config *config) 2128 { 2129 memset(config, 0, sizeof(*config)); 2130 config->mps = MLX5_ARG_UNSET; 2131 config->dbnc = MLX5_ARG_UNSET; 2132 config->rx_vec_en = 1; 2133 config->txq_inline_max = MLX5_ARG_UNSET; 2134 config->txq_inline_min = MLX5_ARG_UNSET; 2135 config->txq_inline_mpw = MLX5_ARG_UNSET; 2136 config->txqs_inline = MLX5_ARG_UNSET; 2137 config->vf_nl_en = 1; 2138 config->mr_ext_memseg_en = 1; 2139 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2140 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2141 config->dv_esw_en = 1; 2142 config->dv_flow_en = 1; 2143 config->decap_en = 1; 2144 config->log_hp_size = MLX5_ARG_UNSET; 2145 } 2146 2147 /** 2148 * Register a PCI device within bonding. 2149 * 2150 * This function spawns Ethernet devices out of a given PCI device and 2151 * bonding owner PF index. 2152 * 2153 * @param[in] pci_dev 2154 * PCI device information. 2155 * @param[in] req_eth_da 2156 * Requested ethdev device argument. 2157 * @param[in] owner_id 2158 * Requested owner PF port ID within bonding device, default to 0. 2159 * 2160 * @return 2161 * 0 on success, a negative errno value otherwise and rte_errno is set. 2162 */ 2163 static int 2164 mlx5_os_pci_probe_pf(struct rte_pci_device *pci_dev, 2165 struct rte_eth_devargs *req_eth_da, 2166 uint16_t owner_id) 2167 { 2168 struct ibv_device **ibv_list; 2169 /* 2170 * Number of found IB Devices matching with requested PCI BDF. 2171 * nd != 1 means there are multiple IB devices over the same 2172 * PCI device and we have representors and master. 2173 */ 2174 unsigned int nd = 0; 2175 /* 2176 * Number of found IB device Ports. nd = 1 and np = 1..n means 2177 * we have the single multiport IB device, and there may be 2178 * representors attached to some of found ports. 2179 */ 2180 unsigned int np = 0; 2181 /* 2182 * Number of DPDK ethernet devices to Spawn - either over 2183 * multiple IB devices or multiple ports of single IB device. 2184 * Actually this is the number of iterations to spawn. 2185 */ 2186 unsigned int ns = 0; 2187 /* 2188 * Bonding device 2189 * < 0 - no bonding device (single one) 2190 * >= 0 - bonding device (value is slave PF index) 2191 */ 2192 int bd = -1; 2193 struct mlx5_dev_spawn_data *list = NULL; 2194 struct mlx5_dev_config dev_config; 2195 unsigned int dev_config_vf; 2196 struct rte_eth_devargs eth_da = *req_eth_da; 2197 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 2198 struct mlx5_bond_info bond_info; 2199 int ret = -1; 2200 2201 errno = 0; 2202 ibv_list = mlx5_glue->get_device_list(&ret); 2203 if (!ibv_list) { 2204 rte_errno = errno ? errno : ENOSYS; 2205 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 2206 return -rte_errno; 2207 } 2208 /* 2209 * First scan the list of all Infiniband devices to find 2210 * matching ones, gathering into the list. 2211 */ 2212 struct ibv_device *ibv_match[ret + 1]; 2213 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 2214 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 2215 unsigned int i; 2216 2217 while (ret-- > 0) { 2218 struct rte_pci_addr pci_addr; 2219 2220 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 2221 bd = mlx5_device_bond_pci_match 2222 (ibv_list[ret], &owner_pci, nl_rdma, owner_id, 2223 &bond_info); 2224 if (bd >= 0) { 2225 /* 2226 * Bonding device detected. Only one match is allowed, 2227 * the bonding is supported over multi-port IB device, 2228 * there should be no matches on representor PCI 2229 * functions or non VF LAG bonding devices with 2230 * specified address. 2231 */ 2232 if (nd) { 2233 DRV_LOG(ERR, 2234 "multiple PCI match on bonding device" 2235 "\"%s\" found", ibv_list[ret]->name); 2236 rte_errno = ENOENT; 2237 ret = -rte_errno; 2238 goto exit; 2239 } 2240 /* Amend owner pci address if owner PF ID specified. */ 2241 if (eth_da.nb_representor_ports) 2242 owner_pci.function += owner_id; 2243 DRV_LOG(INFO, "PCI information matches for" 2244 " slave %d bonding device \"%s\"", 2245 bd, ibv_list[ret]->name); 2246 ibv_match[nd++] = ibv_list[ret]; 2247 break; 2248 } else { 2249 /* Bonding device not found. */ 2250 if (mlx5_get_pci_addr(ibv_list[ret]->ibdev_path, 2251 &pci_addr)) 2252 continue; 2253 if (owner_pci.domain != pci_addr.domain || 2254 owner_pci.bus != pci_addr.bus || 2255 owner_pci.devid != pci_addr.devid || 2256 owner_pci.function != pci_addr.function) 2257 continue; 2258 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2259 ibv_list[ret]->name); 2260 ibv_match[nd++] = ibv_list[ret]; 2261 } 2262 } 2263 ibv_match[nd] = NULL; 2264 if (!nd) { 2265 /* No device matches, just complain and bail out. */ 2266 DRV_LOG(WARNING, 2267 "no Verbs device matches PCI device " PCI_PRI_FMT "," 2268 " are kernel drivers loaded?", 2269 owner_pci.domain, owner_pci.bus, 2270 owner_pci.devid, owner_pci.function); 2271 rte_errno = ENOENT; 2272 ret = -rte_errno; 2273 goto exit; 2274 } 2275 if (nd == 1) { 2276 /* 2277 * Found single matching device may have multiple ports. 2278 * Each port may be representor, we have to check the port 2279 * number and check the representors existence. 2280 */ 2281 if (nl_rdma >= 0) 2282 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2283 if (!np) 2284 DRV_LOG(WARNING, "can not get IB device \"%s\"" 2285 " ports number", ibv_match[0]->name); 2286 if (bd >= 0 && !np) { 2287 DRV_LOG(ERR, "can not get ports" 2288 " for bonding device"); 2289 rte_errno = ENOENT; 2290 ret = -rte_errno; 2291 goto exit; 2292 } 2293 } 2294 /* 2295 * Now we can determine the maximal 2296 * amount of devices to be spawned. 2297 */ 2298 list = mlx5_malloc(MLX5_MEM_ZERO, 2299 sizeof(struct mlx5_dev_spawn_data) * 2300 (np ? np : nd), 2301 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2302 if (!list) { 2303 DRV_LOG(ERR, "spawn data array allocation failure"); 2304 rte_errno = ENOMEM; 2305 ret = -rte_errno; 2306 goto exit; 2307 } 2308 if (bd >= 0 || np > 1) { 2309 /* 2310 * Single IB device with multiple ports found, 2311 * it may be E-Switch master device and representors. 2312 * We have to perform identification through the ports. 2313 */ 2314 MLX5_ASSERT(nl_rdma >= 0); 2315 MLX5_ASSERT(ns == 0); 2316 MLX5_ASSERT(nd == 1); 2317 MLX5_ASSERT(np); 2318 for (i = 1; i <= np; ++i) { 2319 list[ns].bond_info = &bond_info; 2320 list[ns].max_port = np; 2321 list[ns].phys_port = i; 2322 list[ns].phys_dev = ibv_match[0]; 2323 list[ns].eth_dev = NULL; 2324 list[ns].pci_dev = pci_dev; 2325 list[ns].pf_bond = bd; 2326 list[ns].ifindex = mlx5_nl_ifindex 2327 (nl_rdma, 2328 mlx5_os_get_dev_device_name 2329 (list[ns].phys_dev), i); 2330 if (!list[ns].ifindex) { 2331 /* 2332 * No network interface index found for the 2333 * specified port, it means there is no 2334 * representor on this port. It's OK, 2335 * there can be disabled ports, for example 2336 * if sriov_numvfs < sriov_totalvfs. 2337 */ 2338 continue; 2339 } 2340 ret = -1; 2341 if (nl_route >= 0) 2342 ret = mlx5_nl_switch_info 2343 (nl_route, 2344 list[ns].ifindex, 2345 &list[ns].info); 2346 if (ret || (!list[ns].info.representor && 2347 !list[ns].info.master)) { 2348 /* 2349 * We failed to recognize representors with 2350 * Netlink, let's try to perform the task 2351 * with sysfs. 2352 */ 2353 ret = mlx5_sysfs_switch_info 2354 (list[ns].ifindex, 2355 &list[ns].info); 2356 } 2357 if (!ret && bd >= 0) { 2358 switch (list[ns].info.name_type) { 2359 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2360 if (np == 1) { 2361 /* 2362 * Force standalone bonding 2363 * device for ROCE LAG 2364 * confgiurations. 2365 */ 2366 list[ns].info.master = 0; 2367 list[ns].info.representor = 0; 2368 } 2369 if (list[ns].info.port_name == bd) 2370 ns++; 2371 break; 2372 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2373 /* Fallthrough */ 2374 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2375 /* Fallthrough */ 2376 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2377 if (list[ns].info.pf_num == bd) 2378 ns++; 2379 break; 2380 default: 2381 break; 2382 } 2383 continue; 2384 } 2385 if (!ret && (list[ns].info.representor ^ 2386 list[ns].info.master)) 2387 ns++; 2388 } 2389 if (!ns) { 2390 DRV_LOG(ERR, 2391 "unable to recognize master/representors" 2392 " on the IB device with multiple ports"); 2393 rte_errno = ENOENT; 2394 ret = -rte_errno; 2395 goto exit; 2396 } 2397 } else { 2398 /* 2399 * The existence of several matching entries (nd > 1) means 2400 * port representors have been instantiated. No existing Verbs 2401 * call nor sysfs entries can tell them apart, this can only 2402 * be done through Netlink calls assuming kernel drivers are 2403 * recent enough to support them. 2404 * 2405 * In the event of identification failure through Netlink, 2406 * try again through sysfs, then: 2407 * 2408 * 1. A single IB device matches (nd == 1) with single 2409 * port (np=0/1) and is not a representor, assume 2410 * no switch support. 2411 * 2412 * 2. Otherwise no safe assumptions can be made; 2413 * complain louder and bail out. 2414 */ 2415 for (i = 0; i != nd; ++i) { 2416 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2417 list[ns].bond_info = NULL; 2418 list[ns].max_port = 1; 2419 list[ns].phys_port = 1; 2420 list[ns].phys_dev = ibv_match[i]; 2421 list[ns].eth_dev = NULL; 2422 list[ns].pci_dev = pci_dev; 2423 list[ns].pf_bond = -1; 2424 list[ns].ifindex = 0; 2425 if (nl_rdma >= 0) 2426 list[ns].ifindex = mlx5_nl_ifindex 2427 (nl_rdma, 2428 mlx5_os_get_dev_device_name 2429 (list[ns].phys_dev), 1); 2430 if (!list[ns].ifindex) { 2431 char ifname[IF_NAMESIZE]; 2432 2433 /* 2434 * Netlink failed, it may happen with old 2435 * ib_core kernel driver (before 4.16). 2436 * We can assume there is old driver because 2437 * here we are processing single ports IB 2438 * devices. Let's try sysfs to retrieve 2439 * the ifindex. The method works for 2440 * master device only. 2441 */ 2442 if (nd > 1) { 2443 /* 2444 * Multiple devices found, assume 2445 * representors, can not distinguish 2446 * master/representor and retrieve 2447 * ifindex via sysfs. 2448 */ 2449 continue; 2450 } 2451 ret = mlx5_get_ifname_sysfs 2452 (ibv_match[i]->ibdev_path, ifname); 2453 if (!ret) 2454 list[ns].ifindex = 2455 if_nametoindex(ifname); 2456 if (!list[ns].ifindex) { 2457 /* 2458 * No network interface index found 2459 * for the specified device, it means 2460 * there it is neither representor 2461 * nor master. 2462 */ 2463 continue; 2464 } 2465 } 2466 ret = -1; 2467 if (nl_route >= 0) 2468 ret = mlx5_nl_switch_info 2469 (nl_route, 2470 list[ns].ifindex, 2471 &list[ns].info); 2472 if (ret || (!list[ns].info.representor && 2473 !list[ns].info.master)) { 2474 /* 2475 * We failed to recognize representors with 2476 * Netlink, let's try to perform the task 2477 * with sysfs. 2478 */ 2479 ret = mlx5_sysfs_switch_info 2480 (list[ns].ifindex, 2481 &list[ns].info); 2482 } 2483 if (!ret && (list[ns].info.representor ^ 2484 list[ns].info.master)) { 2485 ns++; 2486 } else if ((nd == 1) && 2487 !list[ns].info.representor && 2488 !list[ns].info.master) { 2489 /* 2490 * Single IB device with 2491 * one physical port and 2492 * attached network device. 2493 * May be SRIOV is not enabled 2494 * or there is no representors. 2495 */ 2496 DRV_LOG(INFO, "no E-Switch support detected"); 2497 ns++; 2498 break; 2499 } 2500 } 2501 if (!ns) { 2502 DRV_LOG(ERR, 2503 "unable to recognize master/representors" 2504 " on the multiple IB devices"); 2505 rte_errno = ENOENT; 2506 ret = -rte_errno; 2507 goto exit; 2508 } 2509 /* 2510 * New kernels may add the switch_id attribute for the case 2511 * there is no E-Switch and we wrongly recognized the 2512 * only device as master. Override this if there is the 2513 * single device with single port and new device name 2514 * format present. 2515 */ 2516 if (nd == 1 && 2517 list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) { 2518 list[0].info.master = 0; 2519 list[0].info.representor = 0; 2520 } 2521 } 2522 MLX5_ASSERT(ns); 2523 /* 2524 * Sort list to probe devices in natural order for users convenience 2525 * (i.e. master first, then representors from lowest to highest ID). 2526 */ 2527 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2528 /* Device specific configuration. */ 2529 switch (pci_dev->id.device_id) { 2530 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2531 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2532 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2533 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2534 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2535 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2536 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 2537 dev_config_vf = 1; 2538 break; 2539 default: 2540 dev_config_vf = 0; 2541 break; 2542 } 2543 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2544 /* Set devargs default values. */ 2545 if (eth_da.nb_mh_controllers == 0) { 2546 eth_da.nb_mh_controllers = 1; 2547 eth_da.mh_controllers[0] = 0; 2548 } 2549 if (eth_da.nb_ports == 0 && ns > 0) { 2550 if (list[0].pf_bond >= 0 && list[0].info.representor) 2551 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2552 pci_dev->device.devargs->args); 2553 eth_da.nb_ports = 1; 2554 eth_da.ports[0] = list[0].info.pf_num; 2555 } 2556 if (eth_da.nb_representor_ports == 0) { 2557 eth_da.nb_representor_ports = 1; 2558 eth_da.representor_ports[0] = 0; 2559 } 2560 } 2561 for (i = 0; i != ns; ++i) { 2562 uint32_t restore; 2563 2564 /* Default configuration. */ 2565 mlx5_os_config_default(&dev_config); 2566 dev_config.vf = dev_config_vf; 2567 dev_config.allow_duplicate_pattern = 1; 2568 list[i].numa_node = pci_dev->device.numa_node; 2569 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2570 &list[i], 2571 &dev_config, 2572 ð_da); 2573 if (!list[i].eth_dev) { 2574 if (rte_errno != EBUSY && rte_errno != EEXIST) 2575 break; 2576 /* Device is disabled or already spawned. Ignore it. */ 2577 continue; 2578 } 2579 restore = list[i].eth_dev->data->dev_flags; 2580 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2581 /** 2582 * Each representor has a dedicated interrupts vector. 2583 * rte_eth_copy_pci_info() assigns PF interrupts handle to 2584 * representor eth_dev object because representor and PF 2585 * share the same PCI address. 2586 * Override representor device with a dedicated 2587 * interrupts handle here. 2588 * Representor interrupts handle is released in mlx5_dev_stop(). 2589 */ 2590 if (list[i].info.representor) { 2591 struct rte_intr_handle *intr_handle; 2592 intr_handle = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, 2593 sizeof(*intr_handle), 0, 2594 SOCKET_ID_ANY); 2595 if (!intr_handle) { 2596 DRV_LOG(ERR, 2597 "port %u failed to allocate memory for interrupt handler " 2598 "Rx interrupts will not be supported", 2599 i); 2600 rte_errno = ENOMEM; 2601 ret = -rte_errno; 2602 goto exit; 2603 } 2604 list[i].eth_dev->intr_handle = intr_handle; 2605 } 2606 /* Restore non-PCI flags cleared by the above call. */ 2607 list[i].eth_dev->data->dev_flags |= restore; 2608 rte_eth_dev_probing_finish(list[i].eth_dev); 2609 } 2610 if (i != ns) { 2611 DRV_LOG(ERR, 2612 "probe of PCI device " PCI_PRI_FMT " aborted after" 2613 " encountering an error: %s", 2614 owner_pci.domain, owner_pci.bus, 2615 owner_pci.devid, owner_pci.function, 2616 strerror(rte_errno)); 2617 ret = -rte_errno; 2618 /* Roll back. */ 2619 while (i--) { 2620 if (!list[i].eth_dev) 2621 continue; 2622 mlx5_dev_close(list[i].eth_dev); 2623 /* mac_addrs must not be freed because in dev_private */ 2624 list[i].eth_dev->data->mac_addrs = NULL; 2625 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2626 } 2627 /* Restore original error. */ 2628 rte_errno = -ret; 2629 } else { 2630 ret = 0; 2631 } 2632 exit: 2633 /* 2634 * Do the routine cleanup: 2635 * - close opened Netlink sockets 2636 * - free allocated spawn data array 2637 * - free the Infiniband device list 2638 */ 2639 if (nl_rdma >= 0) 2640 close(nl_rdma); 2641 if (nl_route >= 0) 2642 close(nl_route); 2643 if (list) 2644 mlx5_free(list); 2645 MLX5_ASSERT(ibv_list); 2646 mlx5_glue->free_device_list(ibv_list); 2647 return ret; 2648 } 2649 2650 static int 2651 mlx5_os_parse_eth_devargs(struct rte_device *dev, 2652 struct rte_eth_devargs *eth_da) 2653 { 2654 int ret = 0; 2655 2656 if (dev->devargs == NULL) 2657 return 0; 2658 memset(eth_da, 0, sizeof(*eth_da)); 2659 /* Parse representor information first from class argument. */ 2660 if (dev->devargs->cls_str) 2661 ret = rte_eth_devargs_parse(dev->devargs->cls_str, eth_da); 2662 if (ret != 0) { 2663 DRV_LOG(ERR, "failed to parse device arguments: %s", 2664 dev->devargs->cls_str); 2665 return -rte_errno; 2666 } 2667 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) { 2668 /* Parse legacy device argument */ 2669 ret = rte_eth_devargs_parse(dev->devargs->args, eth_da); 2670 if (ret) { 2671 DRV_LOG(ERR, "failed to parse device arguments: %s", 2672 dev->devargs->args); 2673 return -rte_errno; 2674 } 2675 } 2676 return 0; 2677 } 2678 2679 /** 2680 * Callback to register a PCI device. 2681 * 2682 * This function spawns Ethernet devices out of a given PCI device. 2683 * 2684 * @param[in] pci_dev 2685 * PCI device information. 2686 * 2687 * @return 2688 * 0 on success, a negative errno value otherwise and rte_errno is set. 2689 */ 2690 static int 2691 mlx5_os_pci_probe(struct rte_pci_device *pci_dev) 2692 { 2693 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2694 int ret = 0; 2695 uint16_t p; 2696 2697 ret = mlx5_os_parse_eth_devargs(&pci_dev->device, ð_da); 2698 if (ret != 0) 2699 return ret; 2700 2701 if (eth_da.nb_ports > 0) { 2702 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2703 for (p = 0; p < eth_da.nb_ports; p++) 2704 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 2705 eth_da.ports[p]); 2706 } else { 2707 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 0); 2708 } 2709 return ret; 2710 } 2711 2712 /* Probe a single SF device on auxiliary bus, no representor support. */ 2713 static int 2714 mlx5_os_auxiliary_probe(struct rte_device *dev) 2715 { 2716 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2717 struct mlx5_dev_config config; 2718 struct mlx5_dev_spawn_data spawn = { .pf_bond = -1 }; 2719 struct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev); 2720 struct rte_eth_dev *eth_dev; 2721 int ret = 0; 2722 2723 /* Parse ethdev devargs. */ 2724 ret = mlx5_os_parse_eth_devargs(dev, ð_da); 2725 if (ret != 0) 2726 return ret; 2727 /* Set default config data. */ 2728 mlx5_os_config_default(&config); 2729 config.sf = 1; 2730 /* Init spawn data. */ 2731 spawn.max_port = 1; 2732 spawn.phys_port = 1; 2733 spawn.phys_dev = mlx5_os_get_ibv_dev(dev); 2734 if (spawn.phys_dev == NULL) 2735 return -rte_errno; 2736 ret = mlx5_auxiliary_get_ifindex(dev->name); 2737 if (ret < 0) { 2738 DRV_LOG(ERR, "failed to get ethdev ifindex: %s", dev->name); 2739 return ret; 2740 } 2741 spawn.ifindex = ret; 2742 spawn.numa_node = dev->numa_node; 2743 /* Spawn device. */ 2744 eth_dev = mlx5_dev_spawn(dev, &spawn, &config, ð_da); 2745 if (eth_dev == NULL) 2746 return -rte_errno; 2747 /* Post create. */ 2748 eth_dev->intr_handle = &adev->intr_handle; 2749 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2750 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2751 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV; 2752 eth_dev->data->numa_node = dev->numa_node; 2753 } 2754 rte_eth_dev_probing_finish(eth_dev); 2755 return 0; 2756 } 2757 2758 /** 2759 * Net class driver callback to probe a device. 2760 * 2761 * This function probe PCI bus device(s) or a single SF on auxiliary bus. 2762 * 2763 * @param[in] dev 2764 * Pointer to the generic device. 2765 * 2766 * @return 2767 * 0 on success, the function cannot fail. 2768 */ 2769 int 2770 mlx5_os_net_probe(struct rte_device *dev) 2771 { 2772 int ret; 2773 2774 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2775 mlx5_pmd_socket_init(); 2776 ret = mlx5_init_once(); 2777 if (ret) { 2778 DRV_LOG(ERR, "unable to init PMD global data: %s", 2779 strerror(rte_errno)); 2780 return -rte_errno; 2781 } 2782 if (mlx5_dev_is_pci(dev)) 2783 return mlx5_os_pci_probe(RTE_DEV_TO_PCI(dev)); 2784 else 2785 return mlx5_os_auxiliary_probe(dev); 2786 } 2787 2788 static int 2789 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2790 { 2791 char *env; 2792 int value; 2793 2794 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2795 /* Get environment variable to store. */ 2796 env = getenv(MLX5_SHUT_UP_BF); 2797 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2798 if (config->dbnc == MLX5_ARG_UNSET) 2799 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2800 else 2801 setenv(MLX5_SHUT_UP_BF, 2802 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2803 return value; 2804 } 2805 2806 static void 2807 mlx5_restore_doorbell_mapping_env(int value) 2808 { 2809 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2810 /* Restore the original environment variable state. */ 2811 if (value == MLX5_ARG_UNSET) 2812 unsetenv(MLX5_SHUT_UP_BF); 2813 else 2814 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2815 } 2816 2817 /** 2818 * Extract pdn of PD object using DV API. 2819 * 2820 * @param[in] pd 2821 * Pointer to the verbs PD object. 2822 * @param[out] pdn 2823 * Pointer to the PD object number variable. 2824 * 2825 * @return 2826 * 0 on success, error value otherwise. 2827 */ 2828 int 2829 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2830 { 2831 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2832 struct mlx5dv_obj obj; 2833 struct mlx5dv_pd pd_info; 2834 int ret = 0; 2835 2836 obj.pd.in = pd; 2837 obj.pd.out = &pd_info; 2838 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2839 if (ret) { 2840 DRV_LOG(DEBUG, "Fail to get PD object info"); 2841 return ret; 2842 } 2843 *pdn = pd_info.pdn; 2844 return 0; 2845 #else 2846 (void)pd; 2847 (void)pdn; 2848 return -ENOTSUP; 2849 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2850 } 2851 2852 /** 2853 * Function API to open IB device. 2854 * 2855 * This function calls the Linux glue APIs to open a device. 2856 * 2857 * @param[in] spawn 2858 * Pointer to the IB device attributes (name, port, etc). 2859 * @param[out] config 2860 * Pointer to device configuration structure. 2861 * @param[out] sh 2862 * Pointer to shared context structure. 2863 * 2864 * @return 2865 * 0 on success, a positive error value otherwise. 2866 */ 2867 int 2868 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2869 const struct mlx5_dev_config *config, 2870 struct mlx5_dev_ctx_shared *sh) 2871 { 2872 int dbmap_env; 2873 int err = 0; 2874 2875 pthread_mutex_init(&sh->txpp.mutex, NULL); 2876 /* 2877 * Configure environment variable "MLX5_BF_SHUT_UP" 2878 * before the device creation. The rdma_core library 2879 * checks the variable at device creation and 2880 * stores the result internally. 2881 */ 2882 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2883 /* Try to open IB device with DV first, then usual Verbs. */ 2884 errno = 0; 2885 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2886 if (sh->ctx) { 2887 sh->devx = 1; 2888 DRV_LOG(DEBUG, "DevX is supported"); 2889 /* The device is created, no need for environment. */ 2890 mlx5_restore_doorbell_mapping_env(dbmap_env); 2891 } else { 2892 /* The environment variable is still configured. */ 2893 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2894 err = errno ? errno : ENODEV; 2895 /* 2896 * The environment variable is not needed anymore, 2897 * all device creation attempts are completed. 2898 */ 2899 mlx5_restore_doorbell_mapping_env(dbmap_env); 2900 if (!sh->ctx) 2901 return err; 2902 DRV_LOG(DEBUG, "DevX is NOT supported"); 2903 err = 0; 2904 } 2905 if (!err && sh->ctx) { 2906 /* Hint libmlx5 to use PMD allocator for data plane resources */ 2907 mlx5_glue->dv_set_context_attr(sh->ctx, 2908 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 2909 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 2910 .alloc = &mlx5_alloc_verbs_buf, 2911 .free = &mlx5_free_verbs_buf, 2912 .data = sh, 2913 })); 2914 } 2915 return err; 2916 } 2917 2918 /** 2919 * Install shared asynchronous device events handler. 2920 * This function is implemented to support event sharing 2921 * between multiple ports of single IB device. 2922 * 2923 * @param sh 2924 * Pointer to mlx5_dev_ctx_shared object. 2925 */ 2926 void 2927 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2928 { 2929 int ret; 2930 int flags; 2931 2932 sh->intr_handle.fd = -1; 2933 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2934 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2935 F_SETFL, flags | O_NONBLOCK); 2936 if (ret) { 2937 DRV_LOG(INFO, "failed to change file descriptor async event" 2938 " queue"); 2939 } else { 2940 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2941 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2942 if (rte_intr_callback_register(&sh->intr_handle, 2943 mlx5_dev_interrupt_handler, sh)) { 2944 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2945 sh->intr_handle.fd = -1; 2946 } 2947 } 2948 if (sh->devx) { 2949 #ifdef HAVE_IBV_DEVX_ASYNC 2950 sh->intr_handle_devx.fd = -1; 2951 sh->devx_comp = 2952 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2953 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2954 if (!devx_comp) { 2955 DRV_LOG(INFO, "failed to allocate devx_comp."); 2956 return; 2957 } 2958 flags = fcntl(devx_comp->fd, F_GETFL); 2959 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2960 if (ret) { 2961 DRV_LOG(INFO, "failed to change file descriptor" 2962 " devx comp"); 2963 return; 2964 } 2965 sh->intr_handle_devx.fd = devx_comp->fd; 2966 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2967 if (rte_intr_callback_register(&sh->intr_handle_devx, 2968 mlx5_dev_interrupt_handler_devx, sh)) { 2969 DRV_LOG(INFO, "Fail to install the devx shared" 2970 " interrupt."); 2971 sh->intr_handle_devx.fd = -1; 2972 } 2973 #endif /* HAVE_IBV_DEVX_ASYNC */ 2974 } 2975 } 2976 2977 /** 2978 * Uninstall shared asynchronous device events handler. 2979 * This function is implemented to support event sharing 2980 * between multiple ports of single IB device. 2981 * 2982 * @param dev 2983 * Pointer to mlx5_dev_ctx_shared object. 2984 */ 2985 void 2986 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2987 { 2988 if (sh->intr_handle.fd >= 0) 2989 mlx5_intr_callback_unregister(&sh->intr_handle, 2990 mlx5_dev_interrupt_handler, sh); 2991 #ifdef HAVE_IBV_DEVX_ASYNC 2992 if (sh->intr_handle_devx.fd >= 0) 2993 rte_intr_callback_unregister(&sh->intr_handle_devx, 2994 mlx5_dev_interrupt_handler_devx, sh); 2995 if (sh->devx_comp) 2996 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2997 #endif 2998 } 2999 3000 /** 3001 * Read statistics by a named counter. 3002 * 3003 * @param[in] priv 3004 * Pointer to the private device data structure. 3005 * @param[in] ctr_name 3006 * Pointer to the name of the statistic counter to read 3007 * @param[out] stat 3008 * Pointer to read statistic value. 3009 * @return 3010 * 0 on success and stat is valud, 1 if failed to read the value 3011 * rte_errno is set. 3012 * 3013 */ 3014 int 3015 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 3016 uint64_t *stat) 3017 { 3018 int fd; 3019 3020 if (priv->sh) { 3021 if (priv->q_counters != NULL && 3022 strcmp(ctr_name, "out_of_buffer") == 0) 3023 return mlx5_devx_cmd_queue_counter_query 3024 (priv->q_counters, 0, (uint32_t *)stat); 3025 MKSTR(path, "%s/ports/%d/hw_counters/%s", 3026 priv->sh->ibdev_path, 3027 priv->dev_port, 3028 ctr_name); 3029 fd = open(path, O_RDONLY); 3030 /* 3031 * in switchdev the file location is not per port 3032 * but rather in <ibdev_path>/hw_counters/<file_name>. 3033 */ 3034 if (fd == -1) { 3035 MKSTR(path1, "%s/hw_counters/%s", 3036 priv->sh->ibdev_path, 3037 ctr_name); 3038 fd = open(path1, O_RDONLY); 3039 } 3040 if (fd != -1) { 3041 char buf[21] = {'\0'}; 3042 ssize_t n = read(fd, buf, sizeof(buf)); 3043 3044 close(fd); 3045 if (n != -1) { 3046 *stat = strtoull(buf, NULL, 10); 3047 return 0; 3048 } 3049 } 3050 } 3051 *stat = 0; 3052 return 1; 3053 } 3054 3055 /** 3056 * Set the reg_mr and dereg_mr call backs 3057 * 3058 * @param reg_mr_cb[out] 3059 * Pointer to reg_mr func 3060 * @param dereg_mr_cb[out] 3061 * Pointer to dereg_mr func 3062 * 3063 */ 3064 void 3065 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 3066 mlx5_dereg_mr_t *dereg_mr_cb) 3067 { 3068 *reg_mr_cb = mlx5_mr_verbs_ops.reg_mr; 3069 *dereg_mr_cb = mlx5_mr_verbs_ops.dereg_mr; 3070 } 3071 3072 /** 3073 * Remove a MAC address from device 3074 * 3075 * @param dev 3076 * Pointer to Ethernet device structure. 3077 * @param index 3078 * MAC address index. 3079 */ 3080 void 3081 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 3082 { 3083 struct mlx5_priv *priv = dev->data->dev_private; 3084 const int vf = priv->config.vf; 3085 3086 if (vf) 3087 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 3088 mlx5_ifindex(dev), priv->mac_own, 3089 &dev->data->mac_addrs[index], index); 3090 } 3091 3092 /** 3093 * Adds a MAC address to the device 3094 * 3095 * @param dev 3096 * Pointer to Ethernet device structure. 3097 * @param mac_addr 3098 * MAC address to register. 3099 * @param index 3100 * MAC address index. 3101 * 3102 * @return 3103 * 0 on success, a negative errno value otherwise 3104 */ 3105 int 3106 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 3107 uint32_t index) 3108 { 3109 struct mlx5_priv *priv = dev->data->dev_private; 3110 const int vf = priv->config.vf; 3111 int ret = 0; 3112 3113 if (vf) 3114 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 3115 mlx5_ifindex(dev), priv->mac_own, 3116 mac, index); 3117 return ret; 3118 } 3119 3120 /** 3121 * Modify a VF MAC address 3122 * 3123 * @param priv 3124 * Pointer to device private data. 3125 * @param mac_addr 3126 * MAC address to modify into. 3127 * @param iface_idx 3128 * Net device interface index 3129 * @param vf_index 3130 * VF index 3131 * 3132 * @return 3133 * 0 on success, a negative errno value otherwise 3134 */ 3135 int 3136 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 3137 unsigned int iface_idx, 3138 struct rte_ether_addr *mac_addr, 3139 int vf_index) 3140 { 3141 return mlx5_nl_vf_mac_addr_modify 3142 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 3143 } 3144 3145 /** 3146 * Set device promiscuous mode 3147 * 3148 * @param dev 3149 * Pointer to Ethernet device structure. 3150 * @param enable 3151 * 0 - promiscuous is disabled, otherwise - enabled 3152 * 3153 * @return 3154 * 0 on success, a negative error value otherwise 3155 */ 3156 int 3157 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 3158 { 3159 struct mlx5_priv *priv = dev->data->dev_private; 3160 3161 return mlx5_nl_promisc(priv->nl_socket_route, 3162 mlx5_ifindex(dev), !!enable); 3163 } 3164 3165 /** 3166 * Set device promiscuous mode 3167 * 3168 * @param dev 3169 * Pointer to Ethernet device structure. 3170 * @param enable 3171 * 0 - all multicase is disabled, otherwise - enabled 3172 * 3173 * @return 3174 * 0 on success, a negative error value otherwise 3175 */ 3176 int 3177 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 3178 { 3179 struct mlx5_priv *priv = dev->data->dev_private; 3180 3181 return mlx5_nl_allmulti(priv->nl_socket_route, 3182 mlx5_ifindex(dev), !!enable); 3183 } 3184 3185 /** 3186 * Flush device MAC addresses 3187 * 3188 * @param dev 3189 * Pointer to Ethernet device structure. 3190 * 3191 */ 3192 void 3193 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 3194 { 3195 struct mlx5_priv *priv = dev->data->dev_private; 3196 3197 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 3198 dev->data->mac_addrs, 3199 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 3200 } 3201