net/mlx5: fix memory leak in metering

Avoid allocating memory for meter profile table when meter is not
enabled. This memory was not being freed in the close process when
meter was disabled, potenti

net/mlx5: fix memory leak in metering

Avoid allocating memory for meter profile table when meter is not
enabled. This memory was not being freed in the close process when
meter was disabled, potentially causing a leak.

Fixes: a295c69a8b24 ("net/mlx5: optimize meter profile lookup")
Cc: stable@dpdk.org

Signed-off-by: Shun Hao <shunh@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>

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net/mlx5: support configuration without host PF

Add support for a new BlueField firmware configuration option
NUM_OF_PF=0 that disables the PF on the x86 host side. This results
in no HPF represento

net/mlx5: support configuration without host PF

Add support for a new BlueField firmware configuration option
NUM_OF_PF=0 that disables the PF on the x86 host side. This results
in no HPF representor on the ARM side, with only the bonding device
(PF0) as the RDMA port.

Allow probing a PF device even if it has no associated switch ports,
to handle cases where PF1 may not exist in this configuration. This
enables proper device probing with representor devargs like
pf[0-1]vf[...] on systems using the NUM_OF_PF=0 option.

Signed-off-by: Xueming Li <xuemingl@nvidia.com>
Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

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net/mlx5: share init of control flow rules

Control flow rules lists and control flow rule lock
can be reused between all flow engines, but their initialization
was done in flow_hw_configure() implem

net/mlx5: share init of control flow rules

Control flow rules lists and control flow rule lock
can be reused between all flow engines, but their initialization
was done in flow_hw_configure() implementation.
This patch moves it to mlx5_dev_spawn(),
which is called for Verbs, DV and HWS flow engines.

Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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net/mlx5: add metadata split for compatibility

The method will not create any new flow rule implicitly during split
stage, but only generate needed items, actions and attributes based
on the detecti

net/mlx5: add metadata split for compatibility

The method will not create any new flow rule implicitly during split
stage, but only generate needed items, actions and attributes based
on the detection.

All the rules will still be created in the flow_hw_list_create().

In the meanwhile, once the mark action is specified in the FDB rule,
a new rule in the NIC Rx will be created to:
1. match the mark value on REG_C_x in FDB and set it into Rx
flow tag field.
2. copy the metadata in REG_C_x' into the REG_B.

If there is no mark, the default rule with only copying metadata
will be hit if there is Queue or RSS action in the NIC Rx rule.

Regarding the NIC Tx, only the metadata is relevant and it will be
copied in NIC Tx from REG_A into some REG_C_x. The current HWS
implementation already has already supported in the default copy
rule or the default SQ miss rule in the NIC Tx root table.

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

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net/mlx5: fix uplink port probing in bonding mode

In the HW-LAG bonding mode, the representor port can be from both
slave PFs. When probing a representor (REP), the UPLINK (proxy) port
always needs

net/mlx5: fix uplink port probing in bonding mode

In the HW-LAG bonding mode, the representor port can be from both
slave PFs. When probing a representor (REP), the UPLINK (proxy) port
always needs to be probed firstly before any REP port.

In the current implementation, when probing a device with the
following format:

-a 0000:XX:00.0,dv_flow_en=N,representor=pf1vfy

Since the REP belongs to the 2nd PF in the bonding, the UPLINK would
not be added into the probing ports list.

1. In dv_flow_en=1 mode, the REP itself can be probed. But it didn't
obey the rules and the behaviors were inconsistent.
a. When probing the REP from 1st PFs, the UPLINK was also probed.
b. When detaching the UPLINK, all REPs were detached.
2. In dv_flow_en=2 mode, since some resources can only be allocated /
created on the proxy port, the probing would get a failure.

By removing the unneeded check of the bonding PF device index, the
UPLINK will always try to be probed with any format.

Fixes: 2e569a370395 ("net/mlx5: add VF LAG mode bonding device recognition")
Cc: stable@dpdk.org

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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net/mlx5: add hairpin out-of-buffer per-port counter

Currently mlx5 PMD exposes rx_out_of_buffer counter that tracks
packets dropped when Rx queue was full.

To provide more granular statistics, thi

net/mlx5: add hairpin out-of-buffer per-port counter

Currently mlx5 PMD exposes rx_out_of_buffer counter that tracks
packets dropped when Rx queue was full.

To provide more granular statistics, this patch splits the
`rx_out_of_buffer` counter into two separate counters:
1. hairpin_out_of_buffer - This counter specifically tracks packets dropped
by the device's hairpin Rx queues.
2. rx_out_of_buffer - This counter tracks packets dropped by the device's
Rx queues, excluding the hairpin Rx queues.

Two hardware counter objects will be created per device,
and all the Rx queues will be assigned to these counters during the
configuration phase.

The `hairpin_out_of_buffer` counter will be created only if there is
at least one hairpin Rx queue present on the device.

Signed-off-by: Shani Peretz <shperetz@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

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net/mlx5: fix start without duplicate flow patterns

When devargs "allow_duplicate_pattern=0" is specified, PMD won't
allow duplicated flows to be inserted and return EEXIST as rte_errno.

The queue/

net/mlx5: fix start without duplicate flow patterns

When devargs "allow_duplicate_pattern=0" is specified, PMD won't
allow duplicated flows to be inserted and return EEXIST as rte_errno.

The queue/RSS split table is shared globally by all representors and
PMD didn't prepend port information into it, so all the following ports
tries to insert the same flows and cause PMD insertion failure.

Using the hash list to manage it can solve the issue.

Fixes: ddb68e47331e ("net/mlx5: add extended metadata mode for HWS")
Cc: stable@dpdk.org

Signed-off-by: Rongwei Liu <rongweil@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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net/mlx5: introduce HWS for non-template flow API

Implement the frame and needed building
blocks for non template to hws API's.

Added validate, list_create and list_destroy to mlx5_flow_hw_drv_ops.

net/mlx5: introduce HWS for non-template flow API

Implement the frame and needed building
blocks for non template to hws API's.

Added validate, list_create and list_destroy to mlx5_flow_hw_drv_ops.
Rename old list_create/list_destroy functions to legacy_*
and added a call from verbs/dv ops to the legacy functions.

Updated rte_flow_hw as needed.
Added rte_flow_nt2hws structure for non-template rule data.

Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

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net/mlx5: support flow match with E-Switch manager

Currently, in switch mode, mlx5 PMD only supports match with
dedicated vport. There is a use case which user may want to
offload the rules only to

net/mlx5: support flow match with E-Switch manager

Currently, in switch mode, mlx5 PMD only supports match with
dedicated vport. There is a use case which user may want to
offload the rules only to match with all the packet sent by
application not from vport.

Since the port_id info of packet sent by application is
E-Switch manager, and kernel driver has exposed the E-Switch
manager register value, this commit adds the support of
register matching for E-Switch manager.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

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net/mlx5: support flow match with external Tx queue

For using external created Tx queues in RTE_FLOW_ITEM_TX_QUEUE,
this commit provides the map and unmap functions to convert the
external created S

net/mlx5: support flow match with external Tx queue

For using external created Tx queues in RTE_FLOW_ITEM_TX_QUEUE,
this commit provides the map and unmap functions to convert the
external created SQ's devx ID to DPDK flow item Tx queue ID.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

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net/mlx5: rename external queue

Due to external Tx queue will be supported, in order to reuse
the external queue struct, rename the current external Rx
queue to external queue.

Signed-off-by: Suanm

net/mlx5: rename external queue

Due to external Tx queue will be supported, in order to reuse
the external queue struct, rename the current external Rx
queue to external queue.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

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net/mlx5: fix IPv6 traffic class support

ipv6_tc_fallback will be checked in calling
mlx5_flow_discover_ipv6_tc_support. It should be set "supported" before
checking so that the workaround to use ol

net/mlx5: fix IPv6 traffic class support

ipv6_tc_fallback will be checked in calling
mlx5_flow_discover_ipv6_tc_support. It should be set "supported" before
checking so that the workaround to use old value would not be used. The
corrected result could be gotten only in this case.

Fixes: edc80bbfcf54 ("net/mlx5: store IPv6 TC detection result per physical device")
Cc: stable@dpdk.org

Signed-off-by: Gavin Li <gavinl@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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net/mlx5: store IPv6 TC detection result per physical device

Previously, discovering of IPv6 traffic class would happen on each device
not sharing context with others. However, It's not necessary to

net/mlx5: store IPv6 TC detection result per physical device

Previously, discovering of IPv6 traffic class would happen on each device
not sharing context with others. However, It's not necessary to repeat it
on devices of the same physical device. A flow will be created and
destroyed in the detection, which may trigger cache allocation and take
more memory in scale cases.

To solve the problem, store the discovering of IPv6 traffic class result
in physical device, and do it only once per physical device.

Fixes: d1c84dc015d6 ("net/mlx5: discover IPv6 traffic class support")

Signed-off-by: Gavin Li <gavinl@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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net/mlx5: fix stats query crash in secondary process

The "outer_of_buffer" counter is owned by the primary process devx
object and it is pointer by pointer in mlx5_priv structure. Actually,
there ar

net/mlx5: fix stats query crash in secondary process

The "outer_of_buffer" counter is owned by the primary process devx
object and it is pointer by pointer in mlx5_priv structure. Actually,
there are 4 levels' pointers in this piece of code.

The secondary process can't access this part directly since it belongs
to another process's heap.

Return ENOTSUP as a workaround.

Fixes: 750e48c7d8c3 ("common/mlx5: add DevX commands for queue counters")
Cc: stable@dpdk.org

Signed-off-by: Rongwei Liu <rongweil@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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net/mlx5: update IPv6 traffic class modification

New PRM defined new field OUT_IPV6_TRAFFIC_CLASS for IPv6 which will be
used by both IPv6 ECN and DSCP. A new cap bit
modify_out_ipv6_traffic_class i

net/mlx5: update IPv6 traffic class modification

New PRM defined new field OUT_IPV6_TRAFFIC_CLASS for IPv6 which will be
used by both IPv6 ECN and DSCP. A new cap bit
modify_out_ipv6_traffic_class is added. It can be used to check if the
new field is supported by FW.

However, IPv6 ECN and DSCP starts from different offset in the same byte.
Update SWS and HWS to used the new field and introduce extra offset for
IPv6 DSCP data and mask to solve the issue.

Signed-off-by: Gavin Li <gavinl@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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net/mlx5: discover IPv6 traffic class support

Previously, IPv6 traffic class used the same ids of IPv4 DSCP and ECN by
rdma core and firmware. New FW support new IPv6 traffic class id which is
recom

net/mlx5: discover IPv6 traffic class support

Previously, IPv6 traffic class used the same ids of IPv4 DSCP and ECN by
rdma core and firmware. New FW support new IPv6 traffic class id which is
recommended to be used though the old way is still working.

FW exposed a new cap bit to indicate the supporting of the new id while
RDMA core does not have such mechanism.

To fix the backward compatibility issue of combination of RDMA core and FW
of different versions, a new function and a new flag were introduced to
check if the new IPv6 traffic class id is supported by RDMA core.

Signed-off-by: Gavin Li <gavinl@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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ethdev: parse multiple representor devargs

Adding support for parsing multiple representor devargs strings
passed to a PCI BDF. There may be scenario where port representors
for various PFs or VFs u

ethdev: parse multiple representor devargs

Adding support for parsing multiple representor devargs strings
passed to a PCI BDF. There may be scenario where port representors
for various PFs or VFs under PFs are required and all these are
representor ports shall be backed by single pci device. In such
case port representors can be created using devargs string:
<PCI BDF>,representor=[pf[0-1],pf2vf[1,2-3],[4-5]]

Adding new eth devargs parsing test cases which can demonstrate
valid and invalid usage of devargs patterns.

Signed-off-by: Harman Kalra <hkalra@marvell.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@amd.com>

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net/mlx5: fix LACP redirection in Rx domain

When the "lacp_by_user" is not set from the application in bond
mode, the LACP traffic should be handled by the kernel driver by
default.

This commit add

net/mlx5: fix LACP redirection in Rx domain

When the "lacp_by_user" is not set from the application in bond
mode, the LACP traffic should be handled by the kernel driver by
default.

This commit adds the missing support in the template API when
"dv_flow_en=2". The behavior will be the same as that in the DV
mode with "dv_flow_en=1". The LACP packets will be redirected to the
kernel when starting the steering in the NIC Rx domain.

With this commit, the DEFAULT_MISS action usage is refactored a bit.
In the HWS, one unique action can be created with supported bits set
in the "flag" per port. The *ROOT_FDB and *HWS_FDB flag bits will
only be set when the port is in switchdev mode and working as the
E-Switch manager proxy port. The SF/VF and all other representors
won't have the FDB flag bits when creating the DEFAULT_MISS action.

Fixes: 9fa7c1cddb85 ("net/mlx5: create control flow rules with HWS")
Cc: stable@dpdk.org

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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net/mlx5: sort uplink ports first

This patch changes the behavior of the comparator used to
sort mlx5_dev_spawn_data structures, to put them in a more
user friendly order

Before this patch, ports w

net/mlx5: sort uplink ports first

This patch changes the behavior of the comparator used to
sort mlx5_dev_spawn_data structures, to put them in a more
user friendly order

Before this patch, ports were sorted assuming there is
only a single master port. It resulted in an order where
master port first comes second, then representors in ascending
order of IDs.

This approach however is not desirable with devices configured
for Multiport E-Switch, since uplink ports which do not correspond
to the owning PCI device are representors as well and they will be
mixed with VF/SF representors.

To change that, this patch amends the comparator to force uplink ports
to be first. If there are many uplink ports, the master port will
come first and the rest will be sorted by port index.

Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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net/mlx5: probe multi-port E-Switch device

This patch adds support for probing ports of a Multiport
E-Switch device to mlx5 PMD.

Multiport E-Switch is a configuration of NVIDIA ConnectX/BlueField H

net/mlx5: probe multi-port E-Switch device

This patch adds support for probing ports of a Multiport
E-Switch device to mlx5 PMD.

Multiport E-Switch is a configuration of NVIDIA ConnectX/BlueField HCAs
where all connected entities (i.e. physical ports, VFs and SFs)
share the same switch domain.
In this mode, applications are allowed to create transfer flow rules
which explicitly match on the physical port on which traffic
arrives and/or on VFs and SFs, regardless of the root PF.
On top of that, forwarding to any of these entities is allowed.
Notably, applications are allowed to explicitly forward traffic
to any of the physical ports of the HCA.

This patch implements the following procedure for probing ports
of the device configured as Multiport E-Switch:

1. EAL calls mlx5 PMD to probe certain PCI device (with address BDF).
2. mlx5 PMD iterates over all existing IB devices:
2.1. Check if IB device has a PCI address which matches BDF.
2.2. Check if IB device is configured as Multiport E-Switch device,
using devlink interface.
2.3. Iterate over all IB ports of this device to find a netdev with
matching PCI address.
If any is found, IB device is chosen to instantiate DPDK ports
from it.
3. Iterate over all IB ports of the selected IB device,
to choose which ports to instantiate:
3.1. Choose IB ports which match the selected representor ports
(selected through representor devarg).
Instantiate DPDK ports based on those.
3.2. If IB port represented an uplink port and this port corresponds
to the probed PCI device, instantiated DPDK port is selected
as a switch master port.

Bulk of this work was done in mlx5_os_pci_probe_pf().

To properly enable support for Multiport E-Switch, this patch also
changes the following:

- Probing of representors of type RTE_ETH_REPRESENTOR_PF is allowed,
but if and only if Multiport E-Switch is enabled.
- Uplink ports have a representor type NONE and have
representor ID equal to UINT16_MAX.
rte_eth_dev_representor_info struct returned for uplink ports
have their index stored in `pf` field.
- flow_hw_set_port_info() used by HWS steering layer sets `is_wire`
field to true if a port is an uplink port,
if Multiport E-Switch is enabled.
- Changing MAC address of a port marked as representor is done directly
through its corresponding netdev if it is a Multiport E-Switch uplink.

Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

show more ...

net/mlx5: check multi-port E-Switch state

This patch implements checking if Multiport E-Switch is enabled
on a given PCI device. mlx5_is_mpesw_enabled() implements this
functionality and it will be

net/mlx5: check multi-port E-Switch state

This patch implements checking if Multiport E-Switch is enabled
on a given PCI device. mlx5_is_mpesw_enabled() implements this
functionality and it will be used in a follow up commit.

mlx5_is_mpesw_enabled() first checks if E-Switch state can be probed
using Devlink device parameter. If it cannot be checked or
there was an error, then sysfs interface will be probed.
If that fails, mlx5_is_mpesw_enabled() assumes that Multiport E-Switch
is disabled and returns an error.

Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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net/mlx5: add sysfs check for multi-port E-Switch

This patch implements checking if Multiport E-Switch is enabled
on a given PCI device, using sysfs Linux kernel interface.
This facility will be use

net/mlx5: add sysfs check for multi-port E-Switch

This patch implements checking if Multiport E-Switch is enabled
on a given PCI device, using sysfs Linux kernel interface.
This facility will be used in follow up commits,
which add support for such configuration to mlx5 PMD.

MLNX_OFED mlx5_core kernel module versions which support
Multiport E-Switch do not expose this configuration through Devlink,
but through sysfs interface.
If such a version is used, then Multiport E-Switch can be enabled
(or its state can be probed) through a sysfs file under path:

# <ifname> should be substituted with Linux interface name.
/sys/class/net/<ifname>/compat/devlink/lag_port_select_mode

Writing "multiport_esw" to this file enables Multiport E-Switch.
If "multiport_esw" is read from this file, then
Multiport E-Switch is enabled.

If this file does not exist or writing "multiport_esw" to this file,
raises an error, then Multiport E-Switch is not supported.

Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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net/mlx5: fix flow thread safety flag for HWS

When mlx5 port was configured with HW Steering flow engine
(devarg dv_flow_en set to 2), PMD did not set
RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE in device flag

net/mlx5: fix flow thread safety flag for HWS

When mlx5 port was configured with HW Steering flow engine
(devarg dv_flow_en set to 2), PMD did not set
RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE in device flags.
This caused certain flow API calls, such as rte_flow_query(),
to obtain a port-wide lock, which is not needed.

This patch adds missing code for setting this flag.

Fixes: d84c3cf7662c ("net/mlx5: introduce hardware steering enable routine")
Cc: stable@dpdk.org

Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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net/mlx5: initialize HWS flow registers in shared context

Move HWS flow tags registers initialization to shared dev context.

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Ori Kam <

net/mlx5: initialize HWS flow registers in shared context

Move HWS flow tags registers initialization to shared dev context.

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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net/mlx5: merge C registers aliases

Merge `mtr_color_reg` and `mlx5_flow_hw_aso_tag`
into `aso_reg`

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
Acked-b

net/mlx5: merge C registers aliases

Merge `mtr_color_reg` and `mlx5_flow_hw_aso_tag`
into `aso_reg`

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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