1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <bus_driver.h> 23 #include <bus_pci_driver.h> 24 #include <bus_auxiliary_driver.h> 25 #include <rte_common.h> 26 #include <rte_kvargs.h> 27 #include <rte_rwlock.h> 28 #include <rte_spinlock.h> 29 #include <rte_string_fns.h> 30 #include <rte_alarm.h> 31 #include <rte_eal_paging.h> 32 33 #include <mlx5_glue.h> 34 #include <mlx5_devx_cmds.h> 35 #include <mlx5_common.h> 36 #include <mlx5_common_mp.h> 37 #include <mlx5_common_mr.h> 38 #include <mlx5_malloc.h> 39 40 #include "mlx5_defs.h" 41 #include "mlx5.h" 42 #include "mlx5_common_os.h" 43 #include "mlx5_utils.h" 44 #include "mlx5_rxtx.h" 45 #include "mlx5_rx.h" 46 #include "mlx5_tx.h" 47 #include "mlx5_autoconf.h" 48 #include "mlx5_flow.h" 49 #include "rte_pmd_mlx5.h" 50 #include "mlx5_verbs.h" 51 #include "mlx5_nl.h" 52 #include "mlx5_devx.h" 53 54 #ifndef HAVE_IBV_MLX5_MOD_MPW 55 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 56 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 57 #endif 58 59 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 60 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 61 #endif 62 63 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 64 65 /* Spinlock for mlx5_shared_data allocation. */ 66 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 67 68 /* Process local data for secondary processes. */ 69 static struct mlx5_local_data mlx5_local_data; 70 71 /* rte flow indexed pool configuration. */ 72 static struct mlx5_indexed_pool_config icfg[] = { 73 { 74 .size = sizeof(struct rte_flow), 75 .trunk_size = 64, 76 .need_lock = 1, 77 .release_mem_en = 0, 78 .malloc = mlx5_malloc, 79 .free = mlx5_free, 80 .per_core_cache = 0, 81 .type = "ctl_flow_ipool", 82 }, 83 { 84 .size = sizeof(struct rte_flow), 85 .trunk_size = 64, 86 .grow_trunk = 3, 87 .grow_shift = 2, 88 .need_lock = 1, 89 .release_mem_en = 0, 90 .malloc = mlx5_malloc, 91 .free = mlx5_free, 92 .per_core_cache = 1 << 14, 93 .type = "rte_flow_ipool", 94 }, 95 { 96 .size = sizeof(struct rte_flow), 97 .trunk_size = 64, 98 .grow_trunk = 3, 99 .grow_shift = 2, 100 .need_lock = 1, 101 .release_mem_en = 0, 102 .malloc = mlx5_malloc, 103 .free = mlx5_free, 104 .per_core_cache = 0, 105 .type = "mcp_flow_ipool", 106 }, 107 }; 108 109 /** 110 * Set the completion channel file descriptor interrupt as non-blocking. 111 * 112 * @param[in] rxq_obj 113 * Pointer to RQ channel object, which includes the channel fd 114 * 115 * @param[out] fd 116 * The file descriptor (representing the interrupt) used in this channel. 117 * 118 * @return 119 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 120 */ 121 int 122 mlx5_os_set_nonblock_channel_fd(int fd) 123 { 124 int flags; 125 126 flags = fcntl(fd, F_GETFL); 127 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 128 } 129 130 /** 131 * Get mlx5 device attributes. The glue function query_device_ex() is called 132 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 133 * device attributes from the glue out parameter. 134 * 135 * @param sh 136 * Pointer to shared device context. 137 * 138 * @return 139 * 0 on success, a negative errno value otherwise and rte_errno is set. 140 */ 141 int 142 mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh) 143 { 144 int err; 145 struct mlx5_common_device *cdev = sh->cdev; 146 struct mlx5_hca_attr *hca_attr = &cdev->config.hca_attr; 147 struct ibv_device_attr_ex attr_ex = { .comp_mask = 0 }; 148 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 149 150 err = mlx5_glue->query_device_ex(cdev->ctx, NULL, &attr_ex); 151 if (err) { 152 rte_errno = errno; 153 return -rte_errno; 154 } 155 #ifdef HAVE_IBV_MLX5_MOD_SWP 156 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 157 #endif 158 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 159 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 160 #endif 161 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 162 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 163 #endif 164 err = mlx5_glue->dv_query_device(cdev->ctx, &dv_attr); 165 if (err) { 166 rte_errno = errno; 167 return -rte_errno; 168 } 169 memset(&sh->dev_cap, 0, sizeof(struct mlx5_dev_cap)); 170 if (mlx5_dev_is_pci(cdev->dev)) 171 sh->dev_cap.vf = mlx5_dev_is_vf_pci(RTE_DEV_TO_PCI(cdev->dev)); 172 else 173 sh->dev_cap.sf = 1; 174 sh->dev_cap.max_qp_wr = attr_ex.orig_attr.max_qp_wr; 175 sh->dev_cap.max_sge = attr_ex.orig_attr.max_sge; 176 sh->dev_cap.max_cq = attr_ex.orig_attr.max_cq; 177 sh->dev_cap.max_qp = attr_ex.orig_attr.max_qp; 178 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 179 sh->dev_cap.dest_tir = 1; 180 #endif 181 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) && defined(HAVE_MLX5DV_DR) 182 DRV_LOG(DEBUG, "DV flow is supported."); 183 sh->dev_cap.dv_flow_en = 1; 184 #endif 185 #ifdef HAVE_MLX5DV_DR_ESWITCH 186 if (hca_attr->eswitch_manager && sh->dev_cap.dv_flow_en && sh->esw_mode) 187 sh->dev_cap.dv_esw_en = 1; 188 #endif 189 /* 190 * Multi-packet send is supported by ConnectX-4 Lx PF as well 191 * as all ConnectX-5 devices. 192 */ 193 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 194 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 195 DRV_LOG(DEBUG, "Enhanced MPW is supported."); 196 sh->dev_cap.mps = MLX5_MPW_ENHANCED; 197 } else { 198 DRV_LOG(DEBUG, "MPW is supported."); 199 sh->dev_cap.mps = MLX5_MPW; 200 } 201 } else { 202 DRV_LOG(DEBUG, "MPW isn't supported."); 203 sh->dev_cap.mps = MLX5_MPW_DISABLED; 204 } 205 #if (RTE_CACHE_LINE_SIZE == 128) 206 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP) 207 sh->dev_cap.cqe_comp = 1; 208 DRV_LOG(DEBUG, "Rx CQE 128B compression is %ssupported.", 209 sh->dev_cap.cqe_comp ? "" : "not "); 210 #else 211 sh->dev_cap.cqe_comp = 1; 212 #endif 213 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 214 sh->dev_cap.mpls_en = 215 ((dv_attr.tunnel_offloads_caps & 216 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 217 (dv_attr.tunnel_offloads_caps & 218 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 219 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported.", 220 sh->dev_cap.mpls_en ? "" : "not "); 221 #else 222 DRV_LOG(WARNING, 223 "MPLS over GRE/UDP tunnel offloading disabled due to old OFED/rdma-core version or firmware configuration"); 224 #endif 225 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 226 sh->dev_cap.hw_padding = !!attr_ex.rx_pad_end_addr_align; 227 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 228 sh->dev_cap.hw_padding = !!(attr_ex.device_cap_flags_ex & 229 IBV_DEVICE_PCI_WRITE_END_PADDING); 230 #endif 231 sh->dev_cap.hw_csum = 232 !!(attr_ex.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM); 233 DRV_LOG(DEBUG, "Checksum offloading is %ssupported.", 234 sh->dev_cap.hw_csum ? "" : "not "); 235 sh->dev_cap.hw_vlan_strip = !!(attr_ex.raw_packet_caps & 236 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 237 DRV_LOG(DEBUG, "VLAN stripping is %ssupported.", 238 (sh->dev_cap.hw_vlan_strip ? "" : "not ")); 239 sh->dev_cap.hw_fcs_strip = !!(attr_ex.raw_packet_caps & 240 IBV_RAW_PACKET_CAP_SCATTER_FCS); 241 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 242 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 243 DRV_LOG(DEBUG, "Counters are not supported."); 244 #endif 245 /* 246 * DPDK doesn't support larger/variable indirection tables. 247 * Once DPDK supports it, take max size from device attr. 248 */ 249 sh->dev_cap.ind_table_max_size = 250 RTE_MIN(attr_ex.rss_caps.max_rwq_indirection_table_size, 251 (unsigned int)RTE_ETH_RSS_RETA_SIZE_512); 252 DRV_LOG(DEBUG, "Maximum Rx indirection table size is %u", 253 sh->dev_cap.ind_table_max_size); 254 sh->dev_cap.tso = (attr_ex.tso_caps.max_tso > 0 && 255 (attr_ex.tso_caps.supported_qpts & 256 (1 << IBV_QPT_RAW_PACKET))); 257 if (sh->dev_cap.tso) 258 sh->dev_cap.tso_max_payload_sz = attr_ex.tso_caps.max_tso; 259 strlcpy(sh->dev_cap.fw_ver, attr_ex.orig_attr.fw_ver, 260 sizeof(sh->dev_cap.fw_ver)); 261 #ifdef HAVE_IBV_MLX5_MOD_SWP 262 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 263 sh->dev_cap.swp = dv_attr.sw_parsing_caps.sw_parsing_offloads & 264 (MLX5_SW_PARSING_CAP | 265 MLX5_SW_PARSING_CSUM_CAP | 266 MLX5_SW_PARSING_TSO_CAP); 267 DRV_LOG(DEBUG, "SWP support: %u", sh->dev_cap.swp); 268 #endif 269 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 270 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 271 struct mlx5dv_striding_rq_caps *strd_rq_caps = 272 &dv_attr.striding_rq_caps; 273 274 sh->dev_cap.mprq.enabled = 1; 275 sh->dev_cap.mprq.log_min_stride_size = 276 strd_rq_caps->min_single_stride_log_num_of_bytes; 277 sh->dev_cap.mprq.log_max_stride_size = 278 strd_rq_caps->max_single_stride_log_num_of_bytes; 279 sh->dev_cap.mprq.log_min_stride_num = 280 strd_rq_caps->min_single_wqe_log_num_of_strides; 281 sh->dev_cap.mprq.log_max_stride_num = 282 strd_rq_caps->max_single_wqe_log_num_of_strides; 283 sh->dev_cap.mprq.log_min_stride_wqe_size = 284 cdev->config.devx ? 285 hca_attr->log_min_stride_wqe_sz : 286 MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 287 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %u", 288 sh->dev_cap.mprq.log_min_stride_size); 289 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %u", 290 sh->dev_cap.mprq.log_max_stride_size); 291 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %u", 292 sh->dev_cap.mprq.log_min_stride_num); 293 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %u", 294 sh->dev_cap.mprq.log_max_stride_num); 295 DRV_LOG(DEBUG, "\tmin_stride_wqe_log_size: %u", 296 sh->dev_cap.mprq.log_min_stride_wqe_size); 297 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 298 strd_rq_caps->supported_qpts); 299 DRV_LOG(DEBUG, "Device supports Multi-Packet RQ."); 300 } 301 #endif 302 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 303 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 304 sh->dev_cap.tunnel_en = dv_attr.tunnel_offloads_caps & 305 (MLX5_TUNNELED_OFFLOADS_VXLAN_CAP | 306 MLX5_TUNNELED_OFFLOADS_GRE_CAP | 307 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP); 308 } 309 if (sh->dev_cap.tunnel_en) { 310 DRV_LOG(DEBUG, "Tunnel offloading is supported for %s%s%s", 311 sh->dev_cap.tunnel_en & 312 MLX5_TUNNELED_OFFLOADS_VXLAN_CAP ? "[VXLAN]" : "", 313 sh->dev_cap.tunnel_en & 314 MLX5_TUNNELED_OFFLOADS_GRE_CAP ? "[GRE]" : "", 315 sh->dev_cap.tunnel_en & 316 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP ? "[GENEVE]" : ""); 317 } else { 318 DRV_LOG(DEBUG, "Tunnel offloading is not supported."); 319 } 320 #else 321 DRV_LOG(WARNING, 322 "Tunnel offloading disabled due to old OFED/rdma-core version"); 323 #endif 324 if (!sh->cdev->config.devx) 325 return 0; 326 /* Check capabilities for Packet Pacing. */ 327 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz.", 328 hca_attr->dev_freq_khz); 329 DRV_LOG(DEBUG, "Packet pacing is %ssupported.", 330 hca_attr->qos.packet_pacing ? "" : "not "); 331 DRV_LOG(DEBUG, "Cross channel ops are %ssupported.", 332 hca_attr->cross_channel ? "" : "not "); 333 DRV_LOG(DEBUG, "WQE index ignore is %ssupported.", 334 hca_attr->wqe_index_ignore ? "" : "not "); 335 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported.", 336 hca_attr->non_wire_sq ? "" : "not "); 337 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 338 hca_attr->log_max_static_sq_wq ? "" : "not ", 339 hca_attr->log_max_static_sq_wq); 340 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported.", 341 hca_attr->qos.wqe_rate_pp ? "" : "not "); 342 sh->dev_cap.txpp_en = hca_attr->qos.packet_pacing; 343 if (!hca_attr->cross_channel) { 344 DRV_LOG(DEBUG, 345 "Cross channel operations are required for packet pacing."); 346 sh->dev_cap.txpp_en = 0; 347 } 348 if (!hca_attr->wqe_index_ignore) { 349 DRV_LOG(DEBUG, 350 "WQE index ignore feature is required for packet pacing."); 351 sh->dev_cap.txpp_en = 0; 352 } 353 if (!hca_attr->non_wire_sq) { 354 DRV_LOG(DEBUG, 355 "Non-wire SQ feature is required for packet pacing."); 356 sh->dev_cap.txpp_en = 0; 357 } 358 if (!hca_attr->log_max_static_sq_wq) { 359 DRV_LOG(DEBUG, 360 "Static WQE SQ feature is required for packet pacing."); 361 sh->dev_cap.txpp_en = 0; 362 } 363 if (!hca_attr->qos.wqe_rate_pp) { 364 DRV_LOG(DEBUG, 365 "WQE rate mode is required for packet pacing."); 366 sh->dev_cap.txpp_en = 0; 367 } 368 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 369 DRV_LOG(DEBUG, 370 "DevX does not provide UAR offset, can't create queues for packet pacing."); 371 sh->dev_cap.txpp_en = 0; 372 #endif 373 sh->dev_cap.scatter_fcs_w_decap_disable = 374 hca_attr->scatter_fcs_w_decap_disable; 375 sh->dev_cap.rq_delay_drop_en = hca_attr->rq_delay_drop; 376 mlx5_rt_timestamp_config(sh, hca_attr); 377 return 0; 378 } 379 380 /** 381 * Detect misc5 support or not 382 * 383 * @param[in] priv 384 * Device private data pointer 385 */ 386 #ifdef HAVE_MLX5DV_DR 387 static void 388 __mlx5_discovery_misc5_cap(struct mlx5_priv *priv) 389 { 390 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 391 /* Dummy VxLAN matcher to detect rdma-core misc5 cap 392 * Case: IPv4--->UDP--->VxLAN--->vni 393 */ 394 void *tbl; 395 struct mlx5_flow_dv_match_params matcher_mask; 396 void *match_m; 397 void *matcher; 398 void *headers_m; 399 void *misc5_m; 400 uint32_t *tunnel_header_m; 401 struct mlx5dv_flow_matcher_attr dv_attr; 402 403 memset(&matcher_mask, 0, sizeof(matcher_mask)); 404 matcher_mask.size = sizeof(matcher_mask.buf); 405 match_m = matcher_mask.buf; 406 headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers); 407 misc5_m = MLX5_ADDR_OF(fte_match_param, 408 match_m, misc_parameters_5); 409 tunnel_header_m = (uint32_t *) 410 MLX5_ADDR_OF(fte_match_set_misc5, 411 misc5_m, tunnel_header_1); 412 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff); 413 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4); 414 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff); 415 *tunnel_header_m = 0xffffff; 416 417 tbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1); 418 if (!tbl) { 419 DRV_LOG(INFO, "No SW steering support"); 420 return; 421 } 422 dv_attr.type = IBV_FLOW_ATTR_NORMAL, 423 dv_attr.match_mask = (void *)&matcher_mask, 424 dv_attr.match_criteria_enable = 425 (1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) | 426 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT); 427 dv_attr.priority = 3; 428 #ifdef HAVE_MLX5DV_DR_ESWITCH 429 void *misc2_m; 430 if (priv->sh->config.dv_esw_en) { 431 /* FDB enabled reg_c_0 */ 432 dv_attr.match_criteria_enable |= 433 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT); 434 misc2_m = MLX5_ADDR_OF(fte_match_param, 435 match_m, misc_parameters_2); 436 MLX5_SET(fte_match_set_misc2, misc2_m, 437 metadata_reg_c_0, 0xffff); 438 } 439 #endif 440 matcher = mlx5_glue->dv_create_flow_matcher(priv->sh->cdev->ctx, 441 &dv_attr, tbl); 442 if (matcher) { 443 priv->sh->misc5_cap = 1; 444 mlx5_glue->dv_destroy_flow_matcher(matcher); 445 } 446 mlx5_glue->dr_destroy_flow_tbl(tbl); 447 #else 448 RTE_SET_USED(priv); 449 #endif 450 } 451 #endif 452 453 /** 454 * Initialize DR related data within private structure. 455 * Routine checks the reference counter and does actual 456 * resources creation/initialization only if counter is zero. 457 * 458 * @param[in] priv 459 * Pointer to the private device data structure. 460 * 461 * @return 462 * Zero on success, positive error code otherwise. 463 */ 464 static int 465 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 466 { 467 struct mlx5_dev_ctx_shared *sh = priv->sh; 468 char s[MLX5_NAME_SIZE] __rte_unused; 469 int err; 470 471 MLX5_ASSERT(sh && sh->refcnt); 472 if (sh->refcnt > 1) 473 return 0; 474 err = mlx5_alloc_table_hash_list(priv); 475 if (err) 476 goto error; 477 sh->default_miss_action = 478 mlx5_glue->dr_create_flow_action_default_miss(); 479 if (!sh->default_miss_action) 480 DRV_LOG(WARNING, "Default miss action is not supported."); 481 /* The resources below are only valid with DV support. */ 482 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 483 /* Init shared flex parsers list, no need lcore_share */ 484 snprintf(s, sizeof(s), "%s_flex_parsers_list", sh->ibdev_name); 485 sh->flex_parsers_dv = mlx5_list_create(s, sh, false, 486 mlx5_flex_parser_create_cb, 487 mlx5_flex_parser_match_cb, 488 mlx5_flex_parser_remove_cb, 489 mlx5_flex_parser_clone_cb, 490 mlx5_flex_parser_clone_free_cb); 491 if (!sh->flex_parsers_dv) 492 goto error; 493 if (priv->sh->config.dv_flow_en == 2) 494 return 0; 495 /* Init port id action list. */ 496 snprintf(s, sizeof(s), "%s_port_id_action_list", sh->ibdev_name); 497 sh->port_id_action_list = mlx5_list_create(s, sh, true, 498 flow_dv_port_id_create_cb, 499 flow_dv_port_id_match_cb, 500 flow_dv_port_id_remove_cb, 501 flow_dv_port_id_clone_cb, 502 flow_dv_port_id_clone_free_cb); 503 if (!sh->port_id_action_list) 504 goto error; 505 /* Init push vlan action list. */ 506 snprintf(s, sizeof(s), "%s_push_vlan_action_list", sh->ibdev_name); 507 sh->push_vlan_action_list = mlx5_list_create(s, sh, true, 508 flow_dv_push_vlan_create_cb, 509 flow_dv_push_vlan_match_cb, 510 flow_dv_push_vlan_remove_cb, 511 flow_dv_push_vlan_clone_cb, 512 flow_dv_push_vlan_clone_free_cb); 513 if (!sh->push_vlan_action_list) 514 goto error; 515 /* Init sample action list. */ 516 snprintf(s, sizeof(s), "%s_sample_action_list", sh->ibdev_name); 517 sh->sample_action_list = mlx5_list_create(s, sh, true, 518 flow_dv_sample_create_cb, 519 flow_dv_sample_match_cb, 520 flow_dv_sample_remove_cb, 521 flow_dv_sample_clone_cb, 522 flow_dv_sample_clone_free_cb); 523 if (!sh->sample_action_list) 524 goto error; 525 /* Init dest array action list. */ 526 snprintf(s, sizeof(s), "%s_dest_array_list", sh->ibdev_name); 527 sh->dest_array_list = mlx5_list_create(s, sh, true, 528 flow_dv_dest_array_create_cb, 529 flow_dv_dest_array_match_cb, 530 flow_dv_dest_array_remove_cb, 531 flow_dv_dest_array_clone_cb, 532 flow_dv_dest_array_clone_free_cb); 533 if (!sh->dest_array_list) 534 goto error; 535 #else 536 if (priv->sh->config.dv_flow_en == 2) 537 return 0; 538 #endif 539 #ifdef HAVE_MLX5DV_DR 540 void *domain; 541 542 /* Reference counter is zero, we should initialize structures. */ 543 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 544 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 545 if (!domain) { 546 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 547 err = errno; 548 goto error; 549 } 550 sh->rx_domain = domain; 551 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 552 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 553 if (!domain) { 554 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 555 err = errno; 556 goto error; 557 } 558 sh->tx_domain = domain; 559 #ifdef HAVE_MLX5DV_DR_ESWITCH 560 if (sh->config.dv_esw_en) { 561 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 562 MLX5DV_DR_DOMAIN_TYPE_FDB); 563 if (!domain) { 564 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 565 err = errno; 566 goto error; 567 } 568 sh->fdb_domain = domain; 569 } 570 /* 571 * The drop action is just some dummy placeholder in rdma-core. It 572 * does not belong to domains and has no any attributes, and, can be 573 * shared by the entire device. 574 */ 575 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop(); 576 if (!sh->dr_drop_action) { 577 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop"); 578 err = errno; 579 goto error; 580 } 581 #endif 582 if (!sh->tunnel_hub && sh->config.dv_miss_info) 583 err = mlx5_alloc_tunnel_hub(sh); 584 if (err) { 585 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 586 goto error; 587 } 588 if (sh->config.reclaim_mode == MLX5_RCM_AGGR) { 589 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 590 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 591 if (sh->fdb_domain) 592 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 593 } 594 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 595 if (!sh->config.allow_duplicate_pattern) { 596 #ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE 597 DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?"); 598 #endif 599 mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0); 600 mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0); 601 if (sh->fdb_domain) 602 mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0); 603 } 604 605 __mlx5_discovery_misc5_cap(priv); 606 #endif /* HAVE_MLX5DV_DR */ 607 LIST_INIT(&sh->shared_rxqs); 608 return 0; 609 error: 610 /* Rollback the created objects. */ 611 if (sh->rx_domain) { 612 mlx5_glue->dr_destroy_domain(sh->rx_domain); 613 sh->rx_domain = NULL; 614 } 615 if (sh->tx_domain) { 616 mlx5_glue->dr_destroy_domain(sh->tx_domain); 617 sh->tx_domain = NULL; 618 } 619 if (sh->fdb_domain) { 620 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 621 sh->fdb_domain = NULL; 622 } 623 if (sh->dr_drop_action) { 624 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 625 sh->dr_drop_action = NULL; 626 } 627 if (sh->pop_vlan_action) { 628 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 629 sh->pop_vlan_action = NULL; 630 } 631 if (sh->encaps_decaps) { 632 mlx5_hlist_destroy(sh->encaps_decaps); 633 sh->encaps_decaps = NULL; 634 } 635 if (sh->modify_cmds) { 636 mlx5_hlist_destroy(sh->modify_cmds); 637 sh->modify_cmds = NULL; 638 } 639 if (sh->tag_table) { 640 /* tags should be destroyed with flow before. */ 641 mlx5_hlist_destroy(sh->tag_table); 642 sh->tag_table = NULL; 643 } 644 if (sh->tunnel_hub) { 645 mlx5_release_tunnel_hub(sh, priv->dev_port); 646 sh->tunnel_hub = NULL; 647 } 648 mlx5_free_table_hash_list(priv); 649 if (sh->port_id_action_list) { 650 mlx5_list_destroy(sh->port_id_action_list); 651 sh->port_id_action_list = NULL; 652 } 653 if (sh->push_vlan_action_list) { 654 mlx5_list_destroy(sh->push_vlan_action_list); 655 sh->push_vlan_action_list = NULL; 656 } 657 if (sh->sample_action_list) { 658 mlx5_list_destroy(sh->sample_action_list); 659 sh->sample_action_list = NULL; 660 } 661 if (sh->dest_array_list) { 662 mlx5_list_destroy(sh->dest_array_list); 663 sh->dest_array_list = NULL; 664 } 665 return err; 666 } 667 668 /** 669 * Destroy DR related data within private structure. 670 * 671 * @param[in] priv 672 * Pointer to the private device data structure. 673 */ 674 void 675 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 676 { 677 struct mlx5_dev_ctx_shared *sh = priv->sh; 678 #ifdef HAVE_MLX5DV_DR 679 int i; 680 #endif 681 682 MLX5_ASSERT(sh && sh->refcnt); 683 if (sh->refcnt > 1) 684 return; 685 MLX5_ASSERT(LIST_EMPTY(&sh->shared_rxqs)); 686 #ifdef HAVE_MLX5DV_DR 687 if (sh->rx_domain) { 688 mlx5_glue->dr_destroy_domain(sh->rx_domain); 689 sh->rx_domain = NULL; 690 } 691 if (sh->tx_domain) { 692 mlx5_glue->dr_destroy_domain(sh->tx_domain); 693 sh->tx_domain = NULL; 694 } 695 #ifdef HAVE_MLX5DV_DR_ESWITCH 696 if (sh->fdb_domain) { 697 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 698 sh->fdb_domain = NULL; 699 } 700 if (sh->dr_drop_action) { 701 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 702 sh->dr_drop_action = NULL; 703 } 704 #endif 705 if (sh->pop_vlan_action) { 706 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 707 sh->pop_vlan_action = NULL; 708 } 709 for (i = 0; i < MLX5DR_TABLE_TYPE_MAX; i++) { 710 if (sh->send_to_kernel_action[i].action) { 711 void *action = sh->send_to_kernel_action[i].action; 712 713 mlx5_glue->destroy_flow_action(action); 714 sh->send_to_kernel_action[i].action = NULL; 715 } 716 if (sh->send_to_kernel_action[i].tbl) { 717 struct mlx5_flow_tbl_resource *tbl = 718 sh->send_to_kernel_action[i].tbl; 719 720 flow_dv_tbl_resource_release(sh, tbl); 721 sh->send_to_kernel_action[i].tbl = NULL; 722 } 723 } 724 #endif /* HAVE_MLX5DV_DR */ 725 if (sh->default_miss_action) 726 mlx5_glue->destroy_flow_action 727 (sh->default_miss_action); 728 if (sh->encaps_decaps) { 729 mlx5_hlist_destroy(sh->encaps_decaps); 730 sh->encaps_decaps = NULL; 731 } 732 if (sh->modify_cmds) { 733 mlx5_hlist_destroy(sh->modify_cmds); 734 sh->modify_cmds = NULL; 735 } 736 if (sh->tag_table) { 737 /* tags should be destroyed with flow before. */ 738 mlx5_hlist_destroy(sh->tag_table); 739 sh->tag_table = NULL; 740 } 741 if (sh->tunnel_hub) { 742 mlx5_release_tunnel_hub(sh, priv->dev_port); 743 sh->tunnel_hub = NULL; 744 } 745 mlx5_free_table_hash_list(priv); 746 if (sh->port_id_action_list) { 747 mlx5_list_destroy(sh->port_id_action_list); 748 sh->port_id_action_list = NULL; 749 } 750 if (sh->push_vlan_action_list) { 751 mlx5_list_destroy(sh->push_vlan_action_list); 752 sh->push_vlan_action_list = NULL; 753 } 754 if (sh->sample_action_list) { 755 mlx5_list_destroy(sh->sample_action_list); 756 sh->sample_action_list = NULL; 757 } 758 if (sh->dest_array_list) { 759 mlx5_list_destroy(sh->dest_array_list); 760 sh->dest_array_list = NULL; 761 } 762 } 763 764 /** 765 * Initialize shared data between primary and secondary process. 766 * 767 * A memzone is reserved by primary process and secondary processes attach to 768 * the memzone. 769 * 770 * @return 771 * 0 on success, a negative errno value otherwise and rte_errno is set. 772 */ 773 static int 774 mlx5_init_shared_data(void) 775 { 776 const struct rte_memzone *mz; 777 int ret = 0; 778 779 rte_spinlock_lock(&mlx5_shared_data_lock); 780 if (mlx5_shared_data == NULL) { 781 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 782 /* Allocate shared memory. */ 783 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 784 sizeof(*mlx5_shared_data), 785 SOCKET_ID_ANY, 0); 786 if (mz == NULL) { 787 DRV_LOG(ERR, 788 "Cannot allocate mlx5 shared data"); 789 ret = -rte_errno; 790 goto error; 791 } 792 mlx5_shared_data = mz->addr; 793 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 794 rte_spinlock_init(&mlx5_shared_data->lock); 795 } else { 796 /* Lookup allocated shared memory. */ 797 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 798 if (mz == NULL) { 799 DRV_LOG(ERR, 800 "Cannot attach mlx5 shared data"); 801 ret = -rte_errno; 802 goto error; 803 } 804 mlx5_shared_data = mz->addr; 805 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 806 } 807 } 808 error: 809 rte_spinlock_unlock(&mlx5_shared_data_lock); 810 return ret; 811 } 812 813 /** 814 * PMD global initialization. 815 * 816 * Independent from individual device, this function initializes global 817 * per-PMD data structures distinguishing primary and secondary processes. 818 * Hence, each initialization is called once per a process. 819 * 820 * @return 821 * 0 on success, a negative errno value otherwise and rte_errno is set. 822 */ 823 static int 824 mlx5_init_once(void) 825 { 826 struct mlx5_shared_data *sd; 827 struct mlx5_local_data *ld = &mlx5_local_data; 828 int ret = 0; 829 830 if (mlx5_init_shared_data()) 831 return -rte_errno; 832 sd = mlx5_shared_data; 833 MLX5_ASSERT(sd); 834 rte_spinlock_lock(&sd->lock); 835 switch (rte_eal_process_type()) { 836 case RTE_PROC_PRIMARY: 837 if (sd->init_done) 838 break; 839 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 840 mlx5_mp_os_primary_handle); 841 if (ret) 842 goto out; 843 sd->init_done = true; 844 break; 845 case RTE_PROC_SECONDARY: 846 if (ld->init_done) 847 break; 848 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 849 mlx5_mp_os_secondary_handle); 850 if (ret) 851 goto out; 852 ++sd->secondary_cnt; 853 ld->init_done = true; 854 break; 855 default: 856 break; 857 } 858 out: 859 rte_spinlock_unlock(&sd->lock); 860 return ret; 861 } 862 863 /** 864 * DR flow drop action support detect. 865 * 866 * @param dev 867 * Pointer to rte_eth_dev structure. 868 * 869 */ 870 static void 871 mlx5_flow_drop_action_config(struct rte_eth_dev *dev __rte_unused) 872 { 873 #ifdef HAVE_MLX5DV_DR 874 struct mlx5_priv *priv = dev->data->dev_private; 875 876 if (!priv->sh->config.dv_flow_en || !priv->sh->dr_drop_action) 877 return; 878 /** 879 * DR supports drop action placeholder when it is supported; 880 * otherwise, use the queue drop action. 881 */ 882 if (!priv->sh->drop_action_check_flag) { 883 if (!mlx5_flow_discover_dr_action_support(dev)) 884 priv->sh->dr_root_drop_action_en = 1; 885 priv->sh->drop_action_check_flag = 1; 886 } 887 if (priv->sh->dr_root_drop_action_en) 888 priv->root_drop_action = priv->sh->dr_drop_action; 889 else 890 priv->root_drop_action = priv->drop_queue.hrxq->action; 891 #endif 892 } 893 894 static void 895 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 896 { 897 struct mlx5_priv *priv = dev->data->dev_private; 898 void *ctx = priv->sh->cdev->ctx; 899 900 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 901 if (!priv->q_counters) { 902 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 903 struct ibv_wq *wq; 904 905 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 906 "by DevX - fall-back to use the kernel driver global " 907 "queue counter.", dev->data->port_id); 908 /* Create WQ by kernel and query its queue counter ID. */ 909 if (cq) { 910 wq = mlx5_glue->create_wq(ctx, 911 &(struct ibv_wq_init_attr){ 912 .wq_type = IBV_WQT_RQ, 913 .max_wr = 1, 914 .max_sge = 1, 915 .pd = priv->sh->cdev->pd, 916 .cq = cq, 917 }); 918 if (wq) { 919 /* Counter is assigned only on RDY state. */ 920 int ret = mlx5_glue->modify_wq(wq, 921 &(struct ibv_wq_attr){ 922 .attr_mask = IBV_WQ_ATTR_STATE, 923 .wq_state = IBV_WQS_RDY, 924 }); 925 926 if (ret == 0) 927 mlx5_devx_cmd_wq_query(wq, 928 &priv->counter_set_id); 929 claim_zero(mlx5_glue->destroy_wq(wq)); 930 } 931 claim_zero(mlx5_glue->destroy_cq(cq)); 932 } 933 } else { 934 priv->counter_set_id = priv->q_counters->id; 935 } 936 if (priv->counter_set_id == 0) 937 DRV_LOG(INFO, "Part of the port %d statistics will not be " 938 "available.", dev->data->port_id); 939 } 940 941 /** 942 * Check if representor spawn info match devargs. 943 * 944 * @param spawn 945 * Verbs device parameters (name, port, switch_info) to spawn. 946 * @param eth_da 947 * Device devargs to probe. 948 * 949 * @return 950 * Match result. 951 */ 952 static bool 953 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 954 struct rte_eth_devargs *eth_da) 955 { 956 struct mlx5_switch_info *switch_info = &spawn->info; 957 unsigned int p, f; 958 uint16_t id; 959 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 960 eth_da->type); 961 962 /* 963 * Assuming Multiport E-Switch device was detected, 964 * if spawned port is an uplink, check if the port 965 * was requested through representor devarg. 966 */ 967 if (mlx5_is_probed_port_on_mpesw_device(spawn) && 968 switch_info->name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) { 969 for (p = 0; p < eth_da->nb_ports; ++p) 970 if (switch_info->port_name == eth_da->ports[p]) 971 return true; 972 rte_errno = EBUSY; 973 return false; 974 } 975 switch (eth_da->type) { 976 case RTE_ETH_REPRESENTOR_PF: 977 /* 978 * PF representors provided in devargs translate to uplink ports, but 979 * if and only if the device is a part of MPESW device. 980 */ 981 if (!mlx5_is_probed_port_on_mpesw_device(spawn)) { 982 rte_errno = EBUSY; 983 return false; 984 } 985 break; 986 case RTE_ETH_REPRESENTOR_SF: 987 if (!(spawn->info.port_name == -1 && 988 switch_info->name_type == 989 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 990 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 991 rte_errno = EBUSY; 992 return false; 993 } 994 break; 995 case RTE_ETH_REPRESENTOR_VF: 996 /* Allows HPF representor index -1 as exception. */ 997 if (!(spawn->info.port_name == -1 && 998 switch_info->name_type == 999 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 1000 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 1001 rte_errno = EBUSY; 1002 return false; 1003 } 1004 break; 1005 case RTE_ETH_REPRESENTOR_NONE: 1006 rte_errno = EBUSY; 1007 return false; 1008 default: 1009 rte_errno = ENOTSUP; 1010 DRV_LOG(ERR, "unsupported representor type"); 1011 return false; 1012 } 1013 /* Check representor ID: */ 1014 for (p = 0; p < eth_da->nb_ports; ++p) { 1015 if (!mlx5_is_probed_port_on_mpesw_device(spawn) && spawn->pf_bond < 0) { 1016 /* For non-LAG mode, allow and ignore pf. */ 1017 switch_info->pf_num = eth_da->ports[p]; 1018 repr_id = mlx5_representor_id_encode(switch_info, 1019 eth_da->type); 1020 } 1021 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 1022 id = MLX5_REPRESENTOR_ID 1023 (eth_da->ports[p], eth_da->type, 1024 eth_da->representor_ports[f]); 1025 if (repr_id == id) 1026 return true; 1027 } 1028 } 1029 rte_errno = EBUSY; 1030 return false; 1031 } 1032 1033 /** 1034 * Spawn an Ethernet device from Verbs information. 1035 * 1036 * @param dpdk_dev 1037 * Backing DPDK device. 1038 * @param spawn 1039 * Verbs device parameters (name, port, switch_info) to spawn. 1040 * @param eth_da 1041 * Device arguments. 1042 * @param mkvlist 1043 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 1044 * 1045 * @return 1046 * A valid Ethernet device object on success, NULL otherwise and rte_errno 1047 * is set. The following errors are defined: 1048 * 1049 * EBUSY: device is not supposed to be spawned. 1050 * EEXIST: device is already spawned 1051 */ 1052 static struct rte_eth_dev * 1053 mlx5_dev_spawn(struct rte_device *dpdk_dev, 1054 struct mlx5_dev_spawn_data *spawn, 1055 struct rte_eth_devargs *eth_da, 1056 struct mlx5_kvargs_ctrl *mkvlist) 1057 { 1058 const struct mlx5_switch_info *switch_info = &spawn->info; 1059 struct mlx5_dev_ctx_shared *sh = NULL; 1060 struct ibv_port_attr port_attr = { .state = IBV_PORT_NOP }; 1061 struct rte_eth_dev *eth_dev = NULL; 1062 struct mlx5_priv *priv = NULL; 1063 int err = 0; 1064 struct rte_ether_addr mac; 1065 char name[RTE_ETH_NAME_MAX_LEN]; 1066 int own_domain_id = 0; 1067 uint16_t port_id; 1068 struct mlx5_port_info vport_info = { .query_flags = 0 }; 1069 int nl_rdma; 1070 int i; 1071 1072 /* Determine if this port representor is supposed to be spawned. */ 1073 if (switch_info->representor && dpdk_dev->devargs && 1074 !mlx5_representor_match(spawn, eth_da)) 1075 return NULL; 1076 /* Build device name. */ 1077 if (spawn->pf_bond >= 0) { 1078 /* Bonding device. */ 1079 if (!switch_info->representor) { 1080 err = snprintf(name, sizeof(name), "%s_%s", 1081 dpdk_dev->name, spawn->phys_dev_name); 1082 } else { 1083 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 1084 dpdk_dev->name, spawn->phys_dev_name, 1085 switch_info->ctrl_num, 1086 switch_info->pf_num, 1087 switch_info->name_type == 1088 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 1089 switch_info->port_name); 1090 } 1091 } else if (mlx5_is_probed_port_on_mpesw_device(spawn)) { 1092 /* MPESW device. */ 1093 if (switch_info->name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) { 1094 err = snprintf(name, sizeof(name), "%s_p%d", 1095 dpdk_dev->name, spawn->mpesw_port); 1096 } else { 1097 err = snprintf(name, sizeof(name), "%s_representor_c%dpf%d%s%u", 1098 dpdk_dev->name, 1099 switch_info->ctrl_num, 1100 switch_info->pf_num, 1101 switch_info->name_type == 1102 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 1103 switch_info->port_name); 1104 } 1105 } else { 1106 /* Single device. */ 1107 if (!switch_info->representor) 1108 strlcpy(name, dpdk_dev->name, sizeof(name)); 1109 else 1110 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 1111 dpdk_dev->name, 1112 switch_info->name_type == 1113 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 1114 switch_info->port_name); 1115 } 1116 if (err >= (int)sizeof(name)) 1117 DRV_LOG(WARNING, "device name overflow %s", name); 1118 /* check if the device is already spawned */ 1119 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 1120 /* 1121 * When device is already spawned, its devargs should be set 1122 * as used. otherwise, mlx5_kvargs_validate() will fail. 1123 */ 1124 if (mkvlist) 1125 mlx5_port_args_set_used(name, port_id, mkvlist); 1126 rte_errno = EEXIST; 1127 return NULL; 1128 } 1129 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 1130 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 1131 struct mlx5_mp_id mp_id; 1132 int fd; 1133 1134 eth_dev = rte_eth_dev_attach_secondary(name); 1135 if (eth_dev == NULL) { 1136 DRV_LOG(ERR, "can not attach rte ethdev"); 1137 rte_errno = ENOMEM; 1138 return NULL; 1139 } 1140 eth_dev->device = dpdk_dev; 1141 eth_dev->dev_ops = &mlx5_dev_sec_ops; 1142 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1143 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1144 err = mlx5_proc_priv_init(eth_dev); 1145 if (err) 1146 return NULL; 1147 mlx5_mp_id_init(&mp_id, eth_dev->data->port_id); 1148 /* Receive command fd from primary process */ 1149 fd = mlx5_mp_req_verbs_cmd_fd(&mp_id); 1150 if (fd < 0) 1151 goto err_secondary; 1152 /* Remap UAR for Tx queues. */ 1153 err = mlx5_tx_uar_init_secondary(eth_dev, fd); 1154 close(fd); 1155 if (err) 1156 goto err_secondary; 1157 /* 1158 * Ethdev pointer is still required as input since 1159 * the primary device is not accessible from the 1160 * secondary process. 1161 */ 1162 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 1163 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 1164 return eth_dev; 1165 err_secondary: 1166 mlx5_dev_close(eth_dev); 1167 return NULL; 1168 } 1169 sh = mlx5_alloc_shared_dev_ctx(spawn, mkvlist); 1170 if (!sh) 1171 return NULL; 1172 nl_rdma = mlx5_nl_init(NETLINK_RDMA, 0); 1173 /* Check port status. */ 1174 if (spawn->phys_port <= UINT8_MAX) { 1175 /* Legacy Verbs api only support u8 port number. */ 1176 err = mlx5_glue->query_port(sh->cdev->ctx, spawn->phys_port, 1177 &port_attr); 1178 if (err) { 1179 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1180 goto error; 1181 } 1182 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1183 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1184 err = EINVAL; 1185 goto error; 1186 } 1187 } else if (nl_rdma >= 0) { 1188 /* IB doesn't allow more than 255 ports, must be Ethernet. */ 1189 err = mlx5_nl_port_state(nl_rdma, 1190 spawn->phys_dev_name, 1191 spawn->phys_port); 1192 if (err < 0) { 1193 DRV_LOG(INFO, "Failed to get netlink port state: %s", 1194 strerror(rte_errno)); 1195 err = -rte_errno; 1196 goto error; 1197 } 1198 port_attr.state = (enum ibv_port_state)err; 1199 } 1200 if (port_attr.state != IBV_PORT_ACTIVE) 1201 DRV_LOG(INFO, "port is not active: \"%s\" (%d)", 1202 mlx5_glue->port_state_str(port_attr.state), 1203 port_attr.state); 1204 /* Allocate private eth device data. */ 1205 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1206 sizeof(*priv), 1207 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1208 if (priv == NULL) { 1209 DRV_LOG(ERR, "priv allocation failure"); 1210 err = ENOMEM; 1211 goto error; 1212 } 1213 /* 1214 * When user configures remote PD and CTX and device creates RxQ by 1215 * DevX, external RxQ is both supported and requested. 1216 */ 1217 if (mlx5_imported_pd_and_ctx(sh->cdev) && mlx5_devx_obj_ops_en(sh)) { 1218 priv->ext_rxqs = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1219 sizeof(struct mlx5_external_q) * 1220 MLX5_MAX_EXT_RX_QUEUES, 0, 1221 SOCKET_ID_ANY); 1222 if (priv->ext_rxqs == NULL) { 1223 DRV_LOG(ERR, "Fail to allocate external RxQ array."); 1224 err = ENOMEM; 1225 goto error; 1226 } 1227 priv->ext_txqs = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1228 sizeof(struct mlx5_external_q) * 1229 MLX5_MAX_EXT_TX_QUEUES, 0, 1230 SOCKET_ID_ANY); 1231 if (priv->ext_txqs == NULL) { 1232 DRV_LOG(ERR, "Fail to allocate external TxQ array."); 1233 err = ENOMEM; 1234 goto error; 1235 } 1236 DRV_LOG(DEBUG, "External queue is supported."); 1237 } 1238 priv->sh = sh; 1239 priv->dev_port = spawn->phys_port; 1240 priv->pci_dev = spawn->pci_dev; 1241 priv->mtu = RTE_ETHER_MTU; 1242 /* Some internal functions rely on Netlink sockets, open them now. */ 1243 priv->nl_socket_rdma = nl_rdma; 1244 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE, 0); 1245 priv->representor = !!switch_info->representor; 1246 priv->master = !!switch_info->master; 1247 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1248 priv->vport_meta_tag = 0; 1249 priv->vport_meta_mask = 0; 1250 priv->pf_bond = spawn->pf_bond; 1251 priv->mpesw_port = spawn->mpesw_port; 1252 priv->mpesw_uplink = false; 1253 priv->mpesw_owner = spawn->info.mpesw_owner; 1254 if (mlx5_is_port_on_mpesw_device(priv)) 1255 priv->mpesw_uplink = (spawn->info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK); 1256 1257 DRV_LOG(DEBUG, 1258 "dev_port=%u bus=%s pci=%s master=%d representor=%d pf_bond=%d " 1259 "mpesw_port=%d mpesw_uplink=%d", 1260 priv->dev_port, dpdk_dev->bus->name, 1261 priv->pci_dev ? priv->pci_dev->name : "NONE", 1262 priv->master, priv->representor, priv->pf_bond, 1263 priv->mpesw_port, priv->mpesw_uplink); 1264 1265 if (mlx5_is_port_on_mpesw_device(priv) && priv->sh->config.dv_flow_en != 2) { 1266 DRV_LOG(ERR, "MPESW device is supported only with HWS"); 1267 err = ENOTSUP; 1268 goto error; 1269 } 1270 /* 1271 * If we have E-Switch we should determine the vport attributes. 1272 * E-Switch may use either source vport field or reg_c[0] metadata 1273 * register to match on vport index. The engaged part of metadata 1274 * register is defined by mask. 1275 */ 1276 if (sh->esw_mode) { 1277 err = mlx5_glue->devx_port_query(sh->cdev->ctx, 1278 spawn->phys_port, 1279 &vport_info); 1280 if (err) { 1281 DRV_LOG(WARNING, 1282 "Cannot query devx port %d on device %s", 1283 spawn->phys_port, spawn->phys_dev_name); 1284 vport_info.query_flags = 0; 1285 } 1286 } 1287 if (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) { 1288 priv->vport_meta_tag = vport_info.vport_meta_tag; 1289 priv->vport_meta_mask = vport_info.vport_meta_mask; 1290 if (!priv->vport_meta_mask) { 1291 DRV_LOG(ERR, 1292 "vport zero mask for port %d on bonding device %s", 1293 spawn->phys_port, spawn->phys_dev_name); 1294 err = ENOTSUP; 1295 goto error; 1296 } 1297 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1298 DRV_LOG(ERR, 1299 "Invalid vport tag for port %d on bonding device %s", 1300 spawn->phys_port, spawn->phys_dev_name); 1301 err = ENOTSUP; 1302 goto error; 1303 } 1304 } 1305 if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) { 1306 priv->vport_id = vport_info.vport_id; 1307 } else if (spawn->pf_bond >= 0 && sh->esw_mode) { 1308 DRV_LOG(ERR, 1309 "Cannot deduce vport index for port %d on bonding device %s", 1310 spawn->phys_port, spawn->phys_dev_name); 1311 err = ENOTSUP; 1312 goto error; 1313 } else { 1314 /* 1315 * Suppose vport index in compatible way. Kernel/rdma_core 1316 * support single E-Switch per PF configurations only and 1317 * vport_id field contains the vport index for associated VF, 1318 * which is deduced from representor port name. 1319 * For example, let's have the IB device port 10, it has 1320 * attached network device eth0, which has port name attribute 1321 * pf0vf2, we can deduce the VF number as 2, and set vport index 1322 * as 3 (2+1). This assigning schema should be changed if the 1323 * multiple E-Switch instances per PF configurations or/and PCI 1324 * subfunctions are added. 1325 */ 1326 priv->vport_id = switch_info->representor ? 1327 switch_info->port_name + 1 : -1; 1328 } 1329 priv->representor_id = mlx5_representor_id_encode(switch_info, 1330 eth_da->type); 1331 /* 1332 * Look for sibling devices in order to reuse their switch domain 1333 * if any, otherwise allocate one. 1334 */ 1335 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1336 const struct mlx5_priv *opriv = 1337 rte_eth_devices[port_id].data->dev_private; 1338 1339 if (!opriv || 1340 opriv->sh != priv->sh || 1341 opriv->domain_id == 1342 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1343 continue; 1344 priv->domain_id = opriv->domain_id; 1345 DRV_LOG(DEBUG, "dev_port-%u inherit domain_id=%u\n", 1346 priv->dev_port, priv->domain_id); 1347 break; 1348 } 1349 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1350 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1351 if (err) { 1352 err = rte_errno; 1353 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1354 strerror(rte_errno)); 1355 goto error; 1356 } 1357 own_domain_id = 1; 1358 DRV_LOG(DEBUG, "dev_port-%u new domain_id=%u\n", 1359 priv->dev_port, priv->domain_id); 1360 } 1361 if (sh->cdev->config.devx) { 1362 struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; 1363 1364 sh->steering_format_version = hca_attr->steering_format_version; 1365 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO_EXT) 1366 if (hca_attr->qos.sup && hca_attr->qos.flow_meter_old && 1367 sh->config.dv_flow_en) { 1368 if (sh->registers.aso_reg != REG_NON) { 1369 priv->mtr_en = 1; 1370 priv->mtr_reg_share = hca_attr->qos.flow_meter; 1371 } 1372 } 1373 if (hca_attr->qos.sup && hca_attr->qos.flow_meter_aso_sup) { 1374 uint32_t log_obj_size = 1375 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); 1376 if (log_obj_size >= 1377 hca_attr->qos.log_meter_aso_granularity && 1378 log_obj_size <= 1379 hca_attr->qos.log_meter_aso_max_alloc) 1380 sh->meter_aso_en = 1; 1381 } 1382 if (priv->mtr_en) { 1383 err = mlx5_aso_flow_mtrs_mng_init(priv->sh); 1384 if (err) { 1385 err = -err; 1386 goto error; 1387 } 1388 } 1389 if (hca_attr->flow.tunnel_header_0_1) 1390 sh->tunnel_header_0_1 = 1; 1391 if (hca_attr->flow.tunnel_header_2_3) 1392 sh->tunnel_header_2_3 = 1; 1393 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO_EXT */ 1394 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1395 if (hca_attr->flow_hit_aso && sh->registers.aso_reg == REG_C_3) { 1396 sh->flow_hit_aso_en = 1; 1397 err = mlx5_flow_aso_age_mng_init(sh); 1398 if (err) { 1399 err = -err; 1400 goto error; 1401 } 1402 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1403 } 1404 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1405 #if defined (HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ 1406 defined (HAVE_MLX5_DR_ACTION_ASO_CT) 1407 /* HWS create CT ASO SQ based on HWS configure queue number. */ 1408 if (sh->config.dv_flow_en != 2 && 1409 hca_attr->ct_offload && sh->registers.aso_reg == REG_C_3) { 1410 err = mlx5_flow_aso_ct_mng_init(sh); 1411 if (err) { 1412 err = -err; 1413 goto error; 1414 } 1415 DRV_LOG(DEBUG, "CT ASO is supported."); 1416 sh->ct_aso_en = 1; 1417 } 1418 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ 1419 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1420 if (hca_attr->log_max_ft_sampler_num > 0 && 1421 sh->config.dv_flow_en) { 1422 priv->sampler_en = 1; 1423 DRV_LOG(DEBUG, "Sampler enabled!"); 1424 } else { 1425 priv->sampler_en = 0; 1426 if (!hca_attr->log_max_ft_sampler_num) 1427 DRV_LOG(WARNING, 1428 "No available register for sampler."); 1429 else 1430 DRV_LOG(DEBUG, "DV flow is not supported!"); 1431 } 1432 #endif 1433 if (hca_attr->lag_rx_port_affinity) { 1434 sh->lag_rx_port_affinity_en = 1; 1435 DRV_LOG(DEBUG, "LAG Rx Port Affinity enabled"); 1436 } 1437 priv->num_lag_ports = hca_attr->num_lag_ports; 1438 DRV_LOG(DEBUG, "The number of lag ports is %d", priv->num_lag_ports); 1439 } 1440 /* Process parameters and store port configuration on priv structure. */ 1441 err = mlx5_port_args_config(priv, mkvlist, &priv->config); 1442 if (err) { 1443 err = rte_errno; 1444 DRV_LOG(ERR, "Failed to process port configure: %s", 1445 strerror(rte_errno)); 1446 goto error; 1447 } 1448 eth_dev = rte_eth_dev_allocate(name); 1449 if (eth_dev == NULL) { 1450 DRV_LOG(ERR, "can not allocate rte ethdev"); 1451 err = ENOMEM; 1452 goto error; 1453 } 1454 if (priv->representor) { 1455 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1456 eth_dev->data->representor_id = priv->representor_id; 1457 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1458 struct mlx5_priv *opriv = 1459 rte_eth_devices[port_id].data->dev_private; 1460 if (opriv && 1461 opriv->master && 1462 opriv->domain_id == priv->domain_id && 1463 opriv->sh == priv->sh) { 1464 eth_dev->data->backer_port_id = port_id; 1465 break; 1466 } 1467 } 1468 if (port_id >= RTE_MAX_ETHPORTS) 1469 eth_dev->data->backer_port_id = eth_dev->data->port_id; 1470 } 1471 priv->mp_id.port_id = eth_dev->data->port_id; 1472 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1473 /* 1474 * Store associated network device interface index. This index 1475 * is permanent throughout the lifetime of device. So, we may store 1476 * the ifindex here and use the cached value further. 1477 */ 1478 MLX5_ASSERT(spawn->ifindex); 1479 priv->if_index = spawn->ifindex; 1480 priv->lag_affinity_idx = sh->refcnt - 1; 1481 eth_dev->data->dev_private = priv; 1482 priv->dev_data = eth_dev->data; 1483 eth_dev->data->mac_addrs = priv->mac; 1484 eth_dev->device = dpdk_dev; 1485 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1486 /* Configure the first MAC address by default. */ 1487 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1488 DRV_LOG(ERR, 1489 "port %u cannot get MAC address, is mlx5_en" 1490 " loaded? (errno: %s)", 1491 eth_dev->data->port_id, strerror(rte_errno)); 1492 err = ENODEV; 1493 goto error; 1494 } 1495 DRV_LOG(INFO, 1496 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT, 1497 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac)); 1498 #ifdef RTE_LIBRTE_MLX5_DEBUG 1499 { 1500 char ifname[MLX5_NAMESIZE]; 1501 1502 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1503 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1504 eth_dev->data->port_id, ifname); 1505 else 1506 DRV_LOG(DEBUG, "port %u ifname is unknown", 1507 eth_dev->data->port_id); 1508 } 1509 #endif 1510 /* Get actual MTU if possible. */ 1511 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1512 if (err) { 1513 err = rte_errno; 1514 goto error; 1515 } 1516 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1517 priv->mtu); 1518 /* Initialize burst functions to prevent crashes before link-up. */ 1519 eth_dev->rx_pkt_burst = rte_eth_pkt_burst_dummy; 1520 eth_dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; 1521 eth_dev->dev_ops = &mlx5_dev_ops; 1522 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1523 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1524 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1525 /* Register MAC address. */ 1526 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1527 if (sh->dev_cap.vf && sh->config.vf_nl_en) 1528 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1529 mlx5_ifindex(eth_dev), 1530 eth_dev->data->mac_addrs, 1531 MLX5_MAX_MAC_ADDRESSES); 1532 priv->ctrl_flows = 0; 1533 rte_spinlock_init(&priv->flow_list_lock); 1534 TAILQ_INIT(&priv->flow_meters); 1535 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR); 1536 if (!priv->mtr_profile_tbl) 1537 goto error; 1538 /* Bring Ethernet device up. */ 1539 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1540 eth_dev->data->port_id); 1541 /* Read link status in case it is up and there will be no event. */ 1542 mlx5_link_update(eth_dev, 0); 1543 /* Watch LSC interrupts between port probe and port start. */ 1544 priv->sh->port[priv->dev_port - 1].nl_ih_port_id = 1545 eth_dev->data->port_id; 1546 mlx5_set_link_up(eth_dev); 1547 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 1548 icfg[i].release_mem_en = !!sh->config.reclaim_mode; 1549 if (sh->config.reclaim_mode) 1550 icfg[i].per_core_cache = 0; 1551 priv->flows[i] = mlx5_ipool_create(&icfg[i]); 1552 if (!priv->flows[i]) 1553 goto error; 1554 } 1555 /* Create context for virtual machine VLAN workaround. */ 1556 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1557 if (sh->config.dv_flow_en) { 1558 err = mlx5_alloc_shared_dr(priv); 1559 if (err) 1560 goto error; 1561 if (mlx5_flex_item_port_init(eth_dev) < 0) 1562 goto error; 1563 } 1564 if (mlx5_devx_obj_ops_en(sh)) { 1565 priv->obj_ops = devx_obj_ops; 1566 mlx5_queue_counter_id_prepare(eth_dev); 1567 priv->obj_ops.lb_dummy_queue_create = 1568 mlx5_rxq_ibv_obj_dummy_lb_create; 1569 priv->obj_ops.lb_dummy_queue_release = 1570 mlx5_rxq_ibv_obj_dummy_lb_release; 1571 } else if (spawn->max_port > UINT8_MAX) { 1572 /* Verbs can't support ports larger than 255 by design. */ 1573 DRV_LOG(ERR, "must enable DV and ESW when RDMA link ports > 255"); 1574 err = ENOTSUP; 1575 goto error; 1576 } else { 1577 priv->obj_ops = ibv_obj_ops; 1578 } 1579 if (sh->config.tx_pp && 1580 priv->obj_ops.txq_obj_new != mlx5_txq_devx_obj_new) { 1581 /* 1582 * HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support 1583 * packet pacing and already checked above. 1584 * Hence, we should only make sure the SQs will be created 1585 * with DevX, not with Verbs. 1586 * Verbs allocates the SQ UAR on its own and it can't be shared 1587 * with Clock Queue UAR as required for Tx scheduling. 1588 */ 1589 DRV_LOG(ERR, "Verbs SQs, UAR can't be shared as required for packet pacing"); 1590 err = ENODEV; 1591 goto error; 1592 } 1593 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1594 if (!priv->drop_queue.hrxq) 1595 goto error; 1596 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true, 1597 mlx5_hrxq_create_cb, 1598 mlx5_hrxq_match_cb, 1599 mlx5_hrxq_remove_cb, 1600 mlx5_hrxq_clone_cb, 1601 mlx5_hrxq_clone_free_cb); 1602 if (!priv->hrxqs) 1603 goto error; 1604 mlx5_set_metadata_mask(eth_dev); 1605 if (sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1606 !priv->sh->dv_regc0_mask) { 1607 DRV_LOG(ERR, "metadata mode %u is not supported " 1608 "(no metadata reg_c[0] is available)", 1609 sh->config.dv_xmeta_en); 1610 err = ENOTSUP; 1611 goto error; 1612 } 1613 rte_rwlock_init(&priv->ind_tbls_lock); 1614 if (sh->phdev->config.ipv6_tc_fallback == MLX5_IPV6_TC_UNKNOWN) { 1615 sh->phdev->config.ipv6_tc_fallback = MLX5_IPV6_TC_OK; 1616 if (!sh->cdev->config.hca_attr.modify_outer_ipv6_traffic_class || 1617 (sh->config.dv_flow_en == 1 && mlx5_flow_discover_ipv6_tc_support(eth_dev))) 1618 sh->phdev->config.ipv6_tc_fallback = MLX5_IPV6_TC_FALLBACK; 1619 } 1620 if (priv->sh->config.dv_flow_en == 2) { 1621 #ifdef HAVE_MLX5_HWS_SUPPORT 1622 if (priv->sh->config.dv_esw_en) { 1623 uint32_t usable_bits; 1624 uint32_t required_bits; 1625 1626 if (priv->sh->dv_regc0_mask == UINT32_MAX) { 1627 DRV_LOG(ERR, "E-Switch port metadata is required when using HWS " 1628 "but it is disabled (configure it through devlink)"); 1629 err = ENOTSUP; 1630 goto error; 1631 } 1632 if (priv->sh->dv_regc0_mask == 0) { 1633 DRV_LOG(ERR, "E-Switch with HWS is not supported " 1634 "(no available bits in reg_c[0])"); 1635 err = ENOTSUP; 1636 goto error; 1637 } 1638 usable_bits = rte_popcount32(priv->sh->dv_regc0_mask); 1639 required_bits = rte_popcount32(priv->vport_meta_mask); 1640 if (usable_bits < required_bits) { 1641 DRV_LOG(ERR, "Not enough bits available in reg_c[0] to provide " 1642 "representor matching."); 1643 err = ENOTSUP; 1644 goto error; 1645 } 1646 } 1647 if (priv->vport_meta_mask) 1648 flow_hw_set_port_info(eth_dev); 1649 if (priv->sh->config.dv_esw_en && 1650 priv->sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1651 priv->sh->config.dv_xmeta_en != MLX5_XMETA_MODE_META32_HWS) { 1652 DRV_LOG(ERR, 1653 "metadata mode %u is not supported in HWS eswitch mode", 1654 priv->sh->config.dv_xmeta_en); 1655 err = ENOTSUP; 1656 goto error; 1657 } 1658 if (priv->sh->config.dv_esw_en && 1659 flow_hw_create_vport_action(eth_dev)) { 1660 DRV_LOG(ERR, "port %u failed to create vport action", 1661 eth_dev->data->port_id); 1662 err = EINVAL; 1663 goto error; 1664 } 1665 /* 1666 * If representor matching is disabled, PMD cannot create default flow rules 1667 * to receive traffic for all ports, since implicit source port match is not added. 1668 * Isolated mode is forced. 1669 */ 1670 if (priv->sh->config.dv_esw_en && !priv->sh->config.repr_matching) { 1671 err = mlx5_flow_isolate(eth_dev, 1, NULL); 1672 if (err < 0) { 1673 err = -err; 1674 goto error; 1675 } 1676 DRV_LOG(WARNING, "port %u ingress traffic is restricted to defined " 1677 "flow rules (isolated mode) since representor " 1678 "matching is disabled", 1679 eth_dev->data->port_id); 1680 } 1681 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1682 return eth_dev; 1683 #else 1684 DRV_LOG(ERR, "DV support is missing for HWS."); 1685 goto error; 1686 #endif 1687 } 1688 if (!priv->sh->flow_priority_check_flag) { 1689 /* Supported Verbs flow priority number detection. */ 1690 err = mlx5_flow_discover_priorities(eth_dev); 1691 priv->sh->flow_max_priority = err; 1692 priv->sh->flow_priority_check_flag = 1; 1693 } else { 1694 err = priv->sh->flow_max_priority; 1695 } 1696 if (err < 0) { 1697 err = -err; 1698 goto error; 1699 } 1700 /* Query availability of metadata reg_c's. */ 1701 if (!priv->sh->metadata_regc_check_flag) { 1702 err = mlx5_flow_discover_mreg_c(eth_dev); 1703 if (err < 0) { 1704 err = -err; 1705 goto error; 1706 } 1707 } 1708 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1709 DRV_LOG(DEBUG, 1710 "port %u extensive metadata register is not supported", 1711 eth_dev->data->port_id); 1712 if (sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1713 DRV_LOG(ERR, "metadata mode %u is not supported " 1714 "(no metadata registers available)", 1715 sh->config.dv_xmeta_en); 1716 err = ENOTSUP; 1717 goto error; 1718 } 1719 } 1720 if (sh->config.dv_flow_en && 1721 sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1722 mlx5_flow_ext_mreg_supported(eth_dev) && 1723 priv->sh->dv_regc0_mask) { 1724 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1725 MLX5_FLOW_MREG_HTABLE_SZ, 1726 false, true, eth_dev, 1727 flow_dv_mreg_create_cb, 1728 flow_dv_mreg_match_cb, 1729 flow_dv_mreg_remove_cb, 1730 flow_dv_mreg_clone_cb, 1731 flow_dv_mreg_clone_free_cb); 1732 if (!priv->mreg_cp_tbl) { 1733 err = ENOMEM; 1734 goto error; 1735 } 1736 } 1737 rte_spinlock_init(&priv->shared_act_sl); 1738 mlx5_flow_counter_mode_config(eth_dev); 1739 mlx5_flow_drop_action_config(eth_dev); 1740 if (sh->config.dv_flow_en) 1741 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1742 return eth_dev; 1743 error: 1744 if (priv) { 1745 priv->sh->port[priv->dev_port - 1].nl_ih_port_id = 1746 RTE_MAX_ETHPORTS; 1747 rte_io_wmb(); 1748 #ifdef HAVE_MLX5_HWS_SUPPORT 1749 if (eth_dev && 1750 priv->sh && 1751 priv->sh->config.dv_flow_en == 2 && 1752 priv->sh->config.dv_esw_en) 1753 flow_hw_destroy_vport_action(eth_dev); 1754 #endif 1755 if (priv->mreg_cp_tbl) 1756 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1757 if (priv->sh) 1758 mlx5_os_free_shared_dr(priv); 1759 if (priv->nl_socket_route >= 0) 1760 close(priv->nl_socket_route); 1761 if (priv->vmwa_context) 1762 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1763 if (eth_dev && priv->drop_queue.hrxq) 1764 mlx5_drop_action_destroy(eth_dev); 1765 if (priv->mtr_profile_tbl) 1766 mlx5_l3t_destroy(priv->mtr_profile_tbl); 1767 if (own_domain_id) 1768 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1769 if (priv->hrxqs) 1770 mlx5_list_destroy(priv->hrxqs); 1771 if (eth_dev && priv->flex_item_map) 1772 mlx5_flex_item_port_cleanup(eth_dev); 1773 mlx5_free(priv->ext_rxqs); 1774 mlx5_free(priv->ext_txqs); 1775 mlx5_free(priv); 1776 if (eth_dev != NULL) 1777 eth_dev->data->dev_private = NULL; 1778 } 1779 if (eth_dev != NULL) { 1780 /* mac_addrs must not be freed alone because part of 1781 * dev_private 1782 **/ 1783 eth_dev->data->mac_addrs = NULL; 1784 rte_eth_dev_release_port(eth_dev); 1785 } 1786 if (sh) 1787 mlx5_free_shared_dev_ctx(sh); 1788 if (nl_rdma >= 0) 1789 close(nl_rdma); 1790 MLX5_ASSERT(err > 0); 1791 rte_errno = err; 1792 return NULL; 1793 } 1794 1795 /** 1796 * Comparison callback to sort device data. 1797 * 1798 * This is meant to be used with qsort(). 1799 * 1800 * @param a[in] 1801 * Pointer to pointer to first data object. 1802 * @param b[in] 1803 * Pointer to pointer to second data object. 1804 * 1805 * @return 1806 * 0 if both objects are equal, less than 0 if the first argument is less 1807 * than the second, greater than 0 otherwise. 1808 */ 1809 static int 1810 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1811 { 1812 const struct mlx5_switch_info *si_a = 1813 &((const struct mlx5_dev_spawn_data *)a)->info; 1814 const struct mlx5_switch_info *si_b = 1815 &((const struct mlx5_dev_spawn_data *)b)->info; 1816 int uplink_a = si_a->name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK; 1817 int uplink_b = si_b->name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK; 1818 int ret; 1819 1820 /* Uplink ports first. */ 1821 ret = uplink_b - uplink_a; 1822 if (ret) 1823 return ret; 1824 /* Then master devices. */ 1825 ret = si_b->master - si_a->master; 1826 if (ret) 1827 return ret; 1828 /* Then representor devices. */ 1829 ret = si_b->representor - si_a->representor; 1830 if (ret) 1831 return ret; 1832 /* Unidentified devices come last in no specific order. */ 1833 if (!si_a->representor) 1834 return 0; 1835 /* Order representors by name. */ 1836 return si_a->port_name - si_b->port_name; 1837 } 1838 1839 /** 1840 * Match PCI information for possible slaves of bonding device. 1841 * 1842 * @param[in] ibdev_name 1843 * Name of Infiniband device. 1844 * @param[in] pci_dev 1845 * Pointer to primary PCI address structure to match. 1846 * @param[in] nl_rdma 1847 * Netlink RDMA group socket handle. 1848 * @param[in] owner 1849 * Representor owner PF index. 1850 * @param[out] bond_info 1851 * Pointer to bonding information. 1852 * 1853 * @return 1854 * negative value if no bonding device found, otherwise 1855 * positive index of slave PF in bonding. 1856 */ 1857 static int 1858 mlx5_device_bond_pci_match(const char *ibdev_name, 1859 const struct rte_pci_addr *pci_dev, 1860 int nl_rdma, uint16_t owner, 1861 struct mlx5_bond_info *bond_info) 1862 { 1863 char ifname[IF_NAMESIZE + 1]; 1864 unsigned int ifindex; 1865 unsigned int np, i; 1866 FILE *bond_file = NULL, *file; 1867 int pf = -1; 1868 int ret; 1869 uint8_t cur_guid[32] = {0}; 1870 uint8_t guid[32] = {0}; 1871 1872 /* 1873 * Try to get master device name. If something goes wrong suppose 1874 * the lack of kernel support and no bonding devices. 1875 */ 1876 memset(bond_info, 0, sizeof(*bond_info)); 1877 if (nl_rdma < 0) 1878 return -1; 1879 if (!strstr(ibdev_name, "bond")) 1880 return -1; 1881 np = mlx5_nl_portnum(nl_rdma, ibdev_name); 1882 if (!np) 1883 return -1; 1884 if (mlx5_get_device_guid(pci_dev, cur_guid, sizeof(cur_guid)) < 0) 1885 return -1; 1886 /* 1887 * The master device might not be on the predefined port(not on port 1888 * index 1, it is not guaranteed), we have to scan all Infiniband 1889 * device ports and find master. 1890 */ 1891 for (i = 1; i <= np; ++i) { 1892 /* Check whether Infiniband port is populated. */ 1893 ifindex = mlx5_nl_ifindex(nl_rdma, ibdev_name, i); 1894 if (!ifindex) 1895 continue; 1896 if (!if_indextoname(ifindex, ifname)) 1897 continue; 1898 /* Try to read bonding slave names from sysfs. */ 1899 MKSTR(slaves, 1900 "/sys/class/net/%s/master/bonding/slaves", ifname); 1901 bond_file = fopen(slaves, "r"); 1902 if (bond_file) 1903 break; 1904 } 1905 if (!bond_file) 1906 return -1; 1907 /* Use safe format to check maximal buffer length. */ 1908 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1909 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1910 char tmp_str[IF_NAMESIZE + 32]; 1911 struct rte_pci_addr pci_addr; 1912 struct mlx5_switch_info info; 1913 int ret; 1914 1915 /* Process slave interface names in the loop. */ 1916 snprintf(tmp_str, sizeof(tmp_str), 1917 "/sys/class/net/%s", ifname); 1918 if (mlx5_get_pci_addr(tmp_str, &pci_addr)) { 1919 DRV_LOG(WARNING, 1920 "Cannot get PCI address for netdev \"%s\".", 1921 ifname); 1922 continue; 1923 } 1924 /* Slave interface PCI address match found. */ 1925 snprintf(tmp_str, sizeof(tmp_str), 1926 "/sys/class/net/%s/phys_port_name", ifname); 1927 file = fopen(tmp_str, "rb"); 1928 if (!file) 1929 break; 1930 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1931 if (fscanf(file, "%32s", tmp_str) == 1) 1932 mlx5_translate_port_name(tmp_str, &info); 1933 fclose(file); 1934 /* Only process PF ports. */ 1935 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 1936 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1937 continue; 1938 /* Check max bonding member. */ 1939 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 1940 DRV_LOG(WARNING, "bonding index out of range, " 1941 "please increase MLX5_BOND_MAX_PORTS: %s", 1942 tmp_str); 1943 break; 1944 } 1945 /* Get ifindex. */ 1946 snprintf(tmp_str, sizeof(tmp_str), 1947 "/sys/class/net/%s/ifindex", ifname); 1948 file = fopen(tmp_str, "rb"); 1949 if (!file) 1950 break; 1951 ret = fscanf(file, "%u", &ifindex); 1952 fclose(file); 1953 if (ret != 1) 1954 break; 1955 /* Save bonding info. */ 1956 strncpy(bond_info->ports[info.port_name].ifname, ifname, 1957 sizeof(bond_info->ports[0].ifname)); 1958 bond_info->ports[info.port_name].pci_addr = pci_addr; 1959 bond_info->ports[info.port_name].ifindex = ifindex; 1960 bond_info->n_port++; 1961 /* 1962 * Under socket direct mode, bonding will use 1963 * system_image_guid as identification. 1964 * After OFED 5.4, guid is readable (ret >= 0) under sysfs. 1965 * All bonding members should have the same guid even if driver 1966 * is using PCIe BDF. 1967 */ 1968 ret = mlx5_get_device_guid(&pci_addr, guid, sizeof(guid)); 1969 if (ret < 0) 1970 break; 1971 else if (ret > 0) { 1972 if (!memcmp(guid, cur_guid, sizeof(guid)) && 1973 owner == info.port_name && 1974 (owner != 0 || (owner == 0 && 1975 !rte_pci_addr_cmp(pci_dev, &pci_addr)))) 1976 pf = info.port_name; 1977 } else if (pci_dev->domain == pci_addr.domain && 1978 pci_dev->bus == pci_addr.bus && 1979 pci_dev->devid == pci_addr.devid && 1980 ((pci_dev->function == 0 && 1981 pci_dev->function + owner == pci_addr.function) || 1982 (pci_dev->function == owner && 1983 pci_addr.function == owner))) 1984 pf = info.port_name; 1985 } 1986 if (pf >= 0) { 1987 /* Get bond interface info */ 1988 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 1989 bond_info->ifname); 1990 if (ret) 1991 DRV_LOG(ERR, "unable to get bond info: %s", 1992 strerror(rte_errno)); 1993 else 1994 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 1995 ifindex, bond_info->ifindex, bond_info->ifname); 1996 } 1997 if (owner == 0 && pf != 0) { 1998 DRV_LOG(INFO, "PCIe instance " PCI_PRI_FMT " isn't bonding owner", 1999 pci_dev->domain, pci_dev->bus, pci_dev->devid, 2000 pci_dev->function); 2001 } 2002 return pf; 2003 } 2004 2005 static int 2006 mlx5_nl_esw_multiport_get(struct rte_pci_addr *pci_addr, int *enabled) 2007 { 2008 char pci_addr_str[PCI_PRI_STR_SIZE] = { 0 }; 2009 int nlsk_fd; 2010 int devlink_id; 2011 int ret; 2012 2013 /* Provide correct value to have defined enabled state in case of an error. */ 2014 *enabled = 0; 2015 rte_pci_device_name(pci_addr, pci_addr_str, sizeof(pci_addr_str)); 2016 nlsk_fd = mlx5_nl_init(NETLINK_GENERIC, 0); 2017 if (nlsk_fd < 0) 2018 return nlsk_fd; 2019 devlink_id = mlx5_nl_devlink_family_id_get(nlsk_fd); 2020 if (devlink_id < 0) { 2021 ret = devlink_id; 2022 DRV_LOG(DEBUG, "Unable to get devlink family id for Multiport E-Switch checks " 2023 "by netlink, for PCI device %s", pci_addr_str); 2024 goto close_nlsk_fd; 2025 } 2026 ret = mlx5_nl_devlink_esw_multiport_get(nlsk_fd, devlink_id, pci_addr_str, enabled); 2027 if (ret < 0) 2028 DRV_LOG(DEBUG, "Unable to get Multiport E-Switch state by Netlink."); 2029 close_nlsk_fd: 2030 close(nlsk_fd); 2031 return ret; 2032 } 2033 2034 #define SYSFS_MPESW_PARAM_MAX_LEN 16 2035 2036 static int 2037 mlx5_sysfs_esw_multiport_get(struct ibv_device *ibv, struct rte_pci_addr *pci_addr, int *enabled) 2038 { 2039 int nl_rdma; 2040 unsigned int n_ports; 2041 unsigned int i; 2042 int ret; 2043 2044 /* Provide correct value to have defined enabled state in case of an error. */ 2045 *enabled = 0; 2046 nl_rdma = mlx5_nl_init(NETLINK_RDMA, 0); 2047 if (nl_rdma < 0) 2048 return nl_rdma; 2049 n_ports = mlx5_nl_portnum(nl_rdma, ibv->name); 2050 if (!n_ports) { 2051 ret = -rte_errno; 2052 goto close_nl_rdma; 2053 } 2054 for (i = 1; i <= n_ports; ++i) { 2055 unsigned int ifindex; 2056 char ifname[IF_NAMESIZE + 1]; 2057 struct rte_pci_addr if_pci_addr; 2058 char mpesw[SYSFS_MPESW_PARAM_MAX_LEN + 1]; 2059 FILE *sysfs; 2060 int n; 2061 2062 ifindex = mlx5_nl_ifindex(nl_rdma, ibv->name, i); 2063 if (!ifindex) 2064 continue; 2065 if (!if_indextoname(ifindex, ifname)) 2066 continue; 2067 MKSTR(sysfs_if_path, "/sys/class/net/%s", ifname); 2068 if (mlx5_get_pci_addr(sysfs_if_path, &if_pci_addr)) 2069 continue; 2070 if (pci_addr->domain != if_pci_addr.domain || 2071 pci_addr->bus != if_pci_addr.bus || 2072 pci_addr->devid != if_pci_addr.devid || 2073 pci_addr->function != if_pci_addr.function) 2074 continue; 2075 MKSTR(sysfs_mpesw_path, 2076 "/sys/class/net/%s/compat/devlink/lag_port_select_mode", ifname); 2077 sysfs = fopen(sysfs_mpesw_path, "r"); 2078 if (!sysfs) 2079 continue; 2080 n = fscanf(sysfs, "%" RTE_STR(SYSFS_MPESW_PARAM_MAX_LEN) "s", mpesw); 2081 fclose(sysfs); 2082 if (n != 1) 2083 continue; 2084 ret = 0; 2085 if (strcmp(mpesw, "multiport_esw") == 0) { 2086 *enabled = 1; 2087 break; 2088 } 2089 *enabled = 0; 2090 break; 2091 } 2092 if (i > n_ports) { 2093 DRV_LOG(DEBUG, "Unable to get Multiport E-Switch state by sysfs."); 2094 rte_errno = ENOENT; 2095 ret = -rte_errno; 2096 } 2097 2098 close_nl_rdma: 2099 close(nl_rdma); 2100 return ret; 2101 } 2102 2103 static int 2104 mlx5_is_mpesw_enabled(struct ibv_device *ibv, struct rte_pci_addr *ibv_pci_addr, int *enabled) 2105 { 2106 /* 2107 * Try getting Multiport E-Switch state through netlink interface 2108 * If unable, try sysfs interface. If that is unable as well, 2109 * assume that Multiport E-Switch is disabled and return an error. 2110 */ 2111 if (mlx5_nl_esw_multiport_get(ibv_pci_addr, enabled) >= 0 || 2112 mlx5_sysfs_esw_multiport_get(ibv, ibv_pci_addr, enabled) >= 0) 2113 return 0; 2114 DRV_LOG(DEBUG, "Unable to check MPESW state for IB device %s " 2115 "(PCI: " PCI_PRI_FMT ")", 2116 ibv->name, 2117 ibv_pci_addr->domain, ibv_pci_addr->bus, 2118 ibv_pci_addr->devid, ibv_pci_addr->function); 2119 *enabled = 0; 2120 return -rte_errno; 2121 } 2122 2123 static int 2124 mlx5_device_mpesw_pci_match(struct ibv_device *ibv, 2125 const struct rte_pci_addr *owner_pci, 2126 int nl_rdma) 2127 { 2128 struct rte_pci_addr ibdev_pci_addr = { 0 }; 2129 char ifname[IF_NAMESIZE + 1] = { 0 }; 2130 unsigned int ifindex; 2131 unsigned int np; 2132 unsigned int i; 2133 int enabled = 0; 2134 int ret; 2135 2136 /* Check if IB device's PCI address matches the probed PCI address. */ 2137 if (mlx5_get_pci_addr(ibv->ibdev_path, &ibdev_pci_addr)) { 2138 DRV_LOG(DEBUG, "Skipping MPESW check for IB device %s since " 2139 "there is no underlying PCI device", ibv->name); 2140 rte_errno = ENOENT; 2141 return -rte_errno; 2142 } 2143 if (ibdev_pci_addr.domain != owner_pci->domain || 2144 ibdev_pci_addr.bus != owner_pci->bus || 2145 ibdev_pci_addr.devid != owner_pci->devid || 2146 ibdev_pci_addr.function != owner_pci->function) { 2147 return -1; 2148 } 2149 /* Check if IB device has MPESW enabled. */ 2150 if (mlx5_is_mpesw_enabled(ibv, &ibdev_pci_addr, &enabled)) 2151 return -1; 2152 if (!enabled) 2153 return -1; 2154 /* Iterate through IB ports to find MPESW master uplink port. */ 2155 if (nl_rdma < 0) 2156 return -1; 2157 np = mlx5_nl_portnum(nl_rdma, ibv->name); 2158 if (!np) 2159 return -1; 2160 for (i = 1; i <= np; ++i) { 2161 struct rte_pci_addr pci_addr; 2162 FILE *file; 2163 char port_name[IF_NAMESIZE + 1]; 2164 struct mlx5_switch_info info; 2165 2166 /* Check whether IB port has a corresponding netdev. */ 2167 ifindex = mlx5_nl_ifindex(nl_rdma, ibv->name, i); 2168 if (!ifindex) 2169 continue; 2170 if (!if_indextoname(ifindex, ifname)) 2171 continue; 2172 /* Read port name and determine its type. */ 2173 MKSTR(ifphysportname, "/sys/class/net/%s/phys_port_name", ifname); 2174 file = fopen(ifphysportname, "rb"); 2175 if (!file) 2176 continue; 2177 ret = fscanf(file, "%16s", port_name); 2178 fclose(file); 2179 if (ret != 1) 2180 continue; 2181 memset(&info, 0, sizeof(info)); 2182 mlx5_translate_port_name(port_name, &info); 2183 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 2184 continue; 2185 /* Fetch PCI address of the device to which the netdev is bound. */ 2186 MKSTR(ifpath, "/sys/class/net/%s", ifname); 2187 if (mlx5_get_pci_addr(ifpath, &pci_addr)) 2188 continue; 2189 if (pci_addr.domain == ibdev_pci_addr.domain && 2190 pci_addr.bus == ibdev_pci_addr.bus && 2191 pci_addr.devid == ibdev_pci_addr.devid && 2192 pci_addr.function == ibdev_pci_addr.function) { 2193 MLX5_ASSERT(info.port_name >= 0); 2194 return info.port_name; 2195 } 2196 } 2197 /* No matching MPESW uplink port was found. */ 2198 return -1; 2199 } 2200 2201 /** 2202 * Register a PCI device within bonding. 2203 * 2204 * This function spawns Ethernet devices out of a given PCI device and 2205 * bonding owner PF index. 2206 * 2207 * @param[in] cdev 2208 * Pointer to common mlx5 device structure. 2209 * @param[in] req_eth_da 2210 * Requested ethdev device argument. 2211 * @param[in] owner_id 2212 * Requested owner PF port ID within bonding device, default to 0. 2213 * @param[in, out] mkvlist 2214 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 2215 * 2216 * @return 2217 * 0 on success, a negative errno value otherwise and rte_errno is set. 2218 */ 2219 static int 2220 mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, 2221 struct rte_eth_devargs *req_eth_da, 2222 uint16_t owner_id, struct mlx5_kvargs_ctrl *mkvlist) 2223 { 2224 struct ibv_device **ibv_list; 2225 /* 2226 * Number of found IB Devices matching with requested PCI BDF. 2227 * nd != 1 means there are multiple IB devices over the same 2228 * PCI device and we have representors and master. 2229 */ 2230 unsigned int nd = 0; 2231 /* 2232 * Number of found IB device Ports. nd = 1 and np = 1..n means 2233 * we have the single multiport IB device, and there may be 2234 * representors attached to some of found ports. 2235 */ 2236 unsigned int np = 0; 2237 /* 2238 * Number of DPDK ethernet devices to Spawn - either over 2239 * multiple IB devices or multiple ports of single IB device. 2240 * Actually this is the number of iterations to spawn. 2241 */ 2242 unsigned int ns = 0; 2243 /* 2244 * Bonding device 2245 * < 0 - no bonding device (single one) 2246 * >= 0 - bonding device (value is slave PF index) 2247 */ 2248 int bd = -1; 2249 /* 2250 * Multiport E-Switch (MPESW) device: 2251 * < 0 - no MPESW device or could not determine if it is MPESW device, 2252 * >= 0 - MPESW device. Value is the port index of the MPESW owner. 2253 */ 2254 int mpesw = MLX5_MPESW_PORT_INVALID; 2255 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 2256 struct mlx5_dev_spawn_data *list = NULL; 2257 struct rte_eth_devargs eth_da = *req_eth_da; 2258 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 2259 struct mlx5_bond_info bond_info; 2260 int ret = -1; 2261 2262 errno = 0; 2263 ibv_list = mlx5_glue->get_device_list(&ret); 2264 if (!ibv_list) { 2265 rte_errno = errno ? errno : ENOSYS; 2266 DRV_LOG(ERR, "Cannot list devices, is ib_uverbs loaded?"); 2267 return -rte_errno; 2268 } 2269 /* 2270 * First scan the list of all Infiniband devices to find 2271 * matching ones, gathering into the list. 2272 */ 2273 struct ibv_device *ibv_match[ret + 1]; 2274 int nl_route = mlx5_nl_init(NETLINK_ROUTE, 0); 2275 int nl_rdma = mlx5_nl_init(NETLINK_RDMA, 0); 2276 unsigned int i; 2277 2278 while (ret-- > 0) { 2279 struct rte_pci_addr pci_addr; 2280 2281 DRV_LOG(DEBUG, "Checking device \"%s\"", ibv_list[ret]->name); 2282 bd = mlx5_device_bond_pci_match(ibv_list[ret]->name, &owner_pci, 2283 nl_rdma, owner_id, &bond_info); 2284 if (bd >= 0) { 2285 /* 2286 * Bonding device detected. Only one match is allowed, 2287 * the bonding is supported over multi-port IB device, 2288 * there should be no matches on representor PCI 2289 * functions or non VF LAG bonding devices with 2290 * specified address. 2291 */ 2292 if (nd) { 2293 DRV_LOG(ERR, 2294 "multiple PCI match on bonding device" 2295 "\"%s\" found", ibv_list[ret]->name); 2296 rte_errno = ENOENT; 2297 ret = -rte_errno; 2298 goto exit; 2299 } 2300 /* Amend owner pci address if owner PF ID specified. */ 2301 if (eth_da.nb_representor_ports) 2302 owner_pci.function += owner_id; 2303 DRV_LOG(INFO, 2304 "PCI information matches for slave %d bonding device \"%s\"", 2305 bd, ibv_list[ret]->name); 2306 ibv_match[nd++] = ibv_list[ret]; 2307 break; 2308 } 2309 mpesw = mlx5_device_mpesw_pci_match(ibv_list[ret], &owner_pci, nl_rdma); 2310 if (mpesw >= 0) { 2311 /* 2312 * MPESW device detected. Only one matching IB device is allowed, 2313 * so if any matches were found previously, fail gracefully. 2314 */ 2315 if (nd) { 2316 DRV_LOG(ERR, 2317 "PCI information matches MPESW device \"%s\", " 2318 "but multiple matching PCI devices were found. " 2319 "Probing failed.", 2320 ibv_list[ret]->name); 2321 rte_errno = ENOENT; 2322 ret = -rte_errno; 2323 goto exit; 2324 } 2325 DRV_LOG(INFO, 2326 "PCI information matches MPESW device \"%s\"", 2327 ibv_list[ret]->name); 2328 ibv_match[nd++] = ibv_list[ret]; 2329 break; 2330 } 2331 /* Bonding or MPESW device was not found. */ 2332 if (mlx5_get_pci_addr(ibv_list[ret]->ibdev_path, 2333 &pci_addr)) 2334 continue; 2335 if (rte_pci_addr_cmp(&owner_pci, &pci_addr) != 0) 2336 continue; 2337 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2338 ibv_list[ret]->name); 2339 ibv_match[nd++] = ibv_list[ret]; 2340 } 2341 ibv_match[nd] = NULL; 2342 if (!nd) { 2343 /* No device matches, just complain and bail out. */ 2344 DRV_LOG(WARNING, 2345 "PF %u doesn't have Verbs device matches PCI device " PCI_PRI_FMT "," 2346 " are kernel drivers loaded?", 2347 owner_id, owner_pci.domain, owner_pci.bus, 2348 owner_pci.devid, owner_pci.function); 2349 rte_errno = ENOENT; 2350 ret = -rte_errno; 2351 goto exit; 2352 } 2353 if (nd == 1) { 2354 /* 2355 * Found single matching device may have multiple ports. 2356 * Each port may be representor, we have to check the port 2357 * number and check the representors existence. 2358 */ 2359 if (nl_rdma >= 0) 2360 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2361 if (!np) 2362 DRV_LOG(WARNING, 2363 "Cannot get IB device \"%s\" ports number.", 2364 ibv_match[0]->name); 2365 if (bd >= 0 && !np) { 2366 DRV_LOG(ERR, "Cannot get ports for bonding device."); 2367 rte_errno = ENOENT; 2368 ret = -rte_errno; 2369 goto exit; 2370 } 2371 if (mpesw >= 0 && !np) { 2372 DRV_LOG(ERR, "Cannot get ports for MPESW device."); 2373 rte_errno = ENOENT; 2374 ret = -rte_errno; 2375 goto exit; 2376 } 2377 } 2378 /* Now we can determine the maximal amount of devices to be spawned. */ 2379 list = mlx5_malloc(MLX5_MEM_ZERO, 2380 sizeof(struct mlx5_dev_spawn_data) * (np ? np : nd), 2381 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2382 if (!list) { 2383 DRV_LOG(ERR, "Spawn data array allocation failure."); 2384 rte_errno = ENOMEM; 2385 ret = -rte_errno; 2386 goto exit; 2387 } 2388 if (bd >= 0 || mpesw >= 0 || np > 1) { 2389 /* 2390 * Single IB device with multiple ports found, 2391 * it may be E-Switch master device and representors. 2392 * We have to perform identification through the ports. 2393 */ 2394 MLX5_ASSERT(nl_rdma >= 0); 2395 MLX5_ASSERT(ns == 0); 2396 MLX5_ASSERT(nd == 1); 2397 MLX5_ASSERT(np); 2398 for (i = 1; i <= np; ++i) { 2399 list[ns].bond_info = &bond_info; 2400 list[ns].max_port = np; 2401 list[ns].phys_port = i; 2402 list[ns].phys_dev_name = ibv_match[0]->name; 2403 list[ns].eth_dev = NULL; 2404 list[ns].pci_dev = pci_dev; 2405 list[ns].cdev = cdev; 2406 list[ns].pf_bond = bd; 2407 list[ns].mpesw_port = MLX5_MPESW_PORT_INVALID; 2408 list[ns].ifindex = mlx5_nl_ifindex(nl_rdma, 2409 ibv_match[0]->name, 2410 i); 2411 if (!list[ns].ifindex) { 2412 /* 2413 * No network interface index found for the 2414 * specified port, it means there is no 2415 * representor on this port. It's OK, 2416 * there can be disabled ports, for example 2417 * if sriov_numvfs < sriov_totalvfs. 2418 */ 2419 continue; 2420 } 2421 ret = -1; 2422 if (nl_route >= 0) 2423 ret = mlx5_nl_switch_info(nl_route, 2424 list[ns].ifindex, 2425 &list[ns].info); 2426 if (ret || (!list[ns].info.representor && 2427 !list[ns].info.master)) { 2428 /* 2429 * We failed to recognize representors with 2430 * Netlink, let's try to perform the task 2431 * with sysfs. 2432 */ 2433 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2434 &list[ns].info); 2435 } 2436 if (!ret && bd >= 0) { 2437 switch (list[ns].info.name_type) { 2438 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2439 if (np == 1) { 2440 /* 2441 * Force standalone bonding 2442 * device for ROCE LAG 2443 * configurations. 2444 */ 2445 list[ns].info.master = 0; 2446 list[ns].info.representor = 0; 2447 } 2448 if (list[ns].info.port_name == bd) 2449 ns++; 2450 break; 2451 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2452 /* Fallthrough */ 2453 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2454 /* Fallthrough */ 2455 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2456 if (list[ns].info.pf_num == bd) 2457 ns++; 2458 break; 2459 default: 2460 break; 2461 } 2462 continue; 2463 } 2464 if (!ret && mpesw >= 0) { 2465 switch (list[ns].info.name_type) { 2466 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2467 /* Owner port is treated as master port. */ 2468 if (list[ns].info.port_name == mpesw) { 2469 list[ns].info.master = 1; 2470 list[ns].info.representor = 0; 2471 } else { 2472 list[ns].info.master = 0; 2473 list[ns].info.representor = 1; 2474 } 2475 /* 2476 * Ports of this type have uplink port index 2477 * encoded in the name. This index is also a PF index. 2478 */ 2479 list[ns].info.pf_num = list[ns].info.port_name; 2480 list[ns].mpesw_port = list[ns].info.port_name; 2481 list[ns].info.mpesw_owner = mpesw; 2482 ns++; 2483 break; 2484 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2485 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2486 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2487 /* Only spawn representors related to the probed PF. */ 2488 if (list[ns].info.pf_num == owner_id) { 2489 /* 2490 * Ports of this type have PF index encoded in name, 2491 * which translate to the related uplink port index. 2492 */ 2493 list[ns].mpesw_port = list[ns].info.pf_num; 2494 /* MPESW owner is also saved but not used now. */ 2495 list[ns].info.mpesw_owner = mpesw; 2496 ns++; 2497 } 2498 break; 2499 default: 2500 break; 2501 } 2502 continue; 2503 } 2504 if (!ret && (list[ns].info.representor ^ 2505 list[ns].info.master)) 2506 ns++; 2507 } 2508 if (!ns) { 2509 DRV_LOG(ERR, 2510 "Unable to recognize master/representors on the IB device with multiple ports."); 2511 rte_errno = ENOENT; 2512 ret = -rte_errno; 2513 goto exit; 2514 } 2515 } else { 2516 /* 2517 * The existence of several matching entries (nd > 1) means 2518 * port representors have been instantiated. No existing Verbs 2519 * call nor sysfs entries can tell them apart, this can only 2520 * be done through Netlink calls assuming kernel drivers are 2521 * recent enough to support them. 2522 * 2523 * In the event of identification failure through Netlink, 2524 * try again through sysfs, then: 2525 * 2526 * 1. A single IB device matches (nd == 1) with single 2527 * port (np=0/1) and is not a representor, assume 2528 * no switch support. 2529 * 2530 * 2. Otherwise no safe assumptions can be made; 2531 * complain louder and bail out. 2532 */ 2533 for (i = 0; i != nd; ++i) { 2534 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2535 list[ns].bond_info = NULL; 2536 list[ns].max_port = 1; 2537 list[ns].phys_port = 1; 2538 list[ns].phys_dev_name = ibv_match[i]->name; 2539 list[ns].eth_dev = NULL; 2540 list[ns].pci_dev = pci_dev; 2541 list[ns].cdev = cdev; 2542 list[ns].pf_bond = -1; 2543 list[ns].mpesw_port = MLX5_MPESW_PORT_INVALID; 2544 list[ns].ifindex = 0; 2545 if (nl_rdma >= 0) 2546 list[ns].ifindex = mlx5_nl_ifindex 2547 (nl_rdma, 2548 ibv_match[i]->name, 2549 1); 2550 if (!list[ns].ifindex) { 2551 char ifname[IF_NAMESIZE]; 2552 2553 /* 2554 * Netlink failed, it may happen with old 2555 * ib_core kernel driver (before 4.16). 2556 * We can assume there is old driver because 2557 * here we are processing single ports IB 2558 * devices. Let's try sysfs to retrieve 2559 * the ifindex. The method works for 2560 * master device only. 2561 */ 2562 if (nd > 1) { 2563 /* 2564 * Multiple devices found, assume 2565 * representors, can not distinguish 2566 * master/representor and retrieve 2567 * ifindex via sysfs. 2568 */ 2569 continue; 2570 } 2571 ret = mlx5_get_ifname_sysfs 2572 (ibv_match[i]->ibdev_path, ifname); 2573 if (!ret) 2574 list[ns].ifindex = 2575 if_nametoindex(ifname); 2576 if (!list[ns].ifindex) { 2577 /* 2578 * No network interface index found 2579 * for the specified device, it means 2580 * there it is neither representor 2581 * nor master. 2582 */ 2583 continue; 2584 } 2585 } 2586 ret = -1; 2587 if (nl_route >= 0) 2588 ret = mlx5_nl_switch_info(nl_route, 2589 list[ns].ifindex, 2590 &list[ns].info); 2591 if (ret || (!list[ns].info.representor && 2592 !list[ns].info.master)) { 2593 /* 2594 * We failed to recognize representors with 2595 * Netlink, let's try to perform the task 2596 * with sysfs. 2597 */ 2598 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2599 &list[ns].info); 2600 } 2601 if (!ret && (list[ns].info.representor ^ 2602 list[ns].info.master)) { 2603 ns++; 2604 } else if ((nd == 1) && 2605 !list[ns].info.representor && 2606 !list[ns].info.master) { 2607 /* 2608 * Single IB device with one physical port and 2609 * attached network device. 2610 * May be SRIOV is not enabled or there is no 2611 * representors. 2612 */ 2613 DRV_LOG(INFO, "No E-Switch support detected."); 2614 ns++; 2615 break; 2616 } 2617 } 2618 if (!ns) { 2619 DRV_LOG(ERR, 2620 "Unable to recognize master/representors on the multiple IB devices."); 2621 rte_errno = ENOENT; 2622 ret = -rte_errno; 2623 goto exit; 2624 } 2625 /* 2626 * New kernels may add the switch_id attribute for the case 2627 * there is no E-Switch and we wrongly recognized the only 2628 * device as master. Override this if there is the single 2629 * device with single port and new device name format present. 2630 */ 2631 if (nd == 1 && 2632 list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) { 2633 list[0].info.master = 0; 2634 list[0].info.representor = 0; 2635 } 2636 } 2637 MLX5_ASSERT(ns); 2638 /* 2639 * Sort list to probe devices in natural order for users convenience 2640 * (i.e. master first, then representors from lowest to highest ID). 2641 */ 2642 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2643 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2644 /* Set devargs default values. */ 2645 if (eth_da.nb_mh_controllers == 0) { 2646 eth_da.nb_mh_controllers = 1; 2647 eth_da.mh_controllers[0] = 0; 2648 } 2649 if (eth_da.nb_ports == 0 && ns > 0) { 2650 if (list[0].pf_bond >= 0 && list[0].info.representor) 2651 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2652 pci_dev->device.devargs->args); 2653 eth_da.nb_ports = 1; 2654 eth_da.ports[0] = list[0].info.pf_num; 2655 } 2656 if (eth_da.nb_representor_ports == 0) { 2657 eth_da.nb_representor_ports = 1; 2658 eth_da.representor_ports[0] = 0; 2659 } 2660 } 2661 for (i = 0; i != ns; ++i) { 2662 uint32_t restore; 2663 2664 list[i].eth_dev = mlx5_dev_spawn(cdev->dev, &list[i], ð_da, 2665 mkvlist); 2666 if (!list[i].eth_dev) { 2667 if (rte_errno != EBUSY && rte_errno != EEXIST) 2668 break; 2669 /* Device is disabled or already spawned. Ignore it. */ 2670 continue; 2671 } 2672 restore = list[i].eth_dev->data->dev_flags; 2673 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2674 /** 2675 * Each representor has a dedicated interrupts vector. 2676 * rte_eth_copy_pci_info() assigns PF interrupts handle to 2677 * representor eth_dev object because representor and PF 2678 * share the same PCI address. 2679 * Override representor device with a dedicated 2680 * interrupts handle here. 2681 * Representor interrupts handle is released in mlx5_dev_stop(). 2682 */ 2683 if (list[i].info.representor) { 2684 struct rte_intr_handle *intr_handle = 2685 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2686 if (intr_handle == NULL) { 2687 DRV_LOG(ERR, 2688 "port %u failed to allocate memory for interrupt handler " 2689 "Rx interrupts will not be supported", 2690 i); 2691 rte_errno = ENOMEM; 2692 ret = -rte_errno; 2693 goto exit; 2694 } 2695 list[i].eth_dev->intr_handle = intr_handle; 2696 } 2697 /* Restore non-PCI flags cleared by the above call. */ 2698 list[i].eth_dev->data->dev_flags |= restore; 2699 rte_eth_dev_probing_finish(list[i].eth_dev); 2700 } 2701 if (i != ns) { 2702 DRV_LOG(ERR, 2703 "probe of PCI device " PCI_PRI_FMT " aborted after" 2704 " encountering an error: %s", 2705 owner_pci.domain, owner_pci.bus, 2706 owner_pci.devid, owner_pci.function, 2707 strerror(rte_errno)); 2708 ret = -rte_errno; 2709 /* Roll back. */ 2710 while (i--) { 2711 if (!list[i].eth_dev) 2712 continue; 2713 mlx5_dev_close(list[i].eth_dev); 2714 /* mac_addrs must not be freed because in dev_private */ 2715 list[i].eth_dev->data->mac_addrs = NULL; 2716 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2717 } 2718 /* Restore original error. */ 2719 rte_errno = -ret; 2720 } else { 2721 ret = 0; 2722 } 2723 exit: 2724 /* 2725 * Do the routine cleanup: 2726 * - close opened Netlink sockets 2727 * - free allocated spawn data array 2728 * - free the Infiniband device list 2729 */ 2730 if (nl_rdma >= 0) 2731 close(nl_rdma); 2732 if (nl_route >= 0) 2733 close(nl_route); 2734 if (list) 2735 mlx5_free(list); 2736 MLX5_ASSERT(ibv_list); 2737 mlx5_glue->free_device_list(ibv_list); 2738 return ret; 2739 } 2740 2741 static int 2742 mlx5_os_parse_eth_devargs(struct rte_device *dev, 2743 struct rte_eth_devargs *eth_da) 2744 { 2745 int ret = 0; 2746 2747 if (dev->devargs == NULL) 2748 return 0; 2749 memset(eth_da, 0, sizeof(*eth_da)); 2750 /* Parse representor information first from class argument. */ 2751 if (dev->devargs->cls_str) 2752 ret = rte_eth_devargs_parse(dev->devargs->cls_str, eth_da, 1); 2753 if (ret < 0) { 2754 DRV_LOG(ERR, "failed to parse device arguments: %s", 2755 dev->devargs->cls_str); 2756 return -rte_errno; 2757 } 2758 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE && dev->devargs->args) { 2759 /* Parse legacy device argument */ 2760 ret = rte_eth_devargs_parse(dev->devargs->args, eth_da, 1); 2761 if (ret < 0) { 2762 DRV_LOG(ERR, "failed to parse device arguments: %s", 2763 dev->devargs->args); 2764 return -rte_errno; 2765 } 2766 } 2767 return 0; 2768 } 2769 2770 /** 2771 * Callback to register a PCI device. 2772 * 2773 * This function spawns Ethernet devices out of a given PCI device. 2774 * 2775 * @param[in] cdev 2776 * Pointer to common mlx5 device structure. 2777 * @param[in, out] mkvlist 2778 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 2779 * 2780 * @return 2781 * 0 on success, a negative errno value otherwise and rte_errno is set. 2782 */ 2783 static int 2784 mlx5_os_pci_probe(struct mlx5_common_device *cdev, 2785 struct mlx5_kvargs_ctrl *mkvlist) 2786 { 2787 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 2788 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2789 int ret = 0; 2790 uint16_t p; 2791 2792 ret = mlx5_os_parse_eth_devargs(cdev->dev, ð_da); 2793 if (ret != 0) 2794 return ret; 2795 2796 if (eth_da.nb_ports > 0) { 2797 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2798 for (p = 0; p < eth_da.nb_ports; p++) { 2799 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 2800 eth_da.ports[p], mkvlist); 2801 if (ret) { 2802 DRV_LOG(INFO, "Probe of PCI device " PCI_PRI_FMT " " 2803 "aborted due to proding failure of PF %u", 2804 pci_dev->addr.domain, pci_dev->addr.bus, 2805 pci_dev->addr.devid, pci_dev->addr.function, 2806 eth_da.ports[p]); 2807 mlx5_net_remove(cdev); 2808 if (p != 0) 2809 break; 2810 } 2811 } 2812 } else { 2813 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 0, mkvlist); 2814 } 2815 return ret; 2816 } 2817 2818 /* Probe a single SF device on auxiliary bus, no representor support. */ 2819 static int 2820 mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev, 2821 struct mlx5_kvargs_ctrl *mkvlist) 2822 { 2823 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2824 struct mlx5_dev_spawn_data spawn = { 2825 .pf_bond = -1, 2826 .mpesw_port = MLX5_MPESW_PORT_INVALID, 2827 }; 2828 struct rte_device *dev = cdev->dev; 2829 struct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev); 2830 struct rte_eth_dev *eth_dev; 2831 int ret = 0; 2832 2833 /* Parse ethdev devargs. */ 2834 ret = mlx5_os_parse_eth_devargs(dev, ð_da); 2835 if (ret != 0) 2836 return ret; 2837 /* Init spawn data. */ 2838 spawn.max_port = 1; 2839 spawn.phys_port = 1; 2840 spawn.phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx); 2841 ret = mlx5_auxiliary_get_ifindex(dev->name); 2842 if (ret < 0) { 2843 DRV_LOG(ERR, "failed to get ethdev ifindex: %s", dev->name); 2844 return ret; 2845 } 2846 spawn.ifindex = ret; 2847 spawn.cdev = cdev; 2848 /* Spawn device. */ 2849 eth_dev = mlx5_dev_spawn(dev, &spawn, ð_da, mkvlist); 2850 if (eth_dev == NULL) 2851 return -rte_errno; 2852 /* Post create. */ 2853 eth_dev->intr_handle = adev->intr_handle; 2854 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2855 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2856 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV; 2857 eth_dev->data->numa_node = dev->numa_node; 2858 } 2859 rte_eth_dev_probing_finish(eth_dev); 2860 return 0; 2861 } 2862 2863 /** 2864 * Net class driver callback to probe a device. 2865 * 2866 * This function probe PCI bus device(s) or a single SF on auxiliary bus. 2867 * 2868 * @param[in] cdev 2869 * Pointer to the common mlx5 device. 2870 * @param[in, out] mkvlist 2871 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 2872 * 2873 * @return 2874 * 0 on success, a negative errno value otherwise and rte_errno is set. 2875 */ 2876 int 2877 mlx5_os_net_probe(struct mlx5_common_device *cdev, 2878 struct mlx5_kvargs_ctrl *mkvlist) 2879 { 2880 int ret; 2881 2882 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2883 mlx5_pmd_socket_init(); 2884 ret = mlx5_init_once(); 2885 if (ret) { 2886 DRV_LOG(ERR, "Unable to init PMD global data: %s", 2887 strerror(rte_errno)); 2888 return -rte_errno; 2889 } 2890 ret = mlx5_probe_again_args_validate(cdev, mkvlist); 2891 if (ret) { 2892 DRV_LOG(ERR, "Probe again parameters are not compatible : %s", 2893 strerror(rte_errno)); 2894 return -rte_errno; 2895 } 2896 if (mlx5_dev_is_pci(cdev->dev)) 2897 return mlx5_os_pci_probe(cdev, mkvlist); 2898 else 2899 return mlx5_os_auxiliary_probe(cdev, mkvlist); 2900 } 2901 2902 /** 2903 * Cleanup resources when the last device is closed. 2904 */ 2905 void 2906 mlx5_os_net_cleanup(void) 2907 { 2908 mlx5_pmd_socket_uninit(); 2909 } 2910 2911 /** 2912 * Install shared asynchronous device events handler. 2913 * This function is implemented to support event sharing 2914 * between multiple ports of single IB device. 2915 * 2916 * @param sh 2917 * Pointer to mlx5_dev_ctx_shared object. 2918 */ 2919 void 2920 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2921 { 2922 struct ibv_context *ctx = sh->cdev->ctx; 2923 int nlsk_fd; 2924 2925 sh->intr_handle = mlx5_os_interrupt_handler_create 2926 (RTE_INTR_INSTANCE_F_SHARED, true, 2927 ctx->async_fd, mlx5_dev_interrupt_handler, sh); 2928 if (!sh->intr_handle) { 2929 DRV_LOG(ERR, "Failed to allocate intr_handle."); 2930 return; 2931 } 2932 nlsk_fd = mlx5_nl_init(NETLINK_ROUTE, RTMGRP_LINK); 2933 if (nlsk_fd < 0) { 2934 DRV_LOG(ERR, "Failed to create a socket for Netlink events: %s", 2935 rte_strerror(rte_errno)); 2936 return; 2937 } 2938 sh->intr_handle_nl = mlx5_os_interrupt_handler_create 2939 (RTE_INTR_INSTANCE_F_SHARED, true, 2940 nlsk_fd, mlx5_dev_interrupt_handler_nl, sh); 2941 if (sh->intr_handle_nl == NULL) { 2942 DRV_LOG(ERR, "Fail to allocate intr_handle"); 2943 return; 2944 } 2945 if (sh->cdev->config.devx) { 2946 #ifdef HAVE_IBV_DEVX_ASYNC 2947 struct mlx5dv_devx_cmd_comp *devx_comp; 2948 2949 sh->devx_comp = (void *)mlx5_glue->devx_create_cmd_comp(ctx); 2950 devx_comp = sh->devx_comp; 2951 if (!devx_comp) { 2952 DRV_LOG(INFO, "failed to allocate devx_comp."); 2953 return; 2954 } 2955 sh->intr_handle_devx = mlx5_os_interrupt_handler_create 2956 (RTE_INTR_INSTANCE_F_SHARED, true, 2957 devx_comp->fd, 2958 mlx5_dev_interrupt_handler_devx, sh); 2959 if (!sh->intr_handle_devx) { 2960 DRV_LOG(ERR, "Failed to allocate intr_handle."); 2961 return; 2962 } 2963 #endif /* HAVE_IBV_DEVX_ASYNC */ 2964 } 2965 } 2966 2967 /** 2968 * Uninstall shared asynchronous device events handler. 2969 * This function is implemented to support event sharing 2970 * between multiple ports of single IB device. 2971 * 2972 * @param dev 2973 * Pointer to mlx5_dev_ctx_shared object. 2974 */ 2975 void 2976 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2977 { 2978 mlx5_os_interrupt_handler_destroy(sh->intr_handle, 2979 mlx5_dev_interrupt_handler, sh); 2980 mlx5_os_interrupt_handler_destroy(sh->intr_handle_nl, 2981 mlx5_dev_interrupt_handler_nl, sh); 2982 #ifdef HAVE_IBV_DEVX_ASYNC 2983 mlx5_os_interrupt_handler_destroy(sh->intr_handle_devx, 2984 mlx5_dev_interrupt_handler_devx, sh); 2985 if (sh->devx_comp) 2986 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2987 #endif 2988 } 2989 2990 /** 2991 * Read statistics by a named counter. 2992 * 2993 * @param[in] priv 2994 * Pointer to the private device data structure. 2995 * @param[in] ctr_name 2996 * Pointer to the name of the statistic counter to read 2997 * @param[out] stat 2998 * Pointer to read statistic value. 2999 * @return 3000 * 0 on success and stat is valud, 1 if failed to read the value 3001 * rte_errno is set. 3002 * 3003 */ 3004 int 3005 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 3006 uint64_t *stat) 3007 { 3008 int fd; 3009 3010 if (priv->sh) { 3011 if (priv->q_counters != NULL && 3012 strcmp(ctr_name, "out_of_buffer") == 0) { 3013 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 3014 DRV_LOG(WARNING, "Devx out_of_buffer counter is not supported in the secondary process"); 3015 rte_errno = ENOTSUP; 3016 return 1; 3017 } 3018 return mlx5_devx_cmd_queue_counter_query 3019 (priv->q_counters, 0, (uint32_t *)stat); 3020 } 3021 MKSTR(path, "%s/ports/%d/hw_counters/%s", 3022 priv->sh->ibdev_path, 3023 priv->dev_port, 3024 ctr_name); 3025 fd = open(path, O_RDONLY); 3026 /* 3027 * in switchdev the file location is not per port 3028 * but rather in <ibdev_path>/hw_counters/<file_name>. 3029 */ 3030 if (fd == -1) { 3031 MKSTR(path1, "%s/hw_counters/%s", 3032 priv->sh->ibdev_path, 3033 ctr_name); 3034 fd = open(path1, O_RDONLY); 3035 } 3036 if (fd != -1) { 3037 char buf[21] = {'\0'}; 3038 ssize_t n = read(fd, buf, sizeof(buf)); 3039 3040 close(fd); 3041 if (n != -1) { 3042 *stat = strtoull(buf, NULL, 10); 3043 return 0; 3044 } 3045 } 3046 } 3047 *stat = 0; 3048 return 1; 3049 } 3050 3051 /** 3052 * Remove a MAC address from device 3053 * 3054 * @param dev 3055 * Pointer to Ethernet device structure. 3056 * @param index 3057 * MAC address index. 3058 */ 3059 void 3060 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 3061 { 3062 struct mlx5_priv *priv = dev->data->dev_private; 3063 const int vf = priv->sh->dev_cap.vf; 3064 3065 if (vf) 3066 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 3067 mlx5_ifindex(dev), priv->mac_own, 3068 &dev->data->mac_addrs[index], index); 3069 } 3070 3071 /** 3072 * Adds a MAC address to the device 3073 * 3074 * @param dev 3075 * Pointer to Ethernet device structure. 3076 * @param mac_addr 3077 * MAC address to register. 3078 * @param index 3079 * MAC address index. 3080 * 3081 * @return 3082 * 0 on success, a negative errno value otherwise 3083 */ 3084 int 3085 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 3086 uint32_t index) 3087 { 3088 struct mlx5_priv *priv = dev->data->dev_private; 3089 const int vf = priv->sh->dev_cap.vf; 3090 int ret = 0; 3091 3092 if (vf) 3093 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 3094 mlx5_ifindex(dev), priv->mac_own, 3095 mac, index); 3096 return ret; 3097 } 3098 3099 /** 3100 * Modify a VF MAC address 3101 * 3102 * @param priv 3103 * Pointer to device private data. 3104 * @param mac_addr 3105 * MAC address to modify into. 3106 * @param iface_idx 3107 * Net device interface index 3108 * @param vf_index 3109 * VF index 3110 * 3111 * @return 3112 * 0 on success, a negative errno value otherwise 3113 */ 3114 int 3115 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 3116 unsigned int iface_idx, 3117 struct rte_ether_addr *mac_addr, 3118 int vf_index) 3119 { 3120 return mlx5_nl_vf_mac_addr_modify 3121 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 3122 } 3123 3124 /** 3125 * Set device promiscuous mode 3126 * 3127 * @param dev 3128 * Pointer to Ethernet device structure. 3129 * @param enable 3130 * 0 - promiscuous is disabled, otherwise - enabled 3131 * 3132 * @return 3133 * 0 on success, a negative error value otherwise 3134 */ 3135 int 3136 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 3137 { 3138 struct mlx5_priv *priv = dev->data->dev_private; 3139 3140 return mlx5_nl_promisc(priv->nl_socket_route, 3141 mlx5_ifindex(dev), !!enable); 3142 } 3143 3144 /** 3145 * Set device promiscuous mode 3146 * 3147 * @param dev 3148 * Pointer to Ethernet device structure. 3149 * @param enable 3150 * 0 - all multicase is disabled, otherwise - enabled 3151 * 3152 * @return 3153 * 0 on success, a negative error value otherwise 3154 */ 3155 int 3156 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 3157 { 3158 struct mlx5_priv *priv = dev->data->dev_private; 3159 3160 return mlx5_nl_allmulti(priv->nl_socket_route, 3161 mlx5_ifindex(dev), !!enable); 3162 } 3163 3164 /** 3165 * Flush device MAC addresses 3166 * 3167 * @param dev 3168 * Pointer to Ethernet device structure. 3169 * 3170 */ 3171 void 3172 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 3173 { 3174 struct mlx5_priv *priv = dev->data->dev_private; 3175 3176 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 3177 dev->data->mac_addrs, 3178 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 3179 } 3180