[Modules] Remove potential ODR violations by sinking the DEBUG_TYPE
define below all header includes in the lib/CodeGen/... tree. While the
current modules implementation doesn't check for this kind

[Modules] Remove potential ODR violations by sinking the DEBUG_TYPE
define below all header includes in the lib/CodeGen/... tree. While the
current modules implementation doesn't check for this kind of ODR
violation yet, it is likely to grow support for it in the future. It
also removes one layer of macro pollution across all the included
headers.

Other sub-trees will follow.

llvm-svn: 206837

show more ...

Fix unnecessary line break

llvm-svn: 206772

Patch by Vadim Chugunov

Win64 stack unwinder gets confused when execution flow "falls through" after
a call to 'noreturn' function. This fixes the "missing epilogue" problem by
emitting a trap inst

Patch by Vadim Chugunov

Win64 stack unwinder gets confused when execution flow "falls through" after
a call to 'noreturn' function. This fixes the "missing epilogue" problem by
emitting a trap instruction for IR 'unreachable' on x86_x64-pc-windows.

A secondary use for it would be for anyone wanting to make double-sure that
'noreturn' functions, indeed, do not return.

llvm-svn: 206684

show more ...

Convert SelectionDAG::getVTList to use ArrayRef

llvm-svn: 206357

Break PseudoSourceValue out of the Value hierarchy. It is now the root of its own tree containing FixedStackPseudoSourceValue (which you can use isa/dyn_cast on) and MipsCallEntry (which you can't).

Break PseudoSourceValue out of the Value hierarchy. It is now the root of its own tree containing FixedStackPseudoSourceValue (which you can use isa/dyn_cast on) and MipsCallEntry (which you can't). Anything that needs to use either a PseudoSourceValue* and Value* is strongly encouraged to use a MachinePointerInfo instead.

llvm-svn: 206255

show more ...

[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr.

llvm-svn: 206142

Fix for PR 19261:

llc doesn't generate nodes for unconditional fall-through branches for targets
without FastISel implementation (X86 has it, but can be disabled by
"-fast-isel=false") in SelectionD

Fix for PR 19261:

llc doesn't generate nodes for unconditional fall-through branches for targets
without FastISel implementation (X86 has it, but can be disabled by
"-fast-isel=false") in SelectionDAGBuilder::visitBr().

So for line 4 in the following testcase

1: void foo(int i){
2: switch(i){
3: default:
4: break;
5: }
6: return;
7: }

there is no corresponding line in .debug_line section, and a debugger
cannot set a breakpoint at line 4.

Fix this by always emitting a branch when we're not optimizing and add a
testcase to ensure that there's code on every line we'd want to break.

Patch by Daniil Fukalov.

llvm-svn: 205529

show more ...

Avoid storing Twines.

While there nested ifs into a helper function. No functionality change.

llvm-svn: 205108

Add @llvm.clear_cache builtin

Implementing the LLVM part of the call to __builtin___clear_cache
which translates into an intrinsic @llvm.clear_cache and is lowered
by each target, either to a call t

Add @llvm.clear_cache builtin

Implementing the LLVM part of the call to __builtin___clear_cache
which translates into an intrinsic @llvm.clear_cache and is lowered
by each target, either to a call to __clear_cache or nothing at all
incase the caches are unified.

Updating LangRef and adding some tests for the implemented architectures.
Other archs will have to implement the method in case this builtin
has to be compiled for it, since the default behaviour is to bail
unimplemented.

A Clang patch is required for the builtin to be lowered into the
llvm intrinsic. This will be done next.

llvm-svn: 204802

show more ...

remove a bunch of unused private methods
found with a smarter version of -Wunused-member-function that I'm playwing with.
Appologies in advance if I removed someone's WIP code.

include/llvm/CodeGen

remove a bunch of unused private methods
found with a smarter version of -Wunused-member-function that I'm playwing with.
Appologies in advance if I removed someone's WIP code.

include/llvm/CodeGen/MachineSSAUpdater.h | 1
include/llvm/IR/DebugInfo.h | 3
lib/CodeGen/MachineSSAUpdater.cpp | 10 --
lib/CodeGen/PostRASchedulerList.cpp | 1
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 10 --
lib/IR/DebugInfo.cpp | 12 --
lib/MC/MCAsmStreamer.cpp | 2
lib/Support/YAMLParser.cpp | 39 ---------
lib/TableGen/TGParser.cpp | 16 ---
lib/TableGen/TGParser.h | 1
lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 9 --
lib/Target/ARM/ARMCodeEmitter.cpp | 12 --
lib/Target/ARM/ARMFastISel.cpp | 84 --------------------
lib/Target/Mips/MipsCodeEmitter.cpp | 11 --
lib/Target/Mips/MipsConstantIslandPass.cpp | 12 --
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 21 -----
lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 2
lib/Target/PowerPC/PPCFastISel.cpp | 1
lib/Transforms/Instrumentation/AddressSanitizer.cpp | 2
lib/Transforms/Instrumentation/BoundsChecking.cpp | 2
lib/Transforms/Instrumentation/MemorySanitizer.cpp | 1
lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 8 -
lib/Transforms/Scalar/SCCP.cpp | 1
utils/TableGen/CodeEmitterGen.cpp | 2
24 files changed, 2 insertions(+), 261 deletions(-)

llvm-svn: 204560

show more ...

Fix an assertion caused by using inline asm with indirect register inputs.

llvm-svn: 204425

IR: add a second ordering operand to cmpxhg for failure

The syntax for "cmpxchg" should now look something like:

cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic

where the second ordering argu

IR: add a second ordering operand to cmpxhg for failure

The syntax for "cmpxchg" should now look something like:

cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic

where the second ordering argument gives the required semantics in the case
that no exchange takes place. It should be no stronger than the first ordering
constraint and cannot be either "release" or "acq_rel" (since no store will
have taken place).

rdar://problem/15996804

llvm-svn: 203559

show more ...

[C++11] Add range based accessors for the Use-Def chain of a Value.

This requires a number of steps.
1) Move value_use_iterator into the Value class as an implementation
detail
2) Change it to ac

[C++11] Add range based accessors for the Use-Def chain of a Value.

This requires a number of steps.
1) Move value_use_iterator into the Value class as an implementation
detail
2) Change it to actually be a *Use* iterator rather than a *User*
iterator.
3) Add an adaptor which is a User iterator that always looks through the
Use to the User.
4) Wrap these in Value::use_iterator and Value::user_iterator typedefs.
5) Add the range adaptors as Value::uses() and Value::users().
6) Update *all* of the callers to correctly distinguish between whether
they wanted a use_iterator (and to explicitly dig out the User when
needed), or a user_iterator which makes the Use itself totally
opaque.

Because #6 requires churning essentially everything that walked the
Use-Def chains, I went ahead and added all of the range adaptors and
switched them to range-based loops where appropriate. Also because the
renaming requires at least churning every line of code, it didn't make
any sense to split these up into multiple commits -- all of which would
touch all of the same lies of code.

The result is still not quite optimal. The Value::use_iterator is a nice
regular iterator, but Value::user_iterator is an iterator over User*s
rather than over the User objects themselves. As a consequence, it fits
a bit awkwardly into the range-based world and it has the weird
extra-dereferencing 'operator->' that so many of our iterators have.
I think this could be fixed by providing something which transforms
a range of T&s into a range of T*s, but that *can* be separated into
another patch, and it isn't yet 100% clear whether this is the right
move.

However, this change gets us most of the benefit and cleans up
a substantial amount of code around Use and User. =]

llvm-svn: 203364

show more ...

[Layering] Move DebugInfo.h into the IR library where its implementation
already lives.

llvm-svn: 203046

Check for dynamic allocas and inline asm that clobbers sp before building
selection dag (PR19012)

In X86SelectionDagInfo::EmitTargetCodeForMemcpy we check with MachineFrameInfo
to make sure that ESI

Check for dynamic allocas and inline asm that clobbers sp before building
selection dag (PR19012)

In X86SelectionDagInfo::EmitTargetCodeForMemcpy we check with MachineFrameInfo
to make sure that ESI isn't used as a base pointer register before we choose to
emit rep movs (which clobbers esi).

The problem is that MachineFrameInfo wouldn't know about dynamic allocas or
inline asm that clobbers the stack pointer until SelectionDAGBuilder has
encountered them.

This patch fixes the problem by checking for such things when building the
FunctionLoweringInfo.

Differential Revision: http://llvm-reviews.chandlerc.com/D2954

llvm-svn: 202930

show more ...

[C++11] Replace llvm::next and llvm::prior with std::next and std::prev.

Remove the old functions.

llvm-svn: 202636

Rename a few more DataLayout variables from TD to DL.

llvm-svn: 201870

[DAG] Fix the recognition of opaque constants in the SelectionDAGBuilder.

This fix checks the original LLVM IR node to identify opaque constants by
looking for the bitcast-constant pattern. Original

[DAG] Fix the recognition of opaque constants in the SelectionDAGBuilder.

This fix checks the original LLVM IR node to identify opaque constants by
looking for the bitcast-constant pattern. Originally we looked at the generated
SDNode, but this might lead to incorrect results. The SDNode could have been
generated by an constant expression that was folded to a constant.

This fixes <rdar://problem/16050719>

llvm-svn: 201291

show more ...

[Stackmaps] Improve the stackmap lowering code in the SelectionDAGBuilder.

We are now no longer relying on the target-specific call lowering implementation
to lower a stackmap intrinsic call. Instea

[Stackmaps] Improve the stackmap lowering code in the SelectionDAGBuilder.

We are now no longer relying on the target-specific call lowering implementation
to lower a stackmap intrinsic call. Instead we perform the call lowering in a
target-independent way directly in the stackmap lowering code. This simplifies
the code and removes the need to fixup the code after the target-specific call
lowering.

llvm-svn: 201263

show more ...

[Stackmaps] Fix the ID type to be i64 also for stackmaps (as we claim in the documenation)

The ID type for the stackmap and patchpoint intrinsics are in both cases i64.
This fixes an zero extend in

[Stackmaps] Fix the ID type to be i64 also for stackmaps (as we claim in the documenation)

The ID type for the stackmap and patchpoint intrinsics are in both cases i64.
This fixes an zero extend in the SelectionDAGBuilder that still used i32. This
also updates the target independent instructions STACKMAP and PATCHPOINT to use
the correct type.

llvm-svn: 201262

show more ...

Pass address space to allowsUnalignedMemoryAccesses

llvm-svn: 200888

Implement inalloca codegen for x86 with the new inalloca design

Calls with inalloca are lowered by skipping all stores for arguments
passed in memory and the initial stack adjustment to allocate arg

Implement inalloca codegen for x86 with the new inalloca design

Calls with inalloca are lowered by skipping all stores for arguments
passed in memory and the initial stack adjustment to allocate argument
memory.

Now the frontend is responsible for the memory layout, and the backend
doesn't have to do any work. As a result these changes are pretty
minimal.

Reviewers: echristo

Differential Revision: http://llvm-reviews.chandlerc.com/D2637

llvm-svn: 200596

show more ...

PGO branch weight: update edge weights in SelectionDAGBuilder.

When converting from "or + br" to two branches, or converting from
"and + br" to two branches, we correctly update the edge weights of

PGO branch weight: update edge weights in SelectionDAGBuilder.

When converting from "or + br" to two branches, or converting from
"and + br" to two branches, we correctly update the edge weights of
the two branches.

The previous attempt at r200431 was reverted at r200434 because of
two testing case failures. I modified my patch a little, but forgot
to re-run "make check-all".

Testing case CodeGen/ARM/lsr-unfolded-offset.ll is updated because of
the patch's impact on branch probability which causes changes in
spill placement.

llvm-svn: 200502

show more ...

Revert r200431 due to bot failures.

llvm-svn: 200434

PGO branch weight: update edge weights in SelectionDAGBuilder.

When converting from "or + br" to two branches, or converting from
"and + br" to two branches, we correctly update the edge weights of

PGO branch weight: update edge weights in SelectionDAGBuilder.

When converting from "or + br" to two branches, or converting from
"and + br" to two branches, we correctly update the edge weights of
the two branches.

llvm-svn: 200431

show more ...