| /llvm-project/polly/docs/ |
| H A D | UsingPollyWithClang.rst | 55 -polly-scheduling[=SCHED]
56 set the OpenMP scheduling type; SCHED can be 'static', 'dynamic', 'guided' or 'runtime' (the default);
58 -polly-scheduling-chunksize[=CHUNK]
59 set the chunksize (for the selected scheduling type); CHUNK may be any strictly positive integer (otherwise it will default to 1);
62 `polly-num-threads` and `polly-scheduling` switches, where the latter also has
65 Example: Use alternative backend with dynamic scheduling, four threads and
71 -mllvm -polly-scheduling=dynamic -mllvm -polly-scheduling-chunksize=1
185 Polly uses by default the isl scheduling optimizer. The isl optimizer optimizes
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| /llvm-project/llvm/docs/CommandGuide/ |
| H A D | lli.rst | 138 Disable scheduling after register allocation.
163 =none: No scheduling: breadth first sequencing
164 =simple: Simple two pass scheduling: minimize critical path and maximize processor utilization
165 =simple-noitin: Simple two pass scheduling: Same as simple except using generic latency
166 =list-burr: Bottom-up register reduction list scheduling
167 =list-tdrr: Top-down register reduction list scheduling
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| H A D | llvm-mca.rst | 15 available in LLVM (e.g. scheduling models) to statically measure the performance
20 there is a scheduling model available in LLVM.
52 inevitably affected by the quality of the scheduling models in LLVM.
107 defaults to field 'IssueWidth' in the processor scheduling model. If width is
240 not parse or lack key scheduling information. Note that the resulting analysis
377 instructions to use the scheduling behaviour of its pseudo-instruction
938 of the ``IssueWidth`` in LLVM's scheduling model.
956 number of micro-opcodes specified for that instruction by the target scheduling
960 `MicroOpBufferSize` in the target scheduling model.
963 entries. :program:`llvm-mca` queries the scheduling model to determine the set
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| /llvm-project/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-misched-multimmo.ll | 8 ; Check that no scheduling dependencies are created between the paired loads and the store during p…
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| /llvm-project/llvm/test/CodeGen/PowerPC/ |
| H A D | tls-store2.ll | 26 ; works because, with new scheduling freedom, we create a copy of R3 based on the
27 ; initial scheduling, but don't coalesce it again after we move the instructions
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleM7.td | 26 // pipe. The stages relevant to scheduling are as follows:
35 // for scheduling, so simple ALU operations executing in EX2 will have
138 // Division. Effective scheduling latency is 3, though real latency is larger
145 // Square-root. Effective scheduling latency is 3; real latency is larger
238 // Load/store multiples cannot be dual-issued. Note that default scheduling
353 // single-cycle as far as scheduling opportunities go. By putting WriteALU
408 // Effective scheduling latency is really 3 for nearly all FP operations,
470 // making it appear to have 3 cycle latency for scheduling.
489 // it appear to have 3 cycle latency for scheduling.
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| H A D | ARMScheduleM55.td | 9 // This file defines the scheduling model for the Arm Cortex-M55 processors.
14 // Cortex-M55 is a lot like the M4/M33 in terms of scheduling. It technically
15 // has an extra pipeline stage but that is unimportant for scheduling, just
56 // not relevant (they will not appear when scheduling), Brs are only at the end
60 // instructions at the point in the pipeline where we do the scheduling. The
61 // Thumb2SizeReductionPass has not been run yet. Especially pre-ra scheduling
80 // Post-RA scheduling sees what is T1/T2. It may also be possible to write a
210 // for scheduling
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| /llvm-project/llvm/test/CodeGen/AMDGPU/ |
| H A D | lds-output-queue.ll | 34 ; This is a problem for scheduling the reads from the local data share (lds).
83 ; expanding them after scheduling. Once the scheduler has better alias
85 ; scheduling.
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| /llvm-project/llvm/test/CodeGen/Hexagon/ |
| H A D | swp-ws-fail-0.mir | 16 # CHECK-ANALYSE-II: Window scheduling is not needed!
17 # CHECK-SCHED-NOT-NEEDED: Window scheduling is not needed!
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| H A D | tc_sched1.ll | 3 ; Another scheduling test for Tiny Core.
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| /llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetItinerary.td | 9 // This file defines the target-independent scheduling interfaces
11 // itineraries for scheduling. Itineraries are detailed reservation
13 // in-order machine with complicated scheduling or bundling constraints.
22 // during scheduling and has an affect instruction order based on availability
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| H A D | TargetSchedule.td | 9 // This file defines the target-independent scheduling interfaces which should
10 // be implemented by each target which is using TableGen based scheduling.
91 // that have a scheduling class (itinerary class or SchedRW list)
114 // to skip the checks for scheduling information when building LLVM for
173 // an in-order pipeline within an out-of-order core where scheduling
264 // Allow a processor to mark some scheduling classes as unsupported
267 // Allow a processor to mark some scheduling classes as single-issue.
327 // Allow a processor to mark some scheduling classes as unsupported
364 // Base class for scheduling predicates.
367 // A scheduling predicate whose logic is defined by a MCInstPredicate.
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| /llvm-project/llvm/test/tools/llvm-mca/X86/ |
| H A D | no-sched-model.s | 3 # CHECK: error: unable to find instruction-level scheduling information for target triple 'x86_64-u…
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| /llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| H A D | unsupported-write-variant.s | 7 # CHECK: error: unable to resolve scheduling class for write variant.
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| /llvm-project/polly/lib/External/isl/cpp/ |
| H A D | cpp-checked-conversion.h.top | 6 /// polyhedral compilation, ranging from dependence analysis over scheduling
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| H A D | typed_cpp.h.top | 5 /// polyhedral compilation, ranging from dependence analysis over scheduling
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| /llvm-project/llvm/test/CodeGen/X86/ |
| H A D | break-anti-dependencies.ll | 2 ; Without list-burr scheduling we may not see the difference in codegen here.
3 ; Use a subtarget that has post-RA scheduling enabled because the anti-dependency
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| /llvm-project/llvm/test/CodeGen/ARM/ |
| H A D | cortex-a57-misched-vstm.ll | 5 ; We need second, post-ra scheduling to have VSTM instruction combined from single-stores
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| H A D | postrasched.ll | 5 ; Pre and post ra machine scheduling
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| /llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/ |
| H A D | A55-2-skewed-alu.s | 14 # MCA and LLVM scheduling model do not support this yet.
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| H A D | A55-4-sdiv.s | 5 # number of cycles depending on its operands, but LLVM scheduling
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| H A D | A55-8-ldr.s | 15 # the LLVM scheduling model.
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| H A D | A55-5-mul-sdiv.s | 5 # number of cycles depending on its operands. LLVM scheduling model
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| H A D | A55-6-mul.s | 10 # FIXME: MCA (and LLVM scheduling model) do not support this. The test
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| /llvm-project/llvm/docs/HistoricalNotes/ |
| H A D | 2001-06-01-GCCOptimizations2.txt | 55 3. Instruction scheduling: 'nuff said :)
62 10. Delay slot scheduling
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