xref: /llvm-project/llvm/test/CodeGen/AArch64/arm64-misched-multimmo.ll (revision 5ddce70ef0e5a641d7fea95e31fc5e2439cb98cb)
1; REQUIRES: asserts
2; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched=0 -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
3
4
5@G1 = common dso_local global [100 x i32] zeroinitializer, align 4
6@G2 = common dso_local global [100 x i32] zeroinitializer, align 4
7
8; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling.
9;
10; CHECK-LABEL: # Machine code for function foo:
11; CHECK: SU(2):   renamable $w{{[0-9]+}}, renamable $w{{[0-9]+}} = LDPWi
12; CHECK: Successors:
13; CHECK-NOT: ch SU(4)
14; CHECK: SU(3)
15; CHECK: SU(4):   STRWui $wzr, renamable $x{{[0-9]+}}
16define dso_local i32 @foo() {
17entry:
18  %0 = load i32, ptr @G2, align 4
19  %1 = load i32, ptr getelementptr inbounds ([100 x i32], ptr @G2, i64 0, i64 1), align 4
20  store i32 0, ptr @G1, align 4
21  %add = add nsw i32 %1, %0
22  ret i32 %add
23}
24