1# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-views=false --summary-view --iterations=1000 < %s | FileCheck %s 2# CHECK: IPC: 3# CHECK-SAME: 1.50 4# 5# XFAIL: * 6# 7# MCA reports IPC = 0.60, while hardware shows IPC = 1.50. 8# 9# 1) The skewed ALU on Cortex-A55 is not modeled: ADD and AND 10# instructions should be issued in the same cycle. 11# See A55-2.s test for more details. 12# 13# 2) Cortex-A55 manual mentions that there is a forwarding path from 14# the ALU pipeline to the LD/ST pipeline. This is not implemented in 15# the LLVM scheduling model. 16 17add w8, w8, #1 18and w12, w8, #0x3f 19ldr w14, [x10, w12, uxtw #2] 20