1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-views=false --summary-view --iterations=1000 < %s | FileCheck %s 3 4# DIV is not modeled precisely: on hardware it takes variable 5# number of cycles depending on its operands. LLVM scheduling model 6# only provides an average latency. 7 8add w8, w8, #1 9movz w10, #1, lsl #16 10movz w12, #32768, lsl #16 11mul w11, w8, w8 12sdiv w10, w12, w10 13 14# CHECK: Iterations: 1000 15# CHECK-NEXT: Instructions: 5000 16# CHECK-NEXT: Total Cycles: 8004 17# CHECK-NEXT: Total uOps: 5000 18 19# CHECK: Dispatch Width: 2 20# CHECK-NEXT: uOps Per Cycle: 0.62 21# CHECK-NEXT: IPC: 0.62 22# CHECK-NEXT: Block RThroughput: 8.0 23