1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-views=false --summary-view --iterations=1000 < %s | FileCheck %s 3 4# It appears that ADD and MUL fuse together, if both can be issued in 5# one cycle: 6# 7# add w12, w8, #1 8# mul w10, w12, w10 9# 10# FIXME: MCA (and LLVM scheduling model) do not support this. The test 11# case uses different registers to break the pattern. 12 13add w8, w8, #1 14add w13, w8, #1 15mul w10, w12, w10 16 17# CHECK: Iterations: 1000 18# CHECK-NEXT: Instructions: 3000 19# CHECK-NEXT: Total Cycles: 3003 20# CHECK-NEXT: Total uOps: 3000 21 22# CHECK: Dispatch Width: 2 23# CHECK-NEXT: uOps Per Cycle: 1.00 24# CHECK-NEXT: IPC: 1.00 25# CHECK-NEXT: Block RThroughput: 1.5 26