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/llvm-project/llvm/unittests/ADT/
H A DMapVectorTest.cpp70 MapVector<int, int> MV; in TEST() local
73 R = MV.insert(std::make_pair(1, 2)); in TEST()
74 ASSERT_EQ(R.first, MV.begin()); in TEST()
79 R = MV.insert(std::make_pair(1, 3)); in TEST()
80 ASSERT_EQ(R.first, MV.begin()); in TEST()
85 R = MV.insert(std::make_pair(4, 5)); in TEST()
86 ASSERT_NE(R.first, MV.end()); in TEST()
91 EXPECT_EQ(MV.size(), 2u); in TEST()
92 EXPECT_EQ(MV[1], 2); in TEST()
93 EXPECT_EQ(MV[4], 5); in TEST()
[all …]
/llvm-project/llvm/test/CodeGen/RISCV/
H A Ddouble-select-icmp.ll25 ; RV32ZDINX-NEXT: mv a2, a4
26 ; RV32ZDINX-NEXT: mv a3, a5
28 ; RV32ZDINX-NEXT: mv a0, a2
29 ; RV32ZDINX-NEXT: mv a1, a3
36 ; RV64ZDINX-NEXT: mv a2, a3
38 ; RV64ZDINX-NEXT: mv a0, a2
58 ; RV32ZDINX-NEXT: mv a2, a4
59 ; RV32ZDINX-NEXT: mv a3, a5
61 ; RV32ZDINX-NEXT: mv a0, a2
62 ; RV32ZDINX-NEXT: mv a1, a3
[all …]
H A Dfmax-fmin.ll34 ; R32-NEXT: mv s1, a1
35 ; R32-NEXT: mv s0, a0
39 ; R32-NEXT: mv s0, s1
41 ; R32-NEXT: mv a0, s0
54 ; R64-NEXT: mv s1, a1
55 ; R64-NEXT: mv s0, a0
59 ; R64-NEXT: mv s0, s1
61 ; R64-NEXT: mv a0, s0
102 ; R32-NEXT: mv s1, a3
103 ; R32-NEXT: mv s2, a2
[all …]
H A Dcm_mvas_mvsa.ll22 ; CHECK32I-NEXT: mv s0, a1
23 ; CHECK32I-NEXT: mv s1, a0
25 ; CHECK32I-NEXT: mv s2, a0
26 ; CHECK32I-NEXT: mv a0, s1
27 ; CHECK32I-NEXT: mv a1, s0
42 ; CHECK32ZCMP-NEXT: mv s2, a0
55 ; CHECK64I-NEXT: mv s0, a1
56 ; CHECK64I-NEXT: mv s1, a0
58 ; CHECK64I-NEXT: mv s2, a0
59 ; CHECK64I-NEXT: mv a0, s1
[all …]
H A Ddouble-arith.ll274 ; RV32I-NEXT: mv a2, a0
275 ; RV32I-NEXT: mv a3, a1
279 ; RV32I-NEXT: mv a2, a0
290 ; RV64I-NEXT: mv a1, a0
381 ; RV32I-NEXT: mv a3, a1
384 ; RV32I-NEXT: mv a2, a0
395 ; RV64I-NEXT: mv a1, a0
561 ; RV32I-NEXT: mv s0, a3
562 ; RV32I-NEXT: mv s1, a2
563 ; RV32I-NEXT: mv s
[all...]
H A Dbittest.ll556 ; CHECK-NEXT: mv a0, a1
559 ; CHECK-NEXT: mv a0, a2
572 ; RV32-NEXT: mv a0, a1
575 ; RV32-NEXT: mv a0, a2
582 ; RV64-NEXT: mv a0, a1
585 ; RV64-NEXT: mv a0, a2
598 ; RV32-NEXT: mv a0, a1
601 ; RV32-NEXT: mv a0, a2
608 ; RV64-NEXT: mv a0, a1
611 ; RV64-NEXT: mv a
[all...]
H A Dselect-cc.ll15 ; RV32I-NEXT: mv a0, a2
20 ; RV32I-NEXT: mv a0, a2
25 ; RV32I-NEXT: mv a0, a2
30 ; RV32I-NEXT: mv a0, a2
35 ; RV32I-NEXT: mv a0, a2
40 ; RV32I-NEXT: mv a0, a2
45 ; RV32I-NEXT: mv a0, a2
50 ; RV32I-NEXT: mv a0, a2
55 ; RV32I-NEXT: mv a0, a2
60 ; RV32I-NEXT: mv a
[all...]
H A Dcalls.ll256 ; CHECK-NEXT: mv a2, a0
257 ; CHECK-NEXT: mv a0, a1
267 ; RV64I-NEXT: mv a2, a0
268 ; RV64I-NEXT: mv a0, a1
278 ; RV64I-SMALL-NEXT: mv a2, a0
279 ; RV64I-SMALL-NEXT: mv a0, a1
289 ; RV64I-MEDIUM-NEXT: mv a2, a0
290 ; RV64I-MEDIUM-NEXT: mv a0, a1
300 ; RV64I-LARGE-NEXT: mv a2, a0
301 ; RV64I-LARGE-NEXT: mv a
[all...]
H A Durem-vector-lkk.ll26 ; RV32I-NEXT: mv s3, a0
28 ; RV32I-NEXT: mv a0, a2
30 ; RV32I-NEXT: mv s4, a0
32 ; RV32I-NEXT: mv a0, s0
34 ; RV32I-NEXT: mv s0, a0
36 ; RV32I-NEXT: mv a0, s1
38 ; RV32I-NEXT: mv s1, a0
40 ; RV32I-NEXT: mv a0, s2
105 ; RV64I-NEXT: mv s3, a0
107 ; RV64I-NEXT: mv a
[all...]
H A Dfloat-arith.ll235 ; RV32I-NEXT: mv a1, a0
249 ; RV64I-NEXT: mv a1, a0
283 ; RV32I-NEXT: mv s0, a0
301 ; RV64I-NEXT: mv s0, a0
341 ; RV32I-NEXT: mv a1, a0
354 ; RV64I-NEXT: mv a1, a0
489 ; RV32I-NEXT: mv s0, a1
490 ; RV32I-NEXT: mv s1, a0
491 ; RV32I-NEXT: mv a0, a2
496 ; RV32I-NEXT: mv a
[all...]
H A Ddouble-arith-strict.ll401 ; RV32I-NEXT: mv s0, a3
402 ; RV32I-NEXT: mv s1, a2
403 ; RV32I-NEXT: mv s2, a1
404 ; RV32I-NEXT: mv s3, a0
405 ; RV32I-NEXT: mv a0, a4
406 ; RV32I-NEXT: mv a1, a5
410 ; RV32I-NEXT: mv a4, a0
413 ; RV32I-NEXT: mv a0, s3
414 ; RV32I-NEXT: mv a1, s2
415 ; RV32I-NEXT: mv a2, s1
[all …]
H A Dhalf-arith.ll46 ; RV32I-NEXT: mv s0, a1
51 ; RV32I-NEXT: mv s1, a0
54 ; RV32I-NEXT: mv a1, a0
55 ; RV32I-NEXT: mv a0, s1
72 ; RV64I-NEXT: mv s0, a1
77 ; RV64I-NEXT: mv s1, a0
80 ; RV64I-NEXT: mv a1, a0
81 ; RV64I-NEXT: mv a0, s1
128 ; RV32I-NEXT: mv s0, a1
133 ; RV32I-NEXT: mv s
[all...]
H A Dshort-forward-branch-opt.ll11 ; The sifive-7-series can predicate a mv.
18 ; NOSFB-NEXT: mv a0, a1
26 ; SFB-NEXT: mv a0, a1
40 ; NOSFB-NEXT: mv a1, a0
42 ; NOSFB-NEXT: mv a0, a1
49 ; SFB-NEXT: mv a0, a1
64 ; NOSFB-NEXT: mv a1, a0
65 ; NOSFB-NEXT: mv a2, a3
74 ; RV64SFB-NEXT: mv a2, a3
78 ; RV64SFB-NEXT: mv a
[all...]
H A Dinline-asm-abi-names.ll63 ; RV32I-NEXT: mv ra, a0
75 ; RV64I-NEXT: mv ra, a0
92 ; RV32I-NEXT: mv ra, a0
104 ; RV64I-NEXT: mv ra, a0
118 ; RV32I-NEXT: mv sp, a0
126 ; RV64I-NEXT: mv sp, a0
138 ; RV32I-NEXT: mv sp, a0
146 ; RV64I-NEXT: mv sp, a0
159 ; RV32I-NEXT: mv gp, a0
167 ; RV64I-NEXT: mv gp, a0
[all …]
H A Ddouble-select-fcmp.ll19 ; CHECKRV32ZDINX-NEXT: mv a1, a3
20 ; CHECKRV32ZDINX-NEXT: mv a0, a2
25 ; CHECKRV64ZDINX-NEXT: mv a0, a1
47 ; CHECKRV32ZDINX-NEXT: mv a0, a2
48 ; CHECKRV32ZDINX-NEXT: mv a1, a3
57 ; CHECKRV64ZDINX-NEXT: mv a0, a1
80 ; CHECKRV32ZDINX-NEXT: mv a0, a2
81 ; CHECKRV32ZDINX-NEXT: mv a1, a3
90 ; CHECKRV64ZDINX-NEXT: mv a0, a1
113 ; CHECKRV32ZDINX-NEXT: mv a
[all...]
H A Dllvm.frexp.ll44 ; RV64IFD-NEXT: mv a0, sp
78 ; RV64IZFINXZDINX-NEXT: mv a1, sp
145 ; RV64IFD-NEXT: mv a0, sp
177 ; RV64IZFINXZDINX-NEXT: mv a1, sp
238 ; RV64IFD-NEXT: mv a0, sp
262 ; RV64IZFINXZDINX-NEXT: mv a1, sp
335 ; RV64IFD-NEXT: mv a0, sp
357 ; RV64IZFINXZDINX-NEXT: mv a1, sp
404 ; RV64IFD-NEXT: mv a0, sp
424 ; RV64IZFINXZDINX-NEXT: mv a
[all...]
H A Dsrem-vector-lkk.ll25 ; RV32I-NEXT: mv s3, a0
27 ; RV32I-NEXT: mv a0, a2
29 ; RV32I-NEXT: mv s4, a0
31 ; RV32I-NEXT: mv a0, s0
33 ; RV32I-NEXT: mv s0, a0
35 ; RV32I-NEXT: mv a0, s1
37 ; RV32I-NEXT: mv s1, a0
39 ; RV32I-NEXT: mv a0, s2
117 ; RV64I-NEXT: mv s3, a0
119 ; RV64I-NEXT: mv a
[all...]
H A Ddouble-convert.ll163 ; RV32I-NEXT: mv s0, a1
164 ; RV32I-NEXT: mv s1, a0
169 ; RV32I-NEXT: mv s2, a0
171 ; RV32I-NEXT: mv a0, s1
172 ; RV32I-NEXT: mv a1, s0
175 ; RV32I-NEXT: mv s4, a0
176 ; RV32I-NEXT: mv a0, s1
177 ; RV32I-NEXT: mv a1, s0
179 ; RV32I-NEXT: mv s3, a0
189 ; RV32I-NEXT: mv a
[all...]
H A Datomic-rmw-discard.ll194 ; RV32-NEXT: mv s0, a2
195 ; RV32-NEXT: mv s1, a0
198 ; RV32-NEXT: mv s2, a1
207 ; RV32-NEXT: mv a0, s1
218 ; RV32-NEXT: mv a2, a4
219 ; RV32-NEXT: mv a3, a5
224 ; RV32-NEXT: mv a2, a4
225 ; RV32-NEXT: mv a3, a5
229 ; RV32-NEXT: mv a2, s2
230 ; RV32-NEXT: mv a
[all...]
H A Datomicrmw-uinc-udec-wrap.ll27 ; RV32I-NEXT: mv s0, a0
41 ; RV32I-NEXT: mv a0, s0
46 ; RV32I-NEXT: mv a0, a3
70 ; RV32IA-NEXT: mv a5, a4
105 ; RV64I-NEXT: mv s0, a0
119 ; RV64I-NEXT: mv a0, s0
124 ; RV64I-NEXT: mv a0, a3
189 ; RV32I-NEXT: mv s0, a0
205 ; RV32I-NEXT: mv a0, s0
210 ; RV32I-NEXT: mv a
[all...]
H A Dcondops.ll460 ; RV32I-NEXT: mv a1, a2
478 ; RV32XVENTANACONDOPS-NEXT: mv a1, a2
501 ; RV32ZICOND-NEXT: mv a1, a2
524 ; RV32I-NEXT: mv a1, a2
542 ; RV32XVENTANACONDOPS-NEXT: mv a1, a2
565 ; RV32ZICOND-NEXT: mv a1, a2
1026 ; RV32I-NEXT: mv a0, a1
1027 ; RV32I-NEXT: mv a1, a2
1036 ; RV64I-NEXT: mv a0, a1
1060 ; RV64XTHEADCONDMOV-NEXT: mv a
[all...]
H A Dselect-optimize-multiple.ll17 ; RV32I-NEXT: mv a1, a3
18 ; RV32I-NEXT: mv a2, a4
20 ; RV32I-NEXT: mv a0, a1
21 ; RV32I-NEXT: mv a1, a2
29 ; RV64I-NEXT: mv a1, a2
31 ; RV64I-NEXT: mv a0, a1
44 ; RV32I-NEXT: mv a2, a3
47 ; RV32I-NEXT: mv a2, a4
84 ; RV64I-NEXT: mv a1, a3
85 ; RV64I-NEXT: mv a
[all...]
H A Drv32i-rv64i-half.ll20 ; RV32I-NEXT: mv s0, a1
25 ; RV32I-NEXT: mv s1, a0
28 ; RV32I-NEXT: mv s0, a0
29 ; RV32I-NEXT: mv a0, s1
30 ; RV32I-NEXT: mv a1, s0
35 ; RV32I-NEXT: mv a1, s0
52 ; RV64I-NEXT: mv s0, a1
57 ; RV64I-NEXT: mv s1, a0
60 ; RV64I-NEXT: mv s0, a0
61 ; RV64I-NEXT: mv a0, s1
[all …]
/llvm-project/llvm/test/Transforms/MemCpyOpt/
H A Dform-memset.ll82 %struct.MV = type { i16, i16 }
89 ; CHECK-NEXT: [[LEFT_MVD:%.*]] = alloca [8 x %struct.MV], align 8
90 ; CHECK-NEXT: [[UP_MVD:%.*]] = alloca [8 x %struct.MV], align 8
99 ; CHECK-NEXT: [[TMP43:%.*]] = getelementptr [8 x %struct.MV], ptr [[UP_MVD]], i32 0, i32 7, i32 0
101 ; CHECK-NEXT: [[TMP46:%.*]] = getelementptr [8 x %struct.MV], ptr [[UP_MVD]], i32 0, i32 7, i32 1
102 ; CHECK-NEXT: [[TMP57:%.*]] = getelementptr [8 x %struct.MV], ptr [[UP_MVD]], i32 0, i32 6, i32 0
103 ; CHECK-NEXT: [[TMP60:%.*]] = getelementptr [8 x %struct.MV], ptr [[UP_MVD]], i32 0, i32 6, i32 1
104 ; CHECK-NEXT: [[TMP71:%.*]] = getelementptr [8 x %struct.MV], ptr [[UP_MVD]], i32 0, i32 5, i32 0
105 ; CHECK-NEXT: [[TMP74:%.*]] = getelementptr [8 x %struct.MV], ptr [[UP_MVD]], i32 0, i32 5, i32 1
106 ; CHECK-NEXT: [[TMP85:%.*]] = getelementptr [8 x %struct.MV], pt
[all...]
/llvm-project/lld/test/ELF/lto/
H A Dsave-temps-eq.ll17 ; RUN: mv a.out.lto.* *.o.*.bc %t/all
24 ; RUN: mv a.out.lto.* *.o.* %t/all2
42 ; RUN: mv *.0.preopt.* %t/all3
48 ; RUN: mv *.1.promote* %t/all3
54 ; RUN: mv *.2.internalize* %t/all3
60 ; RUN: mv *.3.import* %t/all3
67 ; RUN: mv *.4.opt* %t/all3
73 ; RUN: mv *.5.precodegen* %t/all3
79 ; RUN: mv *.index.bc %t/all3
80 ; RUN: mv *.index.dot %t/all3
[all …]

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