1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefixes=CHECK,RV32,RV32I 4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s -check-prefixes=CHECK,RV64,RV64I 6; RUN: llc -mtriple=riscv32 -mattr=+zbs -verify-machineinstrs < %s \ 7; RUN: | FileCheck %s -check-prefixes=CHECK,ZBS,RV32,RV32ZBS 8; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \ 9; RUN: | FileCheck %s -check-prefixes=CHECK,ZBS,RV64,RV64ZBS 10; RUN: llc -mtriple=riscv32 -mattr=+xtheadbs -verify-machineinstrs < %s \ 11; RUN: | FileCheck %s -check-prefixes=CHECK,XTHEADBS,RV32,RV32XTHEADBS 12; RUN: llc -mtriple=riscv64 -mattr=+xtheadbs -verify-machineinstrs < %s \ 13; RUN: | FileCheck %s -check-prefixes=CHECK,XTHEADBS,RV64,RV64XTHEADBS 14 15define signext i32 @bittest_7_i32(i32 signext %a) nounwind { 16; CHECK-LABEL: bittest_7_i32: 17; CHECK: # %bb.0: 18; CHECK-NEXT: andi a0, a0, 128 19; CHECK-NEXT: seqz a0, a0 20; CHECK-NEXT: ret 21 %shr = lshr i32 %a, 7 22 %not = xor i32 %shr, -1 23 %and = and i32 %not, 1 24 ret i32 %and 25} 26 27define signext i32 @bittest_10_i32(i32 signext %a) nounwind { 28; CHECK-LABEL: bittest_10_i32: 29; CHECK: # %bb.0: 30; CHECK-NEXT: andi a0, a0, 1024 31; CHECK-NEXT: seqz a0, a0 32; CHECK-NEXT: ret 33 %shr = lshr i32 %a, 10 34 %not = xor i32 %shr, -1 35 %and = and i32 %not, 1 36 ret i32 %and 37} 38 39define signext i32 @bittest_11_i32(i32 signext %a) nounwind { 40; RV32I-LABEL: bittest_11_i32: 41; RV32I: # %bb.0: 42; RV32I-NEXT: not a0, a0 43; RV32I-NEXT: slli a0, a0, 20 44; RV32I-NEXT: srli a0, a0, 31 45; RV32I-NEXT: ret 46; 47; RV64I-LABEL: bittest_11_i32: 48; RV64I: # %bb.0: 49; RV64I-NEXT: not a0, a0 50; RV64I-NEXT: slli a0, a0, 52 51; RV64I-NEXT: srli a0, a0, 63 52; RV64I-NEXT: ret 53; 54; ZBS-LABEL: bittest_11_i32: 55; ZBS: # %bb.0: 56; ZBS-NEXT: not a0, a0 57; ZBS-NEXT: bexti a0, a0, 11 58; ZBS-NEXT: ret 59; 60; XTHEADBS-LABEL: bittest_11_i32: 61; XTHEADBS: # %bb.0: 62; XTHEADBS-NEXT: not a0, a0 63; XTHEADBS-NEXT: th.tst a0, a0, 11 64; XTHEADBS-NEXT: ret 65 %shr = lshr i32 %a, 11 66 %not = xor i32 %shr, -1 67 %and = and i32 %not, 1 68 ret i32 %and 69} 70 71define signext i32 @bittest_31_i32(i32 signext %a) nounwind { 72; RV32-LABEL: bittest_31_i32: 73; RV32: # %bb.0: 74; RV32-NEXT: not a0, a0 75; RV32-NEXT: srli a0, a0, 31 76; RV32-NEXT: ret 77; 78; RV64-LABEL: bittest_31_i32: 79; RV64: # %bb.0: 80; RV64-NEXT: not a0, a0 81; RV64-NEXT: srliw a0, a0, 31 82; RV64-NEXT: ret 83 %shr = lshr i32 %a, 31 84 %not = xor i32 %shr, -1 85 %and = and i32 %not, 1 86 ret i32 %and 87} 88 89define i64 @bittest_7_i64(i64 %a) nounwind { 90; RV32-LABEL: bittest_7_i64: 91; RV32: # %bb.0: 92; RV32-NEXT: andi a0, a0, 128 93; RV32-NEXT: seqz a0, a0 94; RV32-NEXT: li a1, 0 95; RV32-NEXT: ret 96; 97; RV64-LABEL: bittest_7_i64: 98; RV64: # %bb.0: 99; RV64-NEXT: andi a0, a0, 128 100; RV64-NEXT: seqz a0, a0 101; RV64-NEXT: ret 102 %shr = lshr i64 %a, 7 103 %not = xor i64 %shr, -1 104 %and = and i64 %not, 1 105 ret i64 %and 106} 107 108define i64 @bittest_10_i64(i64 %a) nounwind { 109; RV32-LABEL: bittest_10_i64: 110; RV32: # %bb.0: 111; RV32-NEXT: andi a0, a0, 1024 112; RV32-NEXT: seqz a0, a0 113; RV32-NEXT: li a1, 0 114; RV32-NEXT: ret 115; 116; RV64-LABEL: bittest_10_i64: 117; RV64: # %bb.0: 118; RV64-NEXT: andi a0, a0, 1024 119; RV64-NEXT: seqz a0, a0 120; RV64-NEXT: ret 121 %shr = lshr i64 %a, 10 122 %not = xor i64 %shr, -1 123 %and = and i64 %not, 1 124 ret i64 %and 125} 126 127define i64 @bittest_11_i64(i64 %a) nounwind { 128; RV32I-LABEL: bittest_11_i64: 129; RV32I: # %bb.0: 130; RV32I-NEXT: not a0, a0 131; RV32I-NEXT: slli a0, a0, 20 132; RV32I-NEXT: srli a0, a0, 31 133; RV32I-NEXT: li a1, 0 134; RV32I-NEXT: ret 135; 136; RV64I-LABEL: bittest_11_i64: 137; RV64I: # %bb.0: 138; RV64I-NEXT: not a0, a0 139; RV64I-NEXT: slli a0, a0, 52 140; RV64I-NEXT: srli a0, a0, 63 141; RV64I-NEXT: ret 142; 143; RV32ZBS-LABEL: bittest_11_i64: 144; RV32ZBS: # %bb.0: 145; RV32ZBS-NEXT: not a0, a0 146; RV32ZBS-NEXT: bexti a0, a0, 11 147; RV32ZBS-NEXT: li a1, 0 148; RV32ZBS-NEXT: ret 149; 150; RV64ZBS-LABEL: bittest_11_i64: 151; RV64ZBS: # %bb.0: 152; RV64ZBS-NEXT: not a0, a0 153; RV64ZBS-NEXT: bexti a0, a0, 11 154; RV64ZBS-NEXT: ret 155; 156; RV32XTHEADBS-LABEL: bittest_11_i64: 157; RV32XTHEADBS: # %bb.0: 158; RV32XTHEADBS-NEXT: not a0, a0 159; RV32XTHEADBS-NEXT: th.tst a0, a0, 11 160; RV32XTHEADBS-NEXT: li a1, 0 161; RV32XTHEADBS-NEXT: ret 162; 163; RV64XTHEADBS-LABEL: bittest_11_i64: 164; RV64XTHEADBS: # %bb.0: 165; RV64XTHEADBS-NEXT: not a0, a0 166; RV64XTHEADBS-NEXT: th.tst a0, a0, 11 167; RV64XTHEADBS-NEXT: ret 168 %shr = lshr i64 %a, 11 169 %not = xor i64 %shr, -1 170 %and = and i64 %not, 1 171 ret i64 %and 172} 173 174define i64 @bittest_31_i64(i64 %a) nounwind { 175; RV32-LABEL: bittest_31_i64: 176; RV32: # %bb.0: 177; RV32-NEXT: not a0, a0 178; RV32-NEXT: srli a0, a0, 31 179; RV32-NEXT: li a1, 0 180; RV32-NEXT: ret 181; 182; RV64I-LABEL: bittest_31_i64: 183; RV64I: # %bb.0: 184; RV64I-NEXT: not a0, a0 185; RV64I-NEXT: srliw a0, a0, 31 186; RV64I-NEXT: ret 187; 188; RV64ZBS-LABEL: bittest_31_i64: 189; RV64ZBS: # %bb.0: 190; RV64ZBS-NEXT: not a0, a0 191; RV64ZBS-NEXT: bexti a0, a0, 31 192; RV64ZBS-NEXT: ret 193; 194; RV64XTHEADBS-LABEL: bittest_31_i64: 195; RV64XTHEADBS: # %bb.0: 196; RV64XTHEADBS-NEXT: not a0, a0 197; RV64XTHEADBS-NEXT: th.tst a0, a0, 31 198; RV64XTHEADBS-NEXT: ret 199 %shr = lshr i64 %a, 31 200 %not = xor i64 %shr, -1 201 %and = and i64 %not, 1 202 ret i64 %and 203} 204 205define i64 @bittest_32_i64(i64 %a) nounwind { 206; RV32-LABEL: bittest_32_i64: 207; RV32: # %bb.0: 208; RV32-NEXT: not a0, a1 209; RV32-NEXT: andi a0, a0, 1 210; RV32-NEXT: li a1, 0 211; RV32-NEXT: ret 212; 213; RV64I-LABEL: bittest_32_i64: 214; RV64I: # %bb.0: 215; RV64I-NEXT: not a0, a0 216; RV64I-NEXT: slli a0, a0, 31 217; RV64I-NEXT: srli a0, a0, 63 218; RV64I-NEXT: ret 219; 220; RV64ZBS-LABEL: bittest_32_i64: 221; RV64ZBS: # %bb.0: 222; RV64ZBS-NEXT: not a0, a0 223; RV64ZBS-NEXT: bexti a0, a0, 32 224; RV64ZBS-NEXT: ret 225; 226; RV64XTHEADBS-LABEL: bittest_32_i64: 227; RV64XTHEADBS: # %bb.0: 228; RV64XTHEADBS-NEXT: not a0, a0 229; RV64XTHEADBS-NEXT: th.tst a0, a0, 32 230; RV64XTHEADBS-NEXT: ret 231 %shr = lshr i64 %a, 32 232 %not = xor i64 %shr, -1 233 %and = and i64 %not, 1 234 ret i64 %and 235} 236 237define i64 @bittest_63_i64(i64 %a) nounwind { 238; RV32-LABEL: bittest_63_i64: 239; RV32: # %bb.0: 240; RV32-NEXT: not a0, a1 241; RV32-NEXT: srli a0, a0, 31 242; RV32-NEXT: li a1, 0 243; RV32-NEXT: ret 244; 245; RV64-LABEL: bittest_63_i64: 246; RV64: # %bb.0: 247; RV64-NEXT: not a0, a0 248; RV64-NEXT: srli a0, a0, 63 249; RV64-NEXT: ret 250 %shr = lshr i64 %a, 63 251 %not = xor i64 %shr, -1 252 %and = and i64 %not, 1 253 ret i64 %and 254} 255 256; Make sure we use (andi (srl X, Y), 1) or bext. 257define i1 @bittest_constant_by_var_shr_i32(i32 signext %b) nounwind { 258; RV32I-LABEL: bittest_constant_by_var_shr_i32: 259; RV32I: # %bb.0: 260; RV32I-NEXT: lui a1, 301408 261; RV32I-NEXT: addi a1, a1, 722 262; RV32I-NEXT: srl a0, a1, a0 263; RV32I-NEXT: andi a0, a0, 1 264; RV32I-NEXT: ret 265; 266; RV64I-LABEL: bittest_constant_by_var_shr_i32: 267; RV64I: # %bb.0: 268; RV64I-NEXT: lui a1, 301408 269; RV64I-NEXT: addi a1, a1, 722 270; RV64I-NEXT: srlw a0, a1, a0 271; RV64I-NEXT: andi a0, a0, 1 272; RV64I-NEXT: ret 273; 274; RV32ZBS-LABEL: bittest_constant_by_var_shr_i32: 275; RV32ZBS: # %bb.0: 276; RV32ZBS-NEXT: lui a1, 301408 277; RV32ZBS-NEXT: addi a1, a1, 722 278; RV32ZBS-NEXT: bext a0, a1, a0 279; RV32ZBS-NEXT: ret 280; 281; RV64ZBS-LABEL: bittest_constant_by_var_shr_i32: 282; RV64ZBS: # %bb.0: 283; RV64ZBS-NEXT: lui a1, 301408 284; RV64ZBS-NEXT: addiw a1, a1, 722 285; RV64ZBS-NEXT: bext a0, a1, a0 286; RV64ZBS-NEXT: ret 287; 288; RV32XTHEADBS-LABEL: bittest_constant_by_var_shr_i32: 289; RV32XTHEADBS: # %bb.0: 290; RV32XTHEADBS-NEXT: lui a1, 301408 291; RV32XTHEADBS-NEXT: addi a1, a1, 722 292; RV32XTHEADBS-NEXT: srl a0, a1, a0 293; RV32XTHEADBS-NEXT: andi a0, a0, 1 294; RV32XTHEADBS-NEXT: ret 295; 296; RV64XTHEADBS-LABEL: bittest_constant_by_var_shr_i32: 297; RV64XTHEADBS: # %bb.0: 298; RV64XTHEADBS-NEXT: lui a1, 301408 299; RV64XTHEADBS-NEXT: addi a1, a1, 722 300; RV64XTHEADBS-NEXT: srlw a0, a1, a0 301; RV64XTHEADBS-NEXT: andi a0, a0, 1 302; RV64XTHEADBS-NEXT: ret 303 %shl = lshr i32 1234567890, %b 304 %and = and i32 %shl, 1 305 %cmp = icmp ne i32 %and, 0 306 ret i1 %cmp 307} 308 309; Make sure we use (andi (srl X, Y), 1) or bext. 310define i1 @bittest_constant_by_var_shl_i32(i32 signext %b) nounwind { 311; RV32I-LABEL: bittest_constant_by_var_shl_i32: 312; RV32I: # %bb.0: 313; RV32I-NEXT: lui a1, 301408 314; RV32I-NEXT: addi a1, a1, 722 315; RV32I-NEXT: srl a0, a1, a0 316; RV32I-NEXT: andi a0, a0, 1 317; RV32I-NEXT: ret 318; 319; RV64I-LABEL: bittest_constant_by_var_shl_i32: 320; RV64I: # %bb.0: 321; RV64I-NEXT: lui a1, 301408 322; RV64I-NEXT: addi a1, a1, 722 323; RV64I-NEXT: srlw a0, a1, a0 324; RV64I-NEXT: andi a0, a0, 1 325; RV64I-NEXT: ret 326; 327; RV32ZBS-LABEL: bittest_constant_by_var_shl_i32: 328; RV32ZBS: # %bb.0: 329; RV32ZBS-NEXT: lui a1, 301408 330; RV32ZBS-NEXT: addi a1, a1, 722 331; RV32ZBS-NEXT: bext a0, a1, a0 332; RV32ZBS-NEXT: ret 333; 334; RV64ZBS-LABEL: bittest_constant_by_var_shl_i32: 335; RV64ZBS: # %bb.0: 336; RV64ZBS-NEXT: lui a1, 301408 337; RV64ZBS-NEXT: addiw a1, a1, 722 338; RV64ZBS-NEXT: bext a0, a1, a0 339; RV64ZBS-NEXT: ret 340; 341; RV32XTHEADBS-LABEL: bittest_constant_by_var_shl_i32: 342; RV32XTHEADBS: # %bb.0: 343; RV32XTHEADBS-NEXT: lui a1, 301408 344; RV32XTHEADBS-NEXT: addi a1, a1, 722 345; RV32XTHEADBS-NEXT: srl a0, a1, a0 346; RV32XTHEADBS-NEXT: andi a0, a0, 1 347; RV32XTHEADBS-NEXT: ret 348; 349; RV64XTHEADBS-LABEL: bittest_constant_by_var_shl_i32: 350; RV64XTHEADBS: # %bb.0: 351; RV64XTHEADBS-NEXT: lui a1, 301408 352; RV64XTHEADBS-NEXT: addi a1, a1, 722 353; RV64XTHEADBS-NEXT: srlw a0, a1, a0 354; RV64XTHEADBS-NEXT: andi a0, a0, 1 355; RV64XTHEADBS-NEXT: ret 356 %shl = shl i32 1, %b 357 %and = and i32 %shl, 1234567890 358 %cmp = icmp ne i32 %and, 0 359 ret i1 %cmp 360} 361 362; Make sure we use (andi (srl X, Y), 1) or bext. 363define i1 @bittest_constant_by_var_shr_i64(i64 %b) nounwind { 364; RV32-LABEL: bittest_constant_by_var_shr_i64: 365; RV32: # %bb.0: 366; RV32-NEXT: lui a1, 301408 367; RV32-NEXT: addi a1, a1, 722 368; RV32-NEXT: srl a1, a1, a0 369; RV32-NEXT: addi a0, a0, -32 370; RV32-NEXT: srli a0, a0, 31 371; RV32-NEXT: and a0, a0, a1 372; RV32-NEXT: ret 373; 374; RV64I-LABEL: bittest_constant_by_var_shr_i64: 375; RV64I: # %bb.0: 376; RV64I-NEXT: lui a1, 301408 377; RV64I-NEXT: addiw a1, a1, 722 378; RV64I-NEXT: srl a0, a1, a0 379; RV64I-NEXT: andi a0, a0, 1 380; RV64I-NEXT: ret 381; 382; RV64ZBS-LABEL: bittest_constant_by_var_shr_i64: 383; RV64ZBS: # %bb.0: 384; RV64ZBS-NEXT: lui a1, 301408 385; RV64ZBS-NEXT: addiw a1, a1, 722 386; RV64ZBS-NEXT: bext a0, a1, a0 387; RV64ZBS-NEXT: ret 388; 389; RV64XTHEADBS-LABEL: bittest_constant_by_var_shr_i64: 390; RV64XTHEADBS: # %bb.0: 391; RV64XTHEADBS-NEXT: lui a1, 301408 392; RV64XTHEADBS-NEXT: addiw a1, a1, 722 393; RV64XTHEADBS-NEXT: srl a0, a1, a0 394; RV64XTHEADBS-NEXT: andi a0, a0, 1 395; RV64XTHEADBS-NEXT: ret 396 %shl = lshr i64 1234567890, %b 397 %and = and i64 %shl, 1 398 %cmp = icmp ne i64 %and, 0 399 ret i1 %cmp 400} 401 402; Make sure we use (andi (srl X, Y), 1) or bext. 403define i1 @bittest_constant_by_var_shl_i64(i64 %b) nounwind { 404; RV32-LABEL: bittest_constant_by_var_shl_i64: 405; RV32: # %bb.0: 406; RV32-NEXT: lui a1, 301408 407; RV32-NEXT: addi a1, a1, 722 408; RV32-NEXT: srl a1, a1, a0 409; RV32-NEXT: addi a0, a0, -32 410; RV32-NEXT: srli a0, a0, 31 411; RV32-NEXT: and a0, a0, a1 412; RV32-NEXT: ret 413; 414; RV64I-LABEL: bittest_constant_by_var_shl_i64: 415; RV64I: # %bb.0: 416; RV64I-NEXT: lui a1, 301408 417; RV64I-NEXT: addiw a1, a1, 722 418; RV64I-NEXT: srl a0, a1, a0 419; RV64I-NEXT: andi a0, a0, 1 420; RV64I-NEXT: ret 421; 422; RV64ZBS-LABEL: bittest_constant_by_var_shl_i64: 423; RV64ZBS: # %bb.0: 424; RV64ZBS-NEXT: lui a1, 301408 425; RV64ZBS-NEXT: addiw a1, a1, 722 426; RV64ZBS-NEXT: bext a0, a1, a0 427; RV64ZBS-NEXT: ret 428; 429; RV64XTHEADBS-LABEL: bittest_constant_by_var_shl_i64: 430; RV64XTHEADBS: # %bb.0: 431; RV64XTHEADBS-NEXT: lui a1, 301408 432; RV64XTHEADBS-NEXT: addiw a1, a1, 722 433; RV64XTHEADBS-NEXT: srl a0, a1, a0 434; RV64XTHEADBS-NEXT: andi a0, a0, 1 435; RV64XTHEADBS-NEXT: ret 436 %shl = shl i64 1, %b 437 %and = and i64 %shl, 1234567890 438 %cmp = icmp ne i64 %and, 0 439 ret i1 %cmp 440} 441 442; We want to use (andi (srl X, Y), 1) or bext before the beqz. 443define void @bittest_switch(i32 signext %0) { 444; RV32I-LABEL: bittest_switch: 445; RV32I: # %bb.0: 446; RV32I-NEXT: li a1, 31 447; RV32I-NEXT: bltu a1, a0, .LBB14_3 448; RV32I-NEXT: # %bb.1: 449; RV32I-NEXT: lui a1, 524291 450; RV32I-NEXT: addi a1, a1, 768 451; RV32I-NEXT: srl a0, a1, a0 452; RV32I-NEXT: andi a0, a0, 1 453; RV32I-NEXT: beqz a0, .LBB14_3 454; RV32I-NEXT: # %bb.2: 455; RV32I-NEXT: tail bar 456; RV32I-NEXT: .LBB14_3: 457; RV32I-NEXT: ret 458; 459; RV64I-LABEL: bittest_switch: 460; RV64I: # %bb.0: 461; RV64I-NEXT: li a1, 31 462; RV64I-NEXT: bltu a1, a0, .LBB14_3 463; RV64I-NEXT: # %bb.1: 464; RV64I-NEXT: lui a1, 2048 465; RV64I-NEXT: addiw a1, a1, 51 466; RV64I-NEXT: slli a1, a1, 8 467; RV64I-NEXT: srl a0, a1, a0 468; RV64I-NEXT: andi a0, a0, 1 469; RV64I-NEXT: beqz a0, .LBB14_3 470; RV64I-NEXT: # %bb.2: 471; RV64I-NEXT: tail bar 472; RV64I-NEXT: .LBB14_3: 473; RV64I-NEXT: ret 474; 475; RV32ZBS-LABEL: bittest_switch: 476; RV32ZBS: # %bb.0: 477; RV32ZBS-NEXT: li a1, 31 478; RV32ZBS-NEXT: bltu a1, a0, .LBB14_3 479; RV32ZBS-NEXT: # %bb.1: 480; RV32ZBS-NEXT: lui a1, 524291 481; RV32ZBS-NEXT: addi a1, a1, 768 482; RV32ZBS-NEXT: bext a0, a1, a0 483; RV32ZBS-NEXT: beqz a0, .LBB14_3 484; RV32ZBS-NEXT: # %bb.2: 485; RV32ZBS-NEXT: tail bar 486; RV32ZBS-NEXT: .LBB14_3: 487; RV32ZBS-NEXT: ret 488; 489; RV64ZBS-LABEL: bittest_switch: 490; RV64ZBS: # %bb.0: 491; RV64ZBS-NEXT: li a1, 31 492; RV64ZBS-NEXT: bltu a1, a0, .LBB14_3 493; RV64ZBS-NEXT: # %bb.1: 494; RV64ZBS-NEXT: lui a1, 2048 495; RV64ZBS-NEXT: addiw a1, a1, 51 496; RV64ZBS-NEXT: slli a1, a1, 8 497; RV64ZBS-NEXT: bext a0, a1, a0 498; RV64ZBS-NEXT: beqz a0, .LBB14_3 499; RV64ZBS-NEXT: # %bb.2: 500; RV64ZBS-NEXT: tail bar 501; RV64ZBS-NEXT: .LBB14_3: 502; RV64ZBS-NEXT: ret 503; 504; RV32XTHEADBS-LABEL: bittest_switch: 505; RV32XTHEADBS: # %bb.0: 506; RV32XTHEADBS-NEXT: li a1, 31 507; RV32XTHEADBS-NEXT: bltu a1, a0, .LBB14_3 508; RV32XTHEADBS-NEXT: # %bb.1: 509; RV32XTHEADBS-NEXT: lui a1, 524291 510; RV32XTHEADBS-NEXT: addi a1, a1, 768 511; RV32XTHEADBS-NEXT: srl a0, a1, a0 512; RV32XTHEADBS-NEXT: andi a0, a0, 1 513; RV32XTHEADBS-NEXT: beqz a0, .LBB14_3 514; RV32XTHEADBS-NEXT: # %bb.2: 515; RV32XTHEADBS-NEXT: tail bar 516; RV32XTHEADBS-NEXT: .LBB14_3: 517; RV32XTHEADBS-NEXT: ret 518; 519; RV64XTHEADBS-LABEL: bittest_switch: 520; RV64XTHEADBS: # %bb.0: 521; RV64XTHEADBS-NEXT: li a1, 31 522; RV64XTHEADBS-NEXT: bltu a1, a0, .LBB14_3 523; RV64XTHEADBS-NEXT: # %bb.1: 524; RV64XTHEADBS-NEXT: lui a1, 2048 525; RV64XTHEADBS-NEXT: addiw a1, a1, 51 526; RV64XTHEADBS-NEXT: slli a1, a1, 8 527; RV64XTHEADBS-NEXT: srl a0, a1, a0 528; RV64XTHEADBS-NEXT: andi a0, a0, 1 529; RV64XTHEADBS-NEXT: beqz a0, .LBB14_3 530; RV64XTHEADBS-NEXT: # %bb.2: 531; RV64XTHEADBS-NEXT: tail bar 532; RV64XTHEADBS-NEXT: .LBB14_3: 533; RV64XTHEADBS-NEXT: ret 534 switch i32 %0, label %3 [ 535 i32 8, label %2 536 i32 9, label %2 537 i32 12, label %2 538 i32 13, label %2 539 i32 31, label %2 540 ] 541 5422: 543 tail call void @bar() 544 br label %3 545 5463: 547 ret void 548} 549 550declare void @bar() 551 552define signext i32 @bit_10_z_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 553; CHECK-LABEL: bit_10_z_select_i32: 554; CHECK: # %bb.0: 555; CHECK-NEXT: andi a3, a0, 1024 556; CHECK-NEXT: mv a0, a1 557; CHECK-NEXT: beqz a3, .LBB15_2 558; CHECK-NEXT: # %bb.1: 559; CHECK-NEXT: mv a0, a2 560; CHECK-NEXT: .LBB15_2: 561; CHECK-NEXT: ret 562 %1 = and i32 %a, 1024 563 %2 = icmp eq i32 %1, 0 564 %3 = select i1 %2, i32 %b, i32 %c 565 ret i32 %3 566} 567 568define signext i32 @bit_10_nz_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 569; RV32-LABEL: bit_10_nz_select_i32: 570; RV32: # %bb.0: 571; RV32-NEXT: slli a3, a0, 21 572; RV32-NEXT: mv a0, a1 573; RV32-NEXT: bltz a3, .LBB16_2 574; RV32-NEXT: # %bb.1: 575; RV32-NEXT: mv a0, a2 576; RV32-NEXT: .LBB16_2: 577; RV32-NEXT: ret 578; 579; RV64-LABEL: bit_10_nz_select_i32: 580; RV64: # %bb.0: 581; RV64-NEXT: slli a3, a0, 53 582; RV64-NEXT: mv a0, a1 583; RV64-NEXT: bltz a3, .LBB16_2 584; RV64-NEXT: # %bb.1: 585; RV64-NEXT: mv a0, a2 586; RV64-NEXT: .LBB16_2: 587; RV64-NEXT: ret 588 %1 = and i32 %a, 1024 589 %2 = icmp ne i32 %1, 0 590 %3 = select i1 %2, i32 %b, i32 %c 591 ret i32 %3 592} 593 594define signext i32 @bit_11_z_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 595; RV32-LABEL: bit_11_z_select_i32: 596; RV32: # %bb.0: 597; RV32-NEXT: slli a3, a0, 20 598; RV32-NEXT: mv a0, a1 599; RV32-NEXT: bgez a3, .LBB17_2 600; RV32-NEXT: # %bb.1: 601; RV32-NEXT: mv a0, a2 602; RV32-NEXT: .LBB17_2: 603; RV32-NEXT: ret 604; 605; RV64-LABEL: bit_11_z_select_i32: 606; RV64: # %bb.0: 607; RV64-NEXT: slli a3, a0, 52 608; RV64-NEXT: mv a0, a1 609; RV64-NEXT: bgez a3, .LBB17_2 610; RV64-NEXT: # %bb.1: 611; RV64-NEXT: mv a0, a2 612; RV64-NEXT: .LBB17_2: 613; RV64-NEXT: ret 614 %1 = and i32 %a, 2048 615 %2 = icmp eq i32 %1, 0 616 %3 = select i1 %2, i32 %b, i32 %c 617 ret i32 %3 618} 619 620define signext i32 @bit_11_nz_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 621; RV32-LABEL: bit_11_nz_select_i32: 622; RV32: # %bb.0: 623; RV32-NEXT: slli a3, a0, 20 624; RV32-NEXT: mv a0, a1 625; RV32-NEXT: bltz a3, .LBB18_2 626; RV32-NEXT: # %bb.1: 627; RV32-NEXT: mv a0, a2 628; RV32-NEXT: .LBB18_2: 629; RV32-NEXT: ret 630; 631; RV64-LABEL: bit_11_nz_select_i32: 632; RV64: # %bb.0: 633; RV64-NEXT: slli a3, a0, 52 634; RV64-NEXT: mv a0, a1 635; RV64-NEXT: bltz a3, .LBB18_2 636; RV64-NEXT: # %bb.1: 637; RV64-NEXT: mv a0, a2 638; RV64-NEXT: .LBB18_2: 639; RV64-NEXT: ret 640 %1 = and i32 %a, 2048 641 %2 = icmp ne i32 %1, 0 642 %3 = select i1 %2, i32 %b, i32 %c 643 ret i32 %3 644} 645 646define signext i32 @bit_20_z_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 647; RV32-LABEL: bit_20_z_select_i32: 648; RV32: # %bb.0: 649; RV32-NEXT: slli a3, a0, 11 650; RV32-NEXT: mv a0, a1 651; RV32-NEXT: bgez a3, .LBB19_2 652; RV32-NEXT: # %bb.1: 653; RV32-NEXT: mv a0, a2 654; RV32-NEXT: .LBB19_2: 655; RV32-NEXT: ret 656; 657; RV64-LABEL: bit_20_z_select_i32: 658; RV64: # %bb.0: 659; RV64-NEXT: slli a3, a0, 43 660; RV64-NEXT: mv a0, a1 661; RV64-NEXT: bgez a3, .LBB19_2 662; RV64-NEXT: # %bb.1: 663; RV64-NEXT: mv a0, a2 664; RV64-NEXT: .LBB19_2: 665; RV64-NEXT: ret 666 %1 = and i32 %a, 1048576 667 %2 = icmp eq i32 %1, 0 668 %3 = select i1 %2, i32 %b, i32 %c 669 ret i32 %3 670} 671 672define signext i32 @bit_20_nz_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 673; RV32-LABEL: bit_20_nz_select_i32: 674; RV32: # %bb.0: 675; RV32-NEXT: slli a3, a0, 11 676; RV32-NEXT: mv a0, a1 677; RV32-NEXT: bltz a3, .LBB20_2 678; RV32-NEXT: # %bb.1: 679; RV32-NEXT: mv a0, a2 680; RV32-NEXT: .LBB20_2: 681; RV32-NEXT: ret 682; 683; RV64-LABEL: bit_20_nz_select_i32: 684; RV64: # %bb.0: 685; RV64-NEXT: slli a3, a0, 43 686; RV64-NEXT: mv a0, a1 687; RV64-NEXT: bltz a3, .LBB20_2 688; RV64-NEXT: # %bb.1: 689; RV64-NEXT: mv a0, a2 690; RV64-NEXT: .LBB20_2: 691; RV64-NEXT: ret 692 %1 = and i32 %a, 1048576 693 %2 = icmp ne i32 %1, 0 694 %3 = select i1 %2, i32 %b, i32 %c 695 ret i32 %3 696} 697 698define signext i32 @bit_31_z_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 699; RV32-LABEL: bit_31_z_select_i32: 700; RV32: # %bb.0: 701; RV32-NEXT: bgez a0, .LBB21_2 702; RV32-NEXT: # %bb.1: 703; RV32-NEXT: mv a1, a2 704; RV32-NEXT: .LBB21_2: 705; RV32-NEXT: mv a0, a1 706; RV32-NEXT: ret 707; 708; RV64-LABEL: bit_31_z_select_i32: 709; RV64: # %bb.0: 710; RV64-NEXT: lui a3, 524288 711; RV64-NEXT: and a3, a0, a3 712; RV64-NEXT: mv a0, a1 713; RV64-NEXT: beqz a3, .LBB21_2 714; RV64-NEXT: # %bb.1: 715; RV64-NEXT: mv a0, a2 716; RV64-NEXT: .LBB21_2: 717; RV64-NEXT: ret 718 %1 = and i32 %a, 2147483648 719 %2 = icmp eq i32 %1, 0 720 %3 = select i1 %2, i32 %b, i32 %c 721 ret i32 %3 722} 723 724define signext i32 @bit_31_nz_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 725; RV32-LABEL: bit_31_nz_select_i32: 726; RV32: # %bb.0: 727; RV32-NEXT: srli a3, a0, 31 728; RV32-NEXT: mv a0, a1 729; RV32-NEXT: bnez a3, .LBB22_2 730; RV32-NEXT: # %bb.1: 731; RV32-NEXT: mv a0, a2 732; RV32-NEXT: .LBB22_2: 733; RV32-NEXT: ret 734; 735; RV64-LABEL: bit_31_nz_select_i32: 736; RV64: # %bb.0: 737; RV64-NEXT: lui a3, 524288 738; RV64-NEXT: and a3, a0, a3 739; RV64-NEXT: mv a0, a1 740; RV64-NEXT: bnez a3, .LBB22_2 741; RV64-NEXT: # %bb.1: 742; RV64-NEXT: mv a0, a2 743; RV64-NEXT: .LBB22_2: 744; RV64-NEXT: ret 745 %1 = and i32 %a, 2147483648 746 %2 = icmp ne i32 %1, 0 747 %3 = select i1 %2, i32 %b, i32 %c 748 ret i32 %3 749} 750 751define i64 @bit_10_z_select_i64(i64 %a, i64 %b, i64 %c) { 752; RV32-LABEL: bit_10_z_select_i64: 753; RV32: # %bb.0: 754; RV32-NEXT: mv a1, a3 755; RV32-NEXT: andi a3, a0, 1024 756; RV32-NEXT: mv a0, a2 757; RV32-NEXT: beqz a3, .LBB23_2 758; RV32-NEXT: # %bb.1: 759; RV32-NEXT: mv a0, a4 760; RV32-NEXT: mv a1, a5 761; RV32-NEXT: .LBB23_2: 762; RV32-NEXT: ret 763; 764; RV64-LABEL: bit_10_z_select_i64: 765; RV64: # %bb.0: 766; RV64-NEXT: andi a3, a0, 1024 767; RV64-NEXT: mv a0, a1 768; RV64-NEXT: beqz a3, .LBB23_2 769; RV64-NEXT: # %bb.1: 770; RV64-NEXT: mv a0, a2 771; RV64-NEXT: .LBB23_2: 772; RV64-NEXT: ret 773 %1 = and i64 %a, 1024 774 %2 = icmp eq i64 %1, 0 775 %3 = select i1 %2, i64 %b, i64 %c 776 ret i64 %3 777} 778 779define i64 @bit_10_nz_select_i64(i64 %a, i64 %b, i64 %c) { 780; RV32I-LABEL: bit_10_nz_select_i64: 781; RV32I: # %bb.0: 782; RV32I-NEXT: mv a1, a3 783; RV32I-NEXT: slli a0, a0, 21 784; RV32I-NEXT: srli a3, a0, 31 785; RV32I-NEXT: mv a0, a2 786; RV32I-NEXT: bnez a3, .LBB24_2 787; RV32I-NEXT: # %bb.1: 788; RV32I-NEXT: mv a0, a4 789; RV32I-NEXT: mv a1, a5 790; RV32I-NEXT: .LBB24_2: 791; RV32I-NEXT: ret 792; 793; RV64-LABEL: bit_10_nz_select_i64: 794; RV64: # %bb.0: 795; RV64-NEXT: slli a3, a0, 53 796; RV64-NEXT: mv a0, a1 797; RV64-NEXT: bltz a3, .LBB24_2 798; RV64-NEXT: # %bb.1: 799; RV64-NEXT: mv a0, a2 800; RV64-NEXT: .LBB24_2: 801; RV64-NEXT: ret 802; 803; RV32ZBS-LABEL: bit_10_nz_select_i64: 804; RV32ZBS: # %bb.0: 805; RV32ZBS-NEXT: mv a1, a3 806; RV32ZBS-NEXT: bexti a3, a0, 10 807; RV32ZBS-NEXT: mv a0, a2 808; RV32ZBS-NEXT: bnez a3, .LBB24_2 809; RV32ZBS-NEXT: # %bb.1: 810; RV32ZBS-NEXT: mv a0, a4 811; RV32ZBS-NEXT: mv a1, a5 812; RV32ZBS-NEXT: .LBB24_2: 813; RV32ZBS-NEXT: ret 814; 815; RV32XTHEADBS-LABEL: bit_10_nz_select_i64: 816; RV32XTHEADBS: # %bb.0: 817; RV32XTHEADBS-NEXT: mv a1, a3 818; RV32XTHEADBS-NEXT: th.tst a3, a0, 10 819; RV32XTHEADBS-NEXT: mv a0, a2 820; RV32XTHEADBS-NEXT: bnez a3, .LBB24_2 821; RV32XTHEADBS-NEXT: # %bb.1: 822; RV32XTHEADBS-NEXT: mv a0, a4 823; RV32XTHEADBS-NEXT: mv a1, a5 824; RV32XTHEADBS-NEXT: .LBB24_2: 825; RV32XTHEADBS-NEXT: ret 826 %1 = and i64 %a, 1024 827 %2 = icmp ne i64 %1, 0 828 %3 = select i1 %2, i64 %b, i64 %c 829 ret i64 %3 830} 831 832define i64 @bit_11_z_select_i64(i64 %a, i64 %b, i64 %c) { 833; RV32-LABEL: bit_11_z_select_i64: 834; RV32: # %bb.0: 835; RV32-NEXT: mv a1, a3 836; RV32-NEXT: slli a3, a0, 20 837; RV32-NEXT: mv a0, a2 838; RV32-NEXT: bgez a3, .LBB25_2 839; RV32-NEXT: # %bb.1: 840; RV32-NEXT: mv a0, a4 841; RV32-NEXT: mv a1, a5 842; RV32-NEXT: .LBB25_2: 843; RV32-NEXT: ret 844; 845; RV64-LABEL: bit_11_z_select_i64: 846; RV64: # %bb.0: 847; RV64-NEXT: slli a3, a0, 52 848; RV64-NEXT: mv a0, a1 849; RV64-NEXT: bgez a3, .LBB25_2 850; RV64-NEXT: # %bb.1: 851; RV64-NEXT: mv a0, a2 852; RV64-NEXT: .LBB25_2: 853; RV64-NEXT: ret 854 %1 = and i64 %a, 2048 855 %2 = icmp eq i64 %1, 0 856 %3 = select i1 %2, i64 %b, i64 %c 857 ret i64 %3 858} 859 860define i64 @bit_11_nz_select_i64(i64 %a, i64 %b, i64 %c) { 861; RV32I-LABEL: bit_11_nz_select_i64: 862; RV32I: # %bb.0: 863; RV32I-NEXT: mv a1, a3 864; RV32I-NEXT: slli a0, a0, 20 865; RV32I-NEXT: srli a3, a0, 31 866; RV32I-NEXT: mv a0, a2 867; RV32I-NEXT: bnez a3, .LBB26_2 868; RV32I-NEXT: # %bb.1: 869; RV32I-NEXT: mv a0, a4 870; RV32I-NEXT: mv a1, a5 871; RV32I-NEXT: .LBB26_2: 872; RV32I-NEXT: ret 873; 874; RV64-LABEL: bit_11_nz_select_i64: 875; RV64: # %bb.0: 876; RV64-NEXT: slli a3, a0, 52 877; RV64-NEXT: mv a0, a1 878; RV64-NEXT: bltz a3, .LBB26_2 879; RV64-NEXT: # %bb.1: 880; RV64-NEXT: mv a0, a2 881; RV64-NEXT: .LBB26_2: 882; RV64-NEXT: ret 883; 884; RV32ZBS-LABEL: bit_11_nz_select_i64: 885; RV32ZBS: # %bb.0: 886; RV32ZBS-NEXT: mv a1, a3 887; RV32ZBS-NEXT: bexti a3, a0, 11 888; RV32ZBS-NEXT: mv a0, a2 889; RV32ZBS-NEXT: bnez a3, .LBB26_2 890; RV32ZBS-NEXT: # %bb.1: 891; RV32ZBS-NEXT: mv a0, a4 892; RV32ZBS-NEXT: mv a1, a5 893; RV32ZBS-NEXT: .LBB26_2: 894; RV32ZBS-NEXT: ret 895; 896; RV32XTHEADBS-LABEL: bit_11_nz_select_i64: 897; RV32XTHEADBS: # %bb.0: 898; RV32XTHEADBS-NEXT: mv a1, a3 899; RV32XTHEADBS-NEXT: th.tst a3, a0, 11 900; RV32XTHEADBS-NEXT: mv a0, a2 901; RV32XTHEADBS-NEXT: bnez a3, .LBB26_2 902; RV32XTHEADBS-NEXT: # %bb.1: 903; RV32XTHEADBS-NEXT: mv a0, a4 904; RV32XTHEADBS-NEXT: mv a1, a5 905; RV32XTHEADBS-NEXT: .LBB26_2: 906; RV32XTHEADBS-NEXT: ret 907 %1 = and i64 %a, 2048 908 %2 = icmp ne i64 %1, 0 909 %3 = select i1 %2, i64 %b, i64 %c 910 ret i64 %3 911} 912 913define i64 @bit_20_z_select_i64(i64 %a, i64 %b, i64 %c) { 914; RV32-LABEL: bit_20_z_select_i64: 915; RV32: # %bb.0: 916; RV32-NEXT: mv a1, a3 917; RV32-NEXT: slli a3, a0, 11 918; RV32-NEXT: mv a0, a2 919; RV32-NEXT: bgez a3, .LBB27_2 920; RV32-NEXT: # %bb.1: 921; RV32-NEXT: mv a0, a4 922; RV32-NEXT: mv a1, a5 923; RV32-NEXT: .LBB27_2: 924; RV32-NEXT: ret 925; 926; RV64-LABEL: bit_20_z_select_i64: 927; RV64: # %bb.0: 928; RV64-NEXT: slli a3, a0, 43 929; RV64-NEXT: mv a0, a1 930; RV64-NEXT: bgez a3, .LBB27_2 931; RV64-NEXT: # %bb.1: 932; RV64-NEXT: mv a0, a2 933; RV64-NEXT: .LBB27_2: 934; RV64-NEXT: ret 935 %1 = and i64 %a, 1048576 936 %2 = icmp eq i64 %1, 0 937 %3 = select i1 %2, i64 %b, i64 %c 938 ret i64 %3 939} 940 941define i64 @bit_20_nz_select_i64(i64 %a, i64 %b, i64 %c) { 942; RV32I-LABEL: bit_20_nz_select_i64: 943; RV32I: # %bb.0: 944; RV32I-NEXT: mv a1, a3 945; RV32I-NEXT: slli a0, a0, 11 946; RV32I-NEXT: srli a3, a0, 31 947; RV32I-NEXT: mv a0, a2 948; RV32I-NEXT: bnez a3, .LBB28_2 949; RV32I-NEXT: # %bb.1: 950; RV32I-NEXT: mv a0, a4 951; RV32I-NEXT: mv a1, a5 952; RV32I-NEXT: .LBB28_2: 953; RV32I-NEXT: ret 954; 955; RV64-LABEL: bit_20_nz_select_i64: 956; RV64: # %bb.0: 957; RV64-NEXT: slli a3, a0, 43 958; RV64-NEXT: mv a0, a1 959; RV64-NEXT: bltz a3, .LBB28_2 960; RV64-NEXT: # %bb.1: 961; RV64-NEXT: mv a0, a2 962; RV64-NEXT: .LBB28_2: 963; RV64-NEXT: ret 964; 965; RV32ZBS-LABEL: bit_20_nz_select_i64: 966; RV32ZBS: # %bb.0: 967; RV32ZBS-NEXT: mv a1, a3 968; RV32ZBS-NEXT: bexti a3, a0, 20 969; RV32ZBS-NEXT: mv a0, a2 970; RV32ZBS-NEXT: bnez a3, .LBB28_2 971; RV32ZBS-NEXT: # %bb.1: 972; RV32ZBS-NEXT: mv a0, a4 973; RV32ZBS-NEXT: mv a1, a5 974; RV32ZBS-NEXT: .LBB28_2: 975; RV32ZBS-NEXT: ret 976; 977; RV32XTHEADBS-LABEL: bit_20_nz_select_i64: 978; RV32XTHEADBS: # %bb.0: 979; RV32XTHEADBS-NEXT: mv a1, a3 980; RV32XTHEADBS-NEXT: th.tst a3, a0, 20 981; RV32XTHEADBS-NEXT: mv a0, a2 982; RV32XTHEADBS-NEXT: bnez a3, .LBB28_2 983; RV32XTHEADBS-NEXT: # %bb.1: 984; RV32XTHEADBS-NEXT: mv a0, a4 985; RV32XTHEADBS-NEXT: mv a1, a5 986; RV32XTHEADBS-NEXT: .LBB28_2: 987; RV32XTHEADBS-NEXT: ret 988 %1 = and i64 %a, 1048576 989 %2 = icmp ne i64 %1, 0 990 %3 = select i1 %2, i64 %b, i64 %c 991 ret i64 %3 992} 993 994define i64 @bit_31_z_select_i64(i64 %a, i64 %b, i64 %c) { 995; RV32-LABEL: bit_31_z_select_i64: 996; RV32: # %bb.0: 997; RV32-NEXT: mv a1, a3 998; RV32-NEXT: bgez a0, .LBB29_2 999; RV32-NEXT: # %bb.1: 1000; RV32-NEXT: mv a2, a4 1001; RV32-NEXT: mv a1, a5 1002; RV32-NEXT: .LBB29_2: 1003; RV32-NEXT: mv a0, a2 1004; RV32-NEXT: ret 1005; 1006; RV64-LABEL: bit_31_z_select_i64: 1007; RV64: # %bb.0: 1008; RV64-NEXT: slli a3, a0, 32 1009; RV64-NEXT: mv a0, a1 1010; RV64-NEXT: bgez a3, .LBB29_2 1011; RV64-NEXT: # %bb.1: 1012; RV64-NEXT: mv a0, a2 1013; RV64-NEXT: .LBB29_2: 1014; RV64-NEXT: ret 1015 %1 = and i64 %a, 2147483648 1016 %2 = icmp eq i64 %1, 0 1017 %3 = select i1 %2, i64 %b, i64 %c 1018 ret i64 %3 1019} 1020 1021define i64 @bit_31_nz_select_i64(i64 %a, i64 %b, i64 %c) { 1022; RV32-LABEL: bit_31_nz_select_i64: 1023; RV32: # %bb.0: 1024; RV32-NEXT: mv a1, a3 1025; RV32-NEXT: srli a3, a0, 31 1026; RV32-NEXT: mv a0, a2 1027; RV32-NEXT: bnez a3, .LBB30_2 1028; RV32-NEXT: # %bb.1: 1029; RV32-NEXT: mv a0, a4 1030; RV32-NEXT: mv a1, a5 1031; RV32-NEXT: .LBB30_2: 1032; RV32-NEXT: ret 1033; 1034; RV64-LABEL: bit_31_nz_select_i64: 1035; RV64: # %bb.0: 1036; RV64-NEXT: slli a3, a0, 32 1037; RV64-NEXT: mv a0, a1 1038; RV64-NEXT: bltz a3, .LBB30_2 1039; RV64-NEXT: # %bb.1: 1040; RV64-NEXT: mv a0, a2 1041; RV64-NEXT: .LBB30_2: 1042; RV64-NEXT: ret 1043 %1 = and i64 %a, 2147483648 1044 %2 = icmp ne i64 %1, 0 1045 %3 = select i1 %2, i64 %b, i64 %c 1046 ret i64 %3 1047} 1048 1049define i64 @bit_32_z_select_i64(i64 %a, i64 %b, i64 %c) { 1050; RV32-LABEL: bit_32_z_select_i64: 1051; RV32: # %bb.0: 1052; RV32-NEXT: andi a1, a1, 1 1053; RV32-NEXT: mv a0, a2 1054; RV32-NEXT: beqz a1, .LBB31_2 1055; RV32-NEXT: # %bb.1: 1056; RV32-NEXT: mv a0, a4 1057; RV32-NEXT: mv a3, a5 1058; RV32-NEXT: .LBB31_2: 1059; RV32-NEXT: mv a1, a3 1060; RV32-NEXT: ret 1061; 1062; RV64-LABEL: bit_32_z_select_i64: 1063; RV64: # %bb.0: 1064; RV64-NEXT: slli a3, a0, 31 1065; RV64-NEXT: mv a0, a1 1066; RV64-NEXT: bgez a3, .LBB31_2 1067; RV64-NEXT: # %bb.1: 1068; RV64-NEXT: mv a0, a2 1069; RV64-NEXT: .LBB31_2: 1070; RV64-NEXT: ret 1071 %1 = and i64 %a, 4294967296 1072 %2 = icmp eq i64 %1, 0 1073 %3 = select i1 %2, i64 %b, i64 %c 1074 ret i64 %3 1075} 1076 1077define i64 @bit_32_nz_select_i64(i64 %a, i64 %b, i64 %c) { 1078; RV32-LABEL: bit_32_nz_select_i64: 1079; RV32: # %bb.0: 1080; RV32-NEXT: andi a1, a1, 1 1081; RV32-NEXT: mv a0, a2 1082; RV32-NEXT: bnez a1, .LBB32_2 1083; RV32-NEXT: # %bb.1: 1084; RV32-NEXT: mv a0, a4 1085; RV32-NEXT: mv a3, a5 1086; RV32-NEXT: .LBB32_2: 1087; RV32-NEXT: mv a1, a3 1088; RV32-NEXT: ret 1089; 1090; RV64-LABEL: bit_32_nz_select_i64: 1091; RV64: # %bb.0: 1092; RV64-NEXT: slli a3, a0, 31 1093; RV64-NEXT: mv a0, a1 1094; RV64-NEXT: bltz a3, .LBB32_2 1095; RV64-NEXT: # %bb.1: 1096; RV64-NEXT: mv a0, a2 1097; RV64-NEXT: .LBB32_2: 1098; RV64-NEXT: ret 1099 %1 = and i64 %a, 4294967296 1100 %2 = icmp ne i64 %1, 0 1101 %3 = select i1 %2, i64 %b, i64 %c 1102 ret i64 %3 1103} 1104 1105define i64 @bit_55_z_select_i64(i64 %a, i64 %b, i64 %c) { 1106; RV32-LABEL: bit_55_z_select_i64: 1107; RV32: # %bb.0: 1108; RV32-NEXT: slli a1, a1, 8 1109; RV32-NEXT: mv a0, a2 1110; RV32-NEXT: bgez a1, .LBB33_2 1111; RV32-NEXT: # %bb.1: 1112; RV32-NEXT: mv a0, a4 1113; RV32-NEXT: mv a3, a5 1114; RV32-NEXT: .LBB33_2: 1115; RV32-NEXT: mv a1, a3 1116; RV32-NEXT: ret 1117; 1118; RV64-LABEL: bit_55_z_select_i64: 1119; RV64: # %bb.0: 1120; RV64-NEXT: slli a3, a0, 8 1121; RV64-NEXT: mv a0, a1 1122; RV64-NEXT: bgez a3, .LBB33_2 1123; RV64-NEXT: # %bb.1: 1124; RV64-NEXT: mv a0, a2 1125; RV64-NEXT: .LBB33_2: 1126; RV64-NEXT: ret 1127 %1 = and i64 %a, 36028797018963968 1128 %2 = icmp eq i64 %1, 0 1129 %3 = select i1 %2, i64 %b, i64 %c 1130 ret i64 %3 1131} 1132 1133define i64 @bit_55_nz_select_i64(i64 %a, i64 %b, i64 %c) { 1134; RV32I-LABEL: bit_55_nz_select_i64: 1135; RV32I: # %bb.0: 1136; RV32I-NEXT: slli a1, a1, 8 1137; RV32I-NEXT: srli a1, a1, 31 1138; RV32I-NEXT: mv a0, a2 1139; RV32I-NEXT: bnez a1, .LBB34_2 1140; RV32I-NEXT: # %bb.1: 1141; RV32I-NEXT: mv a0, a4 1142; RV32I-NEXT: mv a3, a5 1143; RV32I-NEXT: .LBB34_2: 1144; RV32I-NEXT: mv a1, a3 1145; RV32I-NEXT: ret 1146; 1147; RV64-LABEL: bit_55_nz_select_i64: 1148; RV64: # %bb.0: 1149; RV64-NEXT: slli a3, a0, 8 1150; RV64-NEXT: mv a0, a1 1151; RV64-NEXT: bltz a3, .LBB34_2 1152; RV64-NEXT: # %bb.1: 1153; RV64-NEXT: mv a0, a2 1154; RV64-NEXT: .LBB34_2: 1155; RV64-NEXT: ret 1156; 1157; RV32ZBS-LABEL: bit_55_nz_select_i64: 1158; RV32ZBS: # %bb.0: 1159; RV32ZBS-NEXT: bexti a1, a1, 23 1160; RV32ZBS-NEXT: mv a0, a2 1161; RV32ZBS-NEXT: bnez a1, .LBB34_2 1162; RV32ZBS-NEXT: # %bb.1: 1163; RV32ZBS-NEXT: mv a0, a4 1164; RV32ZBS-NEXT: mv a3, a5 1165; RV32ZBS-NEXT: .LBB34_2: 1166; RV32ZBS-NEXT: mv a1, a3 1167; RV32ZBS-NEXT: ret 1168; 1169; RV32XTHEADBS-LABEL: bit_55_nz_select_i64: 1170; RV32XTHEADBS: # %bb.0: 1171; RV32XTHEADBS-NEXT: th.tst a1, a1, 23 1172; RV32XTHEADBS-NEXT: mv a0, a2 1173; RV32XTHEADBS-NEXT: bnez a1, .LBB34_2 1174; RV32XTHEADBS-NEXT: # %bb.1: 1175; RV32XTHEADBS-NEXT: mv a0, a4 1176; RV32XTHEADBS-NEXT: mv a3, a5 1177; RV32XTHEADBS-NEXT: .LBB34_2: 1178; RV32XTHEADBS-NEXT: mv a1, a3 1179; RV32XTHEADBS-NEXT: ret 1180 %1 = and i64 %a, 36028797018963968 1181 %2 = icmp ne i64 %1, 0 1182 %3 = select i1 %2, i64 %b, i64 %c 1183 ret i64 %3 1184} 1185 1186define i64 @bit_63_z_select_i64(i64 %a, i64 %b, i64 %c) { 1187; RV32-LABEL: bit_63_z_select_i64: 1188; RV32: # %bb.0: 1189; RV32-NEXT: mv a0, a2 1190; RV32-NEXT: bgez a1, .LBB35_2 1191; RV32-NEXT: # %bb.1: 1192; RV32-NEXT: mv a0, a4 1193; RV32-NEXT: mv a3, a5 1194; RV32-NEXT: .LBB35_2: 1195; RV32-NEXT: mv a1, a3 1196; RV32-NEXT: ret 1197; 1198; RV64-LABEL: bit_63_z_select_i64: 1199; RV64: # %bb.0: 1200; RV64-NEXT: bgez a0, .LBB35_2 1201; RV64-NEXT: # %bb.1: 1202; RV64-NEXT: mv a1, a2 1203; RV64-NEXT: .LBB35_2: 1204; RV64-NEXT: mv a0, a1 1205; RV64-NEXT: ret 1206 %1 = and i64 %a, 9223372036854775808 1207 %2 = icmp eq i64 %1, 0 1208 %3 = select i1 %2, i64 %b, i64 %c 1209 ret i64 %3 1210} 1211 1212define i64 @bit_63_nz_select_i64(i64 %a, i64 %b, i64 %c) { 1213; RV32-LABEL: bit_63_nz_select_i64: 1214; RV32: # %bb.0: 1215; RV32-NEXT: srli a1, a1, 31 1216; RV32-NEXT: mv a0, a2 1217; RV32-NEXT: bnez a1, .LBB36_2 1218; RV32-NEXT: # %bb.1: 1219; RV32-NEXT: mv a0, a4 1220; RV32-NEXT: mv a3, a5 1221; RV32-NEXT: .LBB36_2: 1222; RV32-NEXT: mv a1, a3 1223; RV32-NEXT: ret 1224; 1225; RV64-LABEL: bit_63_nz_select_i64: 1226; RV64: # %bb.0: 1227; RV64-NEXT: srli a3, a0, 63 1228; RV64-NEXT: mv a0, a1 1229; RV64-NEXT: bnez a3, .LBB36_2 1230; RV64-NEXT: # %bb.1: 1231; RV64-NEXT: mv a0, a2 1232; RV64-NEXT: .LBB36_2: 1233; RV64-NEXT: ret 1234 %1 = and i64 %a, 9223372036854775808 1235 %2 = icmp ne i64 %1, 0 1236 %3 = select i1 %2, i64 %b, i64 %c 1237 ret i64 %3 1238} 1239 1240define void @bit_10_z_branch_i32(i32 signext %0) { 1241; CHECK-LABEL: bit_10_z_branch_i32: 1242; CHECK: # %bb.0: 1243; CHECK-NEXT: andi a0, a0, 1024 1244; CHECK-NEXT: bnez a0, .LBB37_2 1245; CHECK-NEXT: # %bb.1: 1246; CHECK-NEXT: tail bar 1247; CHECK-NEXT: .LBB37_2: 1248; CHECK-NEXT: ret 1249 %2 = and i32 %0, 1024 1250 %3 = icmp eq i32 %2, 0 1251 br i1 %3, label %4, label %5 1252 12534: 1254 tail call void @bar() 1255 br label %5 1256 12575: 1258 ret void 1259} 1260 1261define void @bit_10_nz_branch_i32(i32 signext %0) { 1262; CHECK-LABEL: bit_10_nz_branch_i32: 1263; CHECK: # %bb.0: 1264; CHECK-NEXT: andi a0, a0, 1024 1265; CHECK-NEXT: beqz a0, .LBB38_2 1266; CHECK-NEXT: # %bb.1: 1267; CHECK-NEXT: tail bar 1268; CHECK-NEXT: .LBB38_2: 1269; CHECK-NEXT: ret 1270 %2 = and i32 %0, 1024 1271 %3 = icmp ne i32 %2, 0 1272 br i1 %3, label %4, label %5 1273 12744: 1275 tail call void @bar() 1276 br label %5 1277 12785: 1279 ret void 1280} 1281 1282define void @bit_11_z_branch_i32(i32 signext %0) { 1283; RV32-LABEL: bit_11_z_branch_i32: 1284; RV32: # %bb.0: 1285; RV32-NEXT: slli a0, a0, 20 1286; RV32-NEXT: bltz a0, .LBB39_2 1287; RV32-NEXT: # %bb.1: 1288; RV32-NEXT: tail bar 1289; RV32-NEXT: .LBB39_2: 1290; RV32-NEXT: ret 1291; 1292; RV64-LABEL: bit_11_z_branch_i32: 1293; RV64: # %bb.0: 1294; RV64-NEXT: slli a0, a0, 52 1295; RV64-NEXT: bltz a0, .LBB39_2 1296; RV64-NEXT: # %bb.1: 1297; RV64-NEXT: tail bar 1298; RV64-NEXT: .LBB39_2: 1299; RV64-NEXT: ret 1300 %2 = and i32 %0, 2048 1301 %3 = icmp eq i32 %2, 0 1302 br i1 %3, label %4, label %5 1303 13044: 1305 tail call void @bar() 1306 br label %5 1307 13085: 1309 ret void 1310} 1311 1312define void @bit_11_nz_branch_i32(i32 signext %0) { 1313; RV32-LABEL: bit_11_nz_branch_i32: 1314; RV32: # %bb.0: 1315; RV32-NEXT: slli a0, a0, 20 1316; RV32-NEXT: bgez a0, .LBB40_2 1317; RV32-NEXT: # %bb.1: 1318; RV32-NEXT: tail bar 1319; RV32-NEXT: .LBB40_2: 1320; RV32-NEXT: ret 1321; 1322; RV64-LABEL: bit_11_nz_branch_i32: 1323; RV64: # %bb.0: 1324; RV64-NEXT: slli a0, a0, 52 1325; RV64-NEXT: bgez a0, .LBB40_2 1326; RV64-NEXT: # %bb.1: 1327; RV64-NEXT: tail bar 1328; RV64-NEXT: .LBB40_2: 1329; RV64-NEXT: ret 1330 %2 = and i32 %0, 2048 1331 %3 = icmp ne i32 %2, 0 1332 br i1 %3, label %4, label %5 1333 13344: 1335 tail call void @bar() 1336 br label %5 1337 13385: 1339 ret void 1340} 1341 1342define void @bit_24_z_branch_i32(i32 signext %0) { 1343; RV32-LABEL: bit_24_z_branch_i32: 1344; RV32: # %bb.0: 1345; RV32-NEXT: slli a0, a0, 7 1346; RV32-NEXT: bltz a0, .LBB41_2 1347; RV32-NEXT: # %bb.1: 1348; RV32-NEXT: tail bar 1349; RV32-NEXT: .LBB41_2: 1350; RV32-NEXT: ret 1351; 1352; RV64-LABEL: bit_24_z_branch_i32: 1353; RV64: # %bb.0: 1354; RV64-NEXT: slli a0, a0, 39 1355; RV64-NEXT: bltz a0, .LBB41_2 1356; RV64-NEXT: # %bb.1: 1357; RV64-NEXT: tail bar 1358; RV64-NEXT: .LBB41_2: 1359; RV64-NEXT: ret 1360 %2 = and i32 %0, 16777216 1361 %3 = icmp eq i32 %2, 0 1362 br i1 %3, label %4, label %5 1363 13644: 1365 tail call void @bar() 1366 br label %5 1367 13685: 1369 ret void 1370} 1371 1372define void @bit_24_nz_branch_i32(i32 signext %0) { 1373; RV32-LABEL: bit_24_nz_branch_i32: 1374; RV32: # %bb.0: 1375; RV32-NEXT: slli a0, a0, 7 1376; RV32-NEXT: bgez a0, .LBB42_2 1377; RV32-NEXT: # %bb.1: 1378; RV32-NEXT: tail bar 1379; RV32-NEXT: .LBB42_2: 1380; RV32-NEXT: ret 1381; 1382; RV64-LABEL: bit_24_nz_branch_i32: 1383; RV64: # %bb.0: 1384; RV64-NEXT: slli a0, a0, 39 1385; RV64-NEXT: bgez a0, .LBB42_2 1386; RV64-NEXT: # %bb.1: 1387; RV64-NEXT: tail bar 1388; RV64-NEXT: .LBB42_2: 1389; RV64-NEXT: ret 1390 %2 = and i32 %0, 16777216 1391 %3 = icmp ne i32 %2, 0 1392 br i1 %3, label %4, label %5 1393 13944: 1395 tail call void @bar() 1396 br label %5 1397 13985: 1399 ret void 1400} 1401 1402define void @bit_31_z_branch_i32(i32 signext %0) { 1403; RV32-LABEL: bit_31_z_branch_i32: 1404; RV32: # %bb.0: 1405; RV32-NEXT: bltz a0, .LBB43_2 1406; RV32-NEXT: # %bb.1: 1407; RV32-NEXT: tail bar 1408; RV32-NEXT: .LBB43_2: 1409; RV32-NEXT: ret 1410; 1411; RV64-LABEL: bit_31_z_branch_i32: 1412; RV64: # %bb.0: 1413; RV64-NEXT: lui a1, 524288 1414; RV64-NEXT: and a0, a0, a1 1415; RV64-NEXT: bnez a0, .LBB43_2 1416; RV64-NEXT: # %bb.1: 1417; RV64-NEXT: tail bar 1418; RV64-NEXT: .LBB43_2: 1419; RV64-NEXT: ret 1420 %2 = and i32 %0, 2147483648 1421 %3 = icmp eq i32 %2, 0 1422 br i1 %3, label %4, label %5 1423 14244: 1425 tail call void @bar() 1426 br label %5 1427 14285: 1429 ret void 1430} 1431 1432define void @bit_31_nz_branch_i32(i32 signext %0) { 1433; RV32-LABEL: bit_31_nz_branch_i32: 1434; RV32: # %bb.0: 1435; RV32-NEXT: bgez a0, .LBB44_2 1436; RV32-NEXT: # %bb.1: 1437; RV32-NEXT: tail bar 1438; RV32-NEXT: .LBB44_2: 1439; RV32-NEXT: ret 1440; 1441; RV64-LABEL: bit_31_nz_branch_i32: 1442; RV64: # %bb.0: 1443; RV64-NEXT: lui a1, 524288 1444; RV64-NEXT: and a0, a0, a1 1445; RV64-NEXT: beqz a0, .LBB44_2 1446; RV64-NEXT: # %bb.1: 1447; RV64-NEXT: tail bar 1448; RV64-NEXT: .LBB44_2: 1449; RV64-NEXT: ret 1450 %2 = and i32 %0, 2147483648 1451 %3 = icmp ne i32 %2, 0 1452 br i1 %3, label %4, label %5 1453 14544: 1455 tail call void @bar() 1456 br label %5 1457 14585: 1459 ret void 1460} 1461 1462define void @bit_10_z_branch_i64(i64 %0) { 1463; CHECK-LABEL: bit_10_z_branch_i64: 1464; CHECK: # %bb.0: 1465; CHECK-NEXT: andi a0, a0, 1024 1466; CHECK-NEXT: bnez a0, .LBB45_2 1467; CHECK-NEXT: # %bb.1: 1468; CHECK-NEXT: tail bar 1469; CHECK-NEXT: .LBB45_2: 1470; CHECK-NEXT: ret 1471 %2 = and i64 %0, 1024 1472 %3 = icmp eq i64 %2, 0 1473 br i1 %3, label %4, label %5 1474 14754: 1476 tail call void @bar() 1477 br label %5 1478 14795: 1480 ret void 1481} 1482 1483define void @bit_10_nz_branch_i64(i64 %0) { 1484; CHECK-LABEL: bit_10_nz_branch_i64: 1485; CHECK: # %bb.0: 1486; CHECK-NEXT: andi a0, a0, 1024 1487; CHECK-NEXT: beqz a0, .LBB46_2 1488; CHECK-NEXT: # %bb.1: 1489; CHECK-NEXT: tail bar 1490; CHECK-NEXT: .LBB46_2: 1491; CHECK-NEXT: ret 1492 %2 = and i64 %0, 1024 1493 %3 = icmp ne i64 %2, 0 1494 br i1 %3, label %4, label %5 1495 14964: 1497 tail call void @bar() 1498 br label %5 1499 15005: 1501 ret void 1502} 1503 1504define void @bit_11_z_branch_i64(i64 %0) { 1505; RV32-LABEL: bit_11_z_branch_i64: 1506; RV32: # %bb.0: 1507; RV32-NEXT: slli a0, a0, 20 1508; RV32-NEXT: bltz a0, .LBB47_2 1509; RV32-NEXT: # %bb.1: 1510; RV32-NEXT: tail bar 1511; RV32-NEXT: .LBB47_2: 1512; RV32-NEXT: ret 1513; 1514; RV64-LABEL: bit_11_z_branch_i64: 1515; RV64: # %bb.0: 1516; RV64-NEXT: slli a0, a0, 52 1517; RV64-NEXT: bltz a0, .LBB47_2 1518; RV64-NEXT: # %bb.1: 1519; RV64-NEXT: tail bar 1520; RV64-NEXT: .LBB47_2: 1521; RV64-NEXT: ret 1522 %2 = and i64 %0, 2048 1523 %3 = icmp eq i64 %2, 0 1524 br i1 %3, label %4, label %5 1525 15264: 1527 tail call void @bar() 1528 br label %5 1529 15305: 1531 ret void 1532} 1533 1534define void @bit_11_nz_branch_i64(i64 %0) { 1535; RV32-LABEL: bit_11_nz_branch_i64: 1536; RV32: # %bb.0: 1537; RV32-NEXT: slli a0, a0, 20 1538; RV32-NEXT: bgez a0, .LBB48_2 1539; RV32-NEXT: # %bb.1: 1540; RV32-NEXT: tail bar 1541; RV32-NEXT: .LBB48_2: 1542; RV32-NEXT: ret 1543; 1544; RV64-LABEL: bit_11_nz_branch_i64: 1545; RV64: # %bb.0: 1546; RV64-NEXT: slli a0, a0, 52 1547; RV64-NEXT: bgez a0, .LBB48_2 1548; RV64-NEXT: # %bb.1: 1549; RV64-NEXT: tail bar 1550; RV64-NEXT: .LBB48_2: 1551; RV64-NEXT: ret 1552 %2 = and i64 %0, 2048 1553 %3 = icmp ne i64 %2, 0 1554 br i1 %3, label %4, label %5 1555 15564: 1557 tail call void @bar() 1558 br label %5 1559 15605: 1561 ret void 1562} 1563 1564define void @bit_24_z_branch_i64(i64 %0) { 1565; RV32-LABEL: bit_24_z_branch_i64: 1566; RV32: # %bb.0: 1567; RV32-NEXT: slli a0, a0, 7 1568; RV32-NEXT: bltz a0, .LBB49_2 1569; RV32-NEXT: # %bb.1: 1570; RV32-NEXT: tail bar 1571; RV32-NEXT: .LBB49_2: 1572; RV32-NEXT: ret 1573; 1574; RV64-LABEL: bit_24_z_branch_i64: 1575; RV64: # %bb.0: 1576; RV64-NEXT: slli a0, a0, 39 1577; RV64-NEXT: bltz a0, .LBB49_2 1578; RV64-NEXT: # %bb.1: 1579; RV64-NEXT: tail bar 1580; RV64-NEXT: .LBB49_2: 1581; RV64-NEXT: ret 1582 %2 = and i64 %0, 16777216 1583 %3 = icmp eq i64 %2, 0 1584 br i1 %3, label %4, label %5 1585 15864: 1587 tail call void @bar() 1588 br label %5 1589 15905: 1591 ret void 1592} 1593 1594define void @bit_24_nz_branch_i64(i64 %0) { 1595; RV32-LABEL: bit_24_nz_branch_i64: 1596; RV32: # %bb.0: 1597; RV32-NEXT: slli a0, a0, 7 1598; RV32-NEXT: bgez a0, .LBB50_2 1599; RV32-NEXT: # %bb.1: 1600; RV32-NEXT: tail bar 1601; RV32-NEXT: .LBB50_2: 1602; RV32-NEXT: ret 1603; 1604; RV64-LABEL: bit_24_nz_branch_i64: 1605; RV64: # %bb.0: 1606; RV64-NEXT: slli a0, a0, 39 1607; RV64-NEXT: bgez a0, .LBB50_2 1608; RV64-NEXT: # %bb.1: 1609; RV64-NEXT: tail bar 1610; RV64-NEXT: .LBB50_2: 1611; RV64-NEXT: ret 1612 %2 = and i64 %0, 16777216 1613 %3 = icmp ne i64 %2, 0 1614 br i1 %3, label %4, label %5 1615 16164: 1617 tail call void @bar() 1618 br label %5 1619 16205: 1621 ret void 1622} 1623 1624define void @bit_31_z_branch_i64(i64 %0) { 1625; RV32-LABEL: bit_31_z_branch_i64: 1626; RV32: # %bb.0: 1627; RV32-NEXT: bltz a0, .LBB51_2 1628; RV32-NEXT: # %bb.1: 1629; RV32-NEXT: tail bar 1630; RV32-NEXT: .LBB51_2: 1631; RV32-NEXT: ret 1632; 1633; RV64-LABEL: bit_31_z_branch_i64: 1634; RV64: # %bb.0: 1635; RV64-NEXT: slli a0, a0, 32 1636; RV64-NEXT: bltz a0, .LBB51_2 1637; RV64-NEXT: # %bb.1: 1638; RV64-NEXT: tail bar 1639; RV64-NEXT: .LBB51_2: 1640; RV64-NEXT: ret 1641 %2 = and i64 %0, 2147483648 1642 %3 = icmp eq i64 %2, 0 1643 br i1 %3, label %4, label %5 1644 16454: 1646 tail call void @bar() 1647 br label %5 1648 16495: 1650 ret void 1651} 1652 1653define void @bit_31_nz_branch_i64(i64 %0) { 1654; RV32-LABEL: bit_31_nz_branch_i64: 1655; RV32: # %bb.0: 1656; RV32-NEXT: bgez a0, .LBB52_2 1657; RV32-NEXT: # %bb.1: 1658; RV32-NEXT: tail bar 1659; RV32-NEXT: .LBB52_2: 1660; RV32-NEXT: ret 1661; 1662; RV64-LABEL: bit_31_nz_branch_i64: 1663; RV64: # %bb.0: 1664; RV64-NEXT: slli a0, a0, 32 1665; RV64-NEXT: bgez a0, .LBB52_2 1666; RV64-NEXT: # %bb.1: 1667; RV64-NEXT: tail bar 1668; RV64-NEXT: .LBB52_2: 1669; RV64-NEXT: ret 1670 %2 = and i64 %0, 2147483648 1671 %3 = icmp ne i64 %2, 0 1672 br i1 %3, label %4, label %5 1673 16744: 1675 tail call void @bar() 1676 br label %5 1677 16785: 1679 ret void 1680} 1681 1682define void @bit_32_z_branch_i64(i64 %0) { 1683; RV32-LABEL: bit_32_z_branch_i64: 1684; RV32: # %bb.0: 1685; RV32-NEXT: andi a1, a1, 1 1686; RV32-NEXT: bnez a1, .LBB53_2 1687; RV32-NEXT: # %bb.1: 1688; RV32-NEXT: tail bar 1689; RV32-NEXT: .LBB53_2: 1690; RV32-NEXT: ret 1691; 1692; RV64-LABEL: bit_32_z_branch_i64: 1693; RV64: # %bb.0: 1694; RV64-NEXT: slli a0, a0, 31 1695; RV64-NEXT: bltz a0, .LBB53_2 1696; RV64-NEXT: # %bb.1: 1697; RV64-NEXT: tail bar 1698; RV64-NEXT: .LBB53_2: 1699; RV64-NEXT: ret 1700 %2 = and i64 %0, 4294967296 1701 %3 = icmp eq i64 %2, 0 1702 br i1 %3, label %4, label %5 1703 17044: 1705 tail call void @bar() 1706 br label %5 1707 17085: 1709 ret void 1710} 1711 1712define void @bit_32_nz_branch_i64(i64 %0) { 1713; RV32-LABEL: bit_32_nz_branch_i64: 1714; RV32: # %bb.0: 1715; RV32-NEXT: andi a1, a1, 1 1716; RV32-NEXT: beqz a1, .LBB54_2 1717; RV32-NEXT: # %bb.1: 1718; RV32-NEXT: tail bar 1719; RV32-NEXT: .LBB54_2: 1720; RV32-NEXT: ret 1721; 1722; RV64-LABEL: bit_32_nz_branch_i64: 1723; RV64: # %bb.0: 1724; RV64-NEXT: slli a0, a0, 31 1725; RV64-NEXT: bgez a0, .LBB54_2 1726; RV64-NEXT: # %bb.1: 1727; RV64-NEXT: tail bar 1728; RV64-NEXT: .LBB54_2: 1729; RV64-NEXT: ret 1730 %2 = and i64 %0, 4294967296 1731 %3 = icmp ne i64 %2, 0 1732 br i1 %3, label %4, label %5 1733 17344: 1735 tail call void @bar() 1736 br label %5 1737 17385: 1739 ret void 1740} 1741 1742define void @bit_62_z_branch_i64(i64 %0) { 1743; RV32-LABEL: bit_62_z_branch_i64: 1744; RV32: # %bb.0: 1745; RV32-NEXT: slli a1, a1, 1 1746; RV32-NEXT: bltz a1, .LBB55_2 1747; RV32-NEXT: # %bb.1: 1748; RV32-NEXT: tail bar 1749; RV32-NEXT: .LBB55_2: 1750; RV32-NEXT: ret 1751; 1752; RV64-LABEL: bit_62_z_branch_i64: 1753; RV64: # %bb.0: 1754; RV64-NEXT: slli a0, a0, 1 1755; RV64-NEXT: bltz a0, .LBB55_2 1756; RV64-NEXT: # %bb.1: 1757; RV64-NEXT: tail bar 1758; RV64-NEXT: .LBB55_2: 1759; RV64-NEXT: ret 1760 %2 = and i64 %0, 4611686018427387904 1761 %3 = icmp eq i64 %2, 0 1762 br i1 %3, label %4, label %5 1763 17644: 1765 tail call void @bar() 1766 br label %5 1767 17685: 1769 ret void 1770} 1771 1772define void @bit_62_nz_branch_i64(i64 %0) { 1773; RV32-LABEL: bit_62_nz_branch_i64: 1774; RV32: # %bb.0: 1775; RV32-NEXT: slli a1, a1, 1 1776; RV32-NEXT: bgez a1, .LBB56_2 1777; RV32-NEXT: # %bb.1: 1778; RV32-NEXT: tail bar 1779; RV32-NEXT: .LBB56_2: 1780; RV32-NEXT: ret 1781; 1782; RV64-LABEL: bit_62_nz_branch_i64: 1783; RV64: # %bb.0: 1784; RV64-NEXT: slli a0, a0, 1 1785; RV64-NEXT: bgez a0, .LBB56_2 1786; RV64-NEXT: # %bb.1: 1787; RV64-NEXT: tail bar 1788; RV64-NEXT: .LBB56_2: 1789; RV64-NEXT: ret 1790 %2 = and i64 %0, 4611686018427387904 1791 %3 = icmp ne i64 %2, 0 1792 br i1 %3, label %4, label %5 1793 17944: 1795 tail call void @bar() 1796 br label %5 1797 17985: 1799 ret void 1800} 1801 1802define void @bit_63_z_branch_i64(i64 %0) { 1803; RV32-LABEL: bit_63_z_branch_i64: 1804; RV32: # %bb.0: 1805; RV32-NEXT: bltz a1, .LBB57_2 1806; RV32-NEXT: # %bb.1: 1807; RV32-NEXT: tail bar 1808; RV32-NEXT: .LBB57_2: 1809; RV32-NEXT: ret 1810; 1811; RV64-LABEL: bit_63_z_branch_i64: 1812; RV64: # %bb.0: 1813; RV64-NEXT: bltz a0, .LBB57_2 1814; RV64-NEXT: # %bb.1: 1815; RV64-NEXT: tail bar 1816; RV64-NEXT: .LBB57_2: 1817; RV64-NEXT: ret 1818 %2 = and i64 %0, 9223372036854775808 1819 %3 = icmp eq i64 %2, 0 1820 br i1 %3, label %4, label %5 1821 18224: 1823 tail call void @bar() 1824 br label %5 1825 18265: 1827 ret void 1828} 1829 1830define void @bit_63_nz_branch_i64(i64 %0) { 1831; RV32-LABEL: bit_63_nz_branch_i64: 1832; RV32: # %bb.0: 1833; RV32-NEXT: bgez a1, .LBB58_2 1834; RV32-NEXT: # %bb.1: 1835; RV32-NEXT: tail bar 1836; RV32-NEXT: .LBB58_2: 1837; RV32-NEXT: ret 1838; 1839; RV64-LABEL: bit_63_nz_branch_i64: 1840; RV64: # %bb.0: 1841; RV64-NEXT: bgez a0, .LBB58_2 1842; RV64-NEXT: # %bb.1: 1843; RV64-NEXT: tail bar 1844; RV64-NEXT: .LBB58_2: 1845; RV64-NEXT: ret 1846 %2 = and i64 %0, 9223372036854775808 1847 %3 = icmp ne i64 %2, 0 1848 br i1 %3, label %4, label %5 1849 18504: 1851 tail call void @bar() 1852 br label %5 1853 18545: 1855 ret void 1856} 1857 1858define signext i32 @bit_10_1_z_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 1859; CHECK-LABEL: bit_10_1_z_select_i32: 1860; CHECK: # %bb.0: 1861; CHECK-NEXT: andi a3, a0, 1023 1862; CHECK-NEXT: mv a0, a1 1863; CHECK-NEXT: beqz a3, .LBB59_2 1864; CHECK-NEXT: # %bb.1: 1865; CHECK-NEXT: mv a0, a2 1866; CHECK-NEXT: .LBB59_2: 1867; CHECK-NEXT: ret 1868 %1 = and i32 %a, 1023 1869 %2 = icmp eq i32 %1, 0 1870 %3 = select i1 %2, i32 %b, i32 %c 1871 ret i32 %3 1872} 1873 1874define signext i32 @bit_10_1_nz_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 1875; CHECK-LABEL: bit_10_1_nz_select_i32: 1876; CHECK: # %bb.0: 1877; CHECK-NEXT: andi a3, a0, 1023 1878; CHECK-NEXT: mv a0, a1 1879; CHECK-NEXT: bnez a3, .LBB60_2 1880; CHECK-NEXT: # %bb.1: 1881; CHECK-NEXT: mv a0, a2 1882; CHECK-NEXT: .LBB60_2: 1883; CHECK-NEXT: ret 1884 %1 = and i32 %a, 1023 1885 %2 = icmp ne i32 %1, 0 1886 %3 = select i1 %2, i32 %b, i32 %c 1887 ret i32 %3 1888} 1889 1890define signext i32 @bit_11_1_z_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 1891; CHECK-LABEL: bit_11_1_z_select_i32: 1892; CHECK: # %bb.0: 1893; CHECK-NEXT: andi a3, a0, 2047 1894; CHECK-NEXT: mv a0, a1 1895; CHECK-NEXT: beqz a3, .LBB61_2 1896; CHECK-NEXT: # %bb.1: 1897; CHECK-NEXT: mv a0, a2 1898; CHECK-NEXT: .LBB61_2: 1899; CHECK-NEXT: ret 1900 %1 = and i32 %a, 2047 1901 %2 = icmp eq i32 %1, 0 1902 %3 = select i1 %2, i32 %b, i32 %c 1903 ret i32 %3 1904} 1905 1906define signext i32 @bit_11_1_nz_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 1907; CHECK-LABEL: bit_11_1_nz_select_i32: 1908; CHECK: # %bb.0: 1909; CHECK-NEXT: andi a3, a0, 2047 1910; CHECK-NEXT: mv a0, a1 1911; CHECK-NEXT: bnez a3, .LBB62_2 1912; CHECK-NEXT: # %bb.1: 1913; CHECK-NEXT: mv a0, a2 1914; CHECK-NEXT: .LBB62_2: 1915; CHECK-NEXT: ret 1916 %1 = and i32 %a, 2047 1917 %2 = icmp ne i32 %1, 0 1918 %3 = select i1 %2, i32 %b, i32 %c 1919 ret i32 %3 1920} 1921 1922define signext i32 @bit_16_1_z_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 1923; RV32-LABEL: bit_16_1_z_select_i32: 1924; RV32: # %bb.0: 1925; RV32-NEXT: slli a3, a0, 16 1926; RV32-NEXT: mv a0, a1 1927; RV32-NEXT: beqz a3, .LBB63_2 1928; RV32-NEXT: # %bb.1: 1929; RV32-NEXT: mv a0, a2 1930; RV32-NEXT: .LBB63_2: 1931; RV32-NEXT: ret 1932; 1933; RV64-LABEL: bit_16_1_z_select_i32: 1934; RV64: # %bb.0: 1935; RV64-NEXT: slli a3, a0, 48 1936; RV64-NEXT: mv a0, a1 1937; RV64-NEXT: beqz a3, .LBB63_2 1938; RV64-NEXT: # %bb.1: 1939; RV64-NEXT: mv a0, a2 1940; RV64-NEXT: .LBB63_2: 1941; RV64-NEXT: ret 1942 %1 = and i32 %a, 65535 1943 %2 = icmp eq i32 %1, 0 1944 %3 = select i1 %2, i32 %b, i32 %c 1945 ret i32 %3 1946} 1947 1948define signext i32 @bit_16_1_nz_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 1949; RV32-LABEL: bit_16_1_nz_select_i32: 1950; RV32: # %bb.0: 1951; RV32-NEXT: slli a3, a0, 16 1952; RV32-NEXT: mv a0, a1 1953; RV32-NEXT: bnez a3, .LBB64_2 1954; RV32-NEXT: # %bb.1: 1955; RV32-NEXT: mv a0, a2 1956; RV32-NEXT: .LBB64_2: 1957; RV32-NEXT: ret 1958; 1959; RV64-LABEL: bit_16_1_nz_select_i32: 1960; RV64: # %bb.0: 1961; RV64-NEXT: slli a3, a0, 48 1962; RV64-NEXT: mv a0, a1 1963; RV64-NEXT: bnez a3, .LBB64_2 1964; RV64-NEXT: # %bb.1: 1965; RV64-NEXT: mv a0, a2 1966; RV64-NEXT: .LBB64_2: 1967; RV64-NEXT: ret 1968 %1 = and i32 %a, 65535 1969 %2 = icmp ne i32 %1, 0 1970 %3 = select i1 %2, i32 %b, i32 %c 1971 ret i32 %3 1972} 1973 1974define signext i32 @bit_20_1_z_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 1975; RV32-LABEL: bit_20_1_z_select_i32: 1976; RV32: # %bb.0: 1977; RV32-NEXT: slli a3, a0, 12 1978; RV32-NEXT: mv a0, a1 1979; RV32-NEXT: beqz a3, .LBB65_2 1980; RV32-NEXT: # %bb.1: 1981; RV32-NEXT: mv a0, a2 1982; RV32-NEXT: .LBB65_2: 1983; RV32-NEXT: ret 1984; 1985; RV64-LABEL: bit_20_1_z_select_i32: 1986; RV64: # %bb.0: 1987; RV64-NEXT: slli a3, a0, 44 1988; RV64-NEXT: mv a0, a1 1989; RV64-NEXT: beqz a3, .LBB65_2 1990; RV64-NEXT: # %bb.1: 1991; RV64-NEXT: mv a0, a2 1992; RV64-NEXT: .LBB65_2: 1993; RV64-NEXT: ret 1994 %1 = and i32 %a, 1048575 1995 %2 = icmp eq i32 %1, 0 1996 %3 = select i1 %2, i32 %b, i32 %c 1997 ret i32 %3 1998} 1999 2000define signext i32 @bit_20_1_nz_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 2001; RV32-LABEL: bit_20_1_nz_select_i32: 2002; RV32: # %bb.0: 2003; RV32-NEXT: slli a3, a0, 12 2004; RV32-NEXT: mv a0, a1 2005; RV32-NEXT: bnez a3, .LBB66_2 2006; RV32-NEXT: # %bb.1: 2007; RV32-NEXT: mv a0, a2 2008; RV32-NEXT: .LBB66_2: 2009; RV32-NEXT: ret 2010; 2011; RV64-LABEL: bit_20_1_nz_select_i32: 2012; RV64: # %bb.0: 2013; RV64-NEXT: slli a3, a0, 44 2014; RV64-NEXT: mv a0, a1 2015; RV64-NEXT: bnez a3, .LBB66_2 2016; RV64-NEXT: # %bb.1: 2017; RV64-NEXT: mv a0, a2 2018; RV64-NEXT: .LBB66_2: 2019; RV64-NEXT: ret 2020 %1 = and i32 %a, 1048575 2021 %2 = icmp ne i32 %1, 0 2022 %3 = select i1 %2, i32 %b, i32 %c 2023 ret i32 %3 2024} 2025 2026define signext i32 @bit_31_1_z_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 2027; RV32-LABEL: bit_31_1_z_select_i32: 2028; RV32: # %bb.0: 2029; RV32-NEXT: slli a3, a0, 1 2030; RV32-NEXT: mv a0, a1 2031; RV32-NEXT: beqz a3, .LBB67_2 2032; RV32-NEXT: # %bb.1: 2033; RV32-NEXT: mv a0, a2 2034; RV32-NEXT: .LBB67_2: 2035; RV32-NEXT: ret 2036; 2037; RV64-LABEL: bit_31_1_z_select_i32: 2038; RV64: # %bb.0: 2039; RV64-NEXT: slli a3, a0, 33 2040; RV64-NEXT: mv a0, a1 2041; RV64-NEXT: beqz a3, .LBB67_2 2042; RV64-NEXT: # %bb.1: 2043; RV64-NEXT: mv a0, a2 2044; RV64-NEXT: .LBB67_2: 2045; RV64-NEXT: ret 2046 %1 = and i32 %a, 2147483647 2047 %2 = icmp eq i32 %1, 0 2048 %3 = select i1 %2, i32 %b, i32 %c 2049 ret i32 %3 2050} 2051 2052define signext i32 @bit_31_1_nz_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 2053; RV32-LABEL: bit_31_1_nz_select_i32: 2054; RV32: # %bb.0: 2055; RV32-NEXT: slli a3, a0, 1 2056; RV32-NEXT: mv a0, a1 2057; RV32-NEXT: bnez a3, .LBB68_2 2058; RV32-NEXT: # %bb.1: 2059; RV32-NEXT: mv a0, a2 2060; RV32-NEXT: .LBB68_2: 2061; RV32-NEXT: ret 2062; 2063; RV64-LABEL: bit_31_1_nz_select_i32: 2064; RV64: # %bb.0: 2065; RV64-NEXT: slli a3, a0, 33 2066; RV64-NEXT: mv a0, a1 2067; RV64-NEXT: bnez a3, .LBB68_2 2068; RV64-NEXT: # %bb.1: 2069; RV64-NEXT: mv a0, a2 2070; RV64-NEXT: .LBB68_2: 2071; RV64-NEXT: ret 2072 %1 = and i32 %a, 2147483647 2073 %2 = icmp ne i32 %1, 0 2074 %3 = select i1 %2, i32 %b, i32 %c 2075 ret i32 %3 2076} 2077 2078define signext i32 @bit_32_1_z_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 2079; CHECK-LABEL: bit_32_1_z_select_i32: 2080; CHECK: # %bb.0: 2081; CHECK-NEXT: beqz a0, .LBB69_2 2082; CHECK-NEXT: # %bb.1: 2083; CHECK-NEXT: mv a1, a2 2084; CHECK-NEXT: .LBB69_2: 2085; CHECK-NEXT: mv a0, a1 2086; CHECK-NEXT: ret 2087 %1 = and i32 %a, 4294967295 2088 %2 = icmp eq i32 %1, 0 2089 %3 = select i1 %2, i32 %b, i32 %c 2090 ret i32 %3 2091} 2092 2093define signext i32 @bit_32_1_nz_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 2094; CHECK-LABEL: bit_32_1_nz_select_i32: 2095; CHECK: # %bb.0: 2096; CHECK-NEXT: bnez a0, .LBB70_2 2097; CHECK-NEXT: # %bb.1: 2098; CHECK-NEXT: mv a1, a2 2099; CHECK-NEXT: .LBB70_2: 2100; CHECK-NEXT: mv a0, a1 2101; CHECK-NEXT: ret 2102 %1 = and i32 %a, 4294967295 2103 %2 = icmp ne i32 %1, 0 2104 %3 = select i1 %2, i32 %b, i32 %c 2105 ret i32 %3 2106} 2107 2108define i64 @bit_10_1_z_select_i64(i64 %a, i64 %b, i64 %c) { 2109; RV32-LABEL: bit_10_1_z_select_i64: 2110; RV32: # %bb.0: 2111; RV32-NEXT: mv a1, a3 2112; RV32-NEXT: andi a3, a0, 1023 2113; RV32-NEXT: mv a0, a2 2114; RV32-NEXT: beqz a3, .LBB71_2 2115; RV32-NEXT: # %bb.1: 2116; RV32-NEXT: mv a0, a4 2117; RV32-NEXT: mv a1, a5 2118; RV32-NEXT: .LBB71_2: 2119; RV32-NEXT: ret 2120; 2121; RV64-LABEL: bit_10_1_z_select_i64: 2122; RV64: # %bb.0: 2123; RV64-NEXT: andi a3, a0, 1023 2124; RV64-NEXT: mv a0, a1 2125; RV64-NEXT: beqz a3, .LBB71_2 2126; RV64-NEXT: # %bb.1: 2127; RV64-NEXT: mv a0, a2 2128; RV64-NEXT: .LBB71_2: 2129; RV64-NEXT: ret 2130 %1 = and i64 %a, 1023 2131 %2 = icmp eq i64 %1, 0 2132 %3 = select i1 %2, i64 %b, i64 %c 2133 ret i64 %3 2134} 2135 2136define i64 @bit_10_1_nz_select_i64(i64 %a, i64 %b, i64 %c) { 2137; RV32-LABEL: bit_10_1_nz_select_i64: 2138; RV32: # %bb.0: 2139; RV32-NEXT: mv a1, a3 2140; RV32-NEXT: andi a3, a0, 1023 2141; RV32-NEXT: mv a0, a2 2142; RV32-NEXT: bnez a3, .LBB72_2 2143; RV32-NEXT: # %bb.1: 2144; RV32-NEXT: mv a0, a4 2145; RV32-NEXT: mv a1, a5 2146; RV32-NEXT: .LBB72_2: 2147; RV32-NEXT: ret 2148; 2149; RV64-LABEL: bit_10_1_nz_select_i64: 2150; RV64: # %bb.0: 2151; RV64-NEXT: andi a3, a0, 1023 2152; RV64-NEXT: mv a0, a1 2153; RV64-NEXT: bnez a3, .LBB72_2 2154; RV64-NEXT: # %bb.1: 2155; RV64-NEXT: mv a0, a2 2156; RV64-NEXT: .LBB72_2: 2157; RV64-NEXT: ret 2158 %1 = and i64 %a, 1023 2159 %2 = icmp ne i64 %1, 0 2160 %3 = select i1 %2, i64 %b, i64 %c 2161 ret i64 %3 2162} 2163 2164define i64 @bit_11_1_z_select_i64(i64 %a, i64 %b, i64 %c) { 2165; RV32-LABEL: bit_11_1_z_select_i64: 2166; RV32: # %bb.0: 2167; RV32-NEXT: mv a1, a3 2168; RV32-NEXT: andi a3, a0, 2047 2169; RV32-NEXT: mv a0, a2 2170; RV32-NEXT: beqz a3, .LBB73_2 2171; RV32-NEXT: # %bb.1: 2172; RV32-NEXT: mv a0, a4 2173; RV32-NEXT: mv a1, a5 2174; RV32-NEXT: .LBB73_2: 2175; RV32-NEXT: ret 2176; 2177; RV64-LABEL: bit_11_1_z_select_i64: 2178; RV64: # %bb.0: 2179; RV64-NEXT: andi a3, a0, 2047 2180; RV64-NEXT: mv a0, a1 2181; RV64-NEXT: beqz a3, .LBB73_2 2182; RV64-NEXT: # %bb.1: 2183; RV64-NEXT: mv a0, a2 2184; RV64-NEXT: .LBB73_2: 2185; RV64-NEXT: ret 2186 %1 = and i64 %a, 2047 2187 %2 = icmp eq i64 %1, 0 2188 %3 = select i1 %2, i64 %b, i64 %c 2189 ret i64 %3 2190} 2191 2192define i64 @bit_11_1_nz_select_i64(i64 %a, i64 %b, i64 %c) { 2193; RV32-LABEL: bit_11_1_nz_select_i64: 2194; RV32: # %bb.0: 2195; RV32-NEXT: mv a1, a3 2196; RV32-NEXT: andi a3, a0, 2047 2197; RV32-NEXT: mv a0, a2 2198; RV32-NEXT: bnez a3, .LBB74_2 2199; RV32-NEXT: # %bb.1: 2200; RV32-NEXT: mv a0, a4 2201; RV32-NEXT: mv a1, a5 2202; RV32-NEXT: .LBB74_2: 2203; RV32-NEXT: ret 2204; 2205; RV64-LABEL: bit_11_1_nz_select_i64: 2206; RV64: # %bb.0: 2207; RV64-NEXT: andi a3, a0, 2047 2208; RV64-NEXT: mv a0, a1 2209; RV64-NEXT: bnez a3, .LBB74_2 2210; RV64-NEXT: # %bb.1: 2211; RV64-NEXT: mv a0, a2 2212; RV64-NEXT: .LBB74_2: 2213; RV64-NEXT: ret 2214 %1 = and i64 %a, 2047 2215 %2 = icmp ne i64 %1, 0 2216 %3 = select i1 %2, i64 %b, i64 %c 2217 ret i64 %3 2218} 2219 2220define i64 @bit_16_1_z_select_i64(i64 %a, i64 %b, i64 %c) { 2221; RV32-LABEL: bit_16_1_z_select_i64: 2222; RV32: # %bb.0: 2223; RV32-NEXT: mv a1, a3 2224; RV32-NEXT: slli a3, a0, 16 2225; RV32-NEXT: mv a0, a2 2226; RV32-NEXT: beqz a3, .LBB75_2 2227; RV32-NEXT: # %bb.1: 2228; RV32-NEXT: mv a0, a4 2229; RV32-NEXT: mv a1, a5 2230; RV32-NEXT: .LBB75_2: 2231; RV32-NEXT: ret 2232; 2233; RV64-LABEL: bit_16_1_z_select_i64: 2234; RV64: # %bb.0: 2235; RV64-NEXT: slli a3, a0, 48 2236; RV64-NEXT: mv a0, a1 2237; RV64-NEXT: beqz a3, .LBB75_2 2238; RV64-NEXT: # %bb.1: 2239; RV64-NEXT: mv a0, a2 2240; RV64-NEXT: .LBB75_2: 2241; RV64-NEXT: ret 2242 %1 = and i64 %a, 65535 2243 %2 = icmp eq i64 %1, 0 2244 %3 = select i1 %2, i64 %b, i64 %c 2245 ret i64 %3 2246} 2247 2248define i64 @bit_16_1_nz_select_i64(i64 %a, i64 %b, i64 %c) { 2249; RV32-LABEL: bit_16_1_nz_select_i64: 2250; RV32: # %bb.0: 2251; RV32-NEXT: mv a1, a3 2252; RV32-NEXT: bnez a0, .LBB76_2 2253; RV32-NEXT: # %bb.1: 2254; RV32-NEXT: mv a2, a4 2255; RV32-NEXT: mv a1, a5 2256; RV32-NEXT: .LBB76_2: 2257; RV32-NEXT: mv a0, a2 2258; RV32-NEXT: ret 2259; 2260; RV64-LABEL: bit_16_1_nz_select_i64: 2261; RV64: # %bb.0: 2262; RV64-NEXT: sext.w a3, a0 2263; RV64-NEXT: mv a0, a1 2264; RV64-NEXT: bnez a3, .LBB76_2 2265; RV64-NEXT: # %bb.1: 2266; RV64-NEXT: mv a0, a2 2267; RV64-NEXT: .LBB76_2: 2268; RV64-NEXT: ret 2269 %1 = and i64 %a, 4294967295 2270 %2 = icmp ne i64 %1, 0 2271 %3 = select i1 %2, i64 %b, i64 %c 2272 ret i64 %3 2273} 2274 2275 2276define i64 @bit_20_1_z_select_i64(i64 %a, i64 %b, i64 %c) { 2277; RV32-LABEL: bit_20_1_z_select_i64: 2278; RV32: # %bb.0: 2279; RV32-NEXT: mv a1, a3 2280; RV32-NEXT: slli a3, a0, 12 2281; RV32-NEXT: mv a0, a2 2282; RV32-NEXT: beqz a3, .LBB77_2 2283; RV32-NEXT: # %bb.1: 2284; RV32-NEXT: mv a0, a4 2285; RV32-NEXT: mv a1, a5 2286; RV32-NEXT: .LBB77_2: 2287; RV32-NEXT: ret 2288; 2289; RV64-LABEL: bit_20_1_z_select_i64: 2290; RV64: # %bb.0: 2291; RV64-NEXT: slli a3, a0, 44 2292; RV64-NEXT: mv a0, a1 2293; RV64-NEXT: beqz a3, .LBB77_2 2294; RV64-NEXT: # %bb.1: 2295; RV64-NEXT: mv a0, a2 2296; RV64-NEXT: .LBB77_2: 2297; RV64-NEXT: ret 2298 %1 = and i64 %a, 1048575 2299 %2 = icmp eq i64 %1, 0 2300 %3 = select i1 %2, i64 %b, i64 %c 2301 ret i64 %3 2302} 2303 2304define i64 @bit_20_1_nz_select_i64(i64 %a, i64 %b, i64 %c) { 2305; RV32-LABEL: bit_20_1_nz_select_i64: 2306; RV32: # %bb.0: 2307; RV32-NEXT: mv a1, a3 2308; RV32-NEXT: slli a3, a0, 12 2309; RV32-NEXT: mv a0, a2 2310; RV32-NEXT: bnez a3, .LBB78_2 2311; RV32-NEXT: # %bb.1: 2312; RV32-NEXT: mv a0, a4 2313; RV32-NEXT: mv a1, a5 2314; RV32-NEXT: .LBB78_2: 2315; RV32-NEXT: ret 2316; 2317; RV64-LABEL: bit_20_1_nz_select_i64: 2318; RV64: # %bb.0: 2319; RV64-NEXT: slli a3, a0, 44 2320; RV64-NEXT: mv a0, a1 2321; RV64-NEXT: bnez a3, .LBB78_2 2322; RV64-NEXT: # %bb.1: 2323; RV64-NEXT: mv a0, a2 2324; RV64-NEXT: .LBB78_2: 2325; RV64-NEXT: ret 2326 %1 = and i64 %a, 1048575 2327 %2 = icmp ne i64 %1, 0 2328 %3 = select i1 %2, i64 %b, i64 %c 2329 ret i64 %3 2330} 2331 2332define i64 @bit_31_1_z_select_i64(i64 %a, i64 %b, i64 %c) { 2333; RV32-LABEL: bit_31_1_z_select_i64: 2334; RV32: # %bb.0: 2335; RV32-NEXT: mv a1, a3 2336; RV32-NEXT: slli a3, a0, 1 2337; RV32-NEXT: mv a0, a2 2338; RV32-NEXT: beqz a3, .LBB79_2 2339; RV32-NEXT: # %bb.1: 2340; RV32-NEXT: mv a0, a4 2341; RV32-NEXT: mv a1, a5 2342; RV32-NEXT: .LBB79_2: 2343; RV32-NEXT: ret 2344; 2345; RV64-LABEL: bit_31_1_z_select_i64: 2346; RV64: # %bb.0: 2347; RV64-NEXT: slli a3, a0, 33 2348; RV64-NEXT: mv a0, a1 2349; RV64-NEXT: beqz a3, .LBB79_2 2350; RV64-NEXT: # %bb.1: 2351; RV64-NEXT: mv a0, a2 2352; RV64-NEXT: .LBB79_2: 2353; RV64-NEXT: ret 2354 %1 = and i64 %a, 2147483647 2355 %2 = icmp eq i64 %1, 0 2356 %3 = select i1 %2, i64 %b, i64 %c 2357 ret i64 %3 2358} 2359 2360define i64 @bit_31_1_nz_select_i64(i64 %a, i64 %b, i64 %c) { 2361; RV32-LABEL: bit_31_1_nz_select_i64: 2362; RV32: # %bb.0: 2363; RV32-NEXT: mv a1, a3 2364; RV32-NEXT: slli a3, a0, 1 2365; RV32-NEXT: mv a0, a2 2366; RV32-NEXT: bnez a3, .LBB80_2 2367; RV32-NEXT: # %bb.1: 2368; RV32-NEXT: mv a0, a4 2369; RV32-NEXT: mv a1, a5 2370; RV32-NEXT: .LBB80_2: 2371; RV32-NEXT: ret 2372; 2373; RV64-LABEL: bit_31_1_nz_select_i64: 2374; RV64: # %bb.0: 2375; RV64-NEXT: slli a3, a0, 33 2376; RV64-NEXT: mv a0, a1 2377; RV64-NEXT: bnez a3, .LBB80_2 2378; RV64-NEXT: # %bb.1: 2379; RV64-NEXT: mv a0, a2 2380; RV64-NEXT: .LBB80_2: 2381; RV64-NEXT: ret 2382 %1 = and i64 %a, 2147483647 2383 %2 = icmp ne i64 %1, 0 2384 %3 = select i1 %2, i64 %b, i64 %c 2385 ret i64 %3 2386} 2387 2388define i64 @bit_32_1_z_select_i64(i64 %a, i64 %b, i64 %c) { 2389; RV32-LABEL: bit_32_1_z_select_i64: 2390; RV32: # %bb.0: 2391; RV32-NEXT: mv a1, a3 2392; RV32-NEXT: beqz a0, .LBB81_2 2393; RV32-NEXT: # %bb.1: 2394; RV32-NEXT: mv a2, a4 2395; RV32-NEXT: mv a1, a5 2396; RV32-NEXT: .LBB81_2: 2397; RV32-NEXT: mv a0, a2 2398; RV32-NEXT: ret 2399; 2400; RV64-LABEL: bit_32_1_z_select_i64: 2401; RV64: # %bb.0: 2402; RV64-NEXT: sext.w a3, a0 2403; RV64-NEXT: mv a0, a1 2404; RV64-NEXT: beqz a3, .LBB81_2 2405; RV64-NEXT: # %bb.1: 2406; RV64-NEXT: mv a0, a2 2407; RV64-NEXT: .LBB81_2: 2408; RV64-NEXT: ret 2409 %1 = and i64 %a, 4294967295 2410 %2 = icmp eq i64 %1, 0 2411 %3 = select i1 %2, i64 %b, i64 %c 2412 ret i64 %3 2413} 2414 2415define i64 @bit_32_1_nz_select_i64(i64 %a, i64 %b, i64 %c) { 2416; RV32-LABEL: bit_32_1_nz_select_i64: 2417; RV32: # %bb.0: 2418; RV32-NEXT: mv a1, a3 2419; RV32-NEXT: bnez a0, .LBB82_2 2420; RV32-NEXT: # %bb.1: 2421; RV32-NEXT: mv a2, a4 2422; RV32-NEXT: mv a1, a5 2423; RV32-NEXT: .LBB82_2: 2424; RV32-NEXT: mv a0, a2 2425; RV32-NEXT: ret 2426; 2427; RV64-LABEL: bit_32_1_nz_select_i64: 2428; RV64: # %bb.0: 2429; RV64-NEXT: sext.w a3, a0 2430; RV64-NEXT: mv a0, a1 2431; RV64-NEXT: bnez a3, .LBB82_2 2432; RV64-NEXT: # %bb.1: 2433; RV64-NEXT: mv a0, a2 2434; RV64-NEXT: .LBB82_2: 2435; RV64-NEXT: ret 2436 %1 = and i64 %a, 4294967295 2437 %2 = icmp ne i64 %1, 0 2438 %3 = select i1 %2, i64 %b, i64 %c 2439 ret i64 %3 2440} 2441 2442define i64 @bit_55_1_z_select_i64(i64 %a, i64 %b, i64 %c) { 2443; RV32-LABEL: bit_55_1_z_select_i64: 2444; RV32: # %bb.0: 2445; RV32-NEXT: slli a1, a1, 9 2446; RV32-NEXT: srli a1, a1, 9 2447; RV32-NEXT: or a1, a0, a1 2448; RV32-NEXT: mv a0, a2 2449; RV32-NEXT: beqz a1, .LBB83_2 2450; RV32-NEXT: # %bb.1: 2451; RV32-NEXT: mv a0, a4 2452; RV32-NEXT: mv a3, a5 2453; RV32-NEXT: .LBB83_2: 2454; RV32-NEXT: mv a1, a3 2455; RV32-NEXT: ret 2456; 2457; RV64-LABEL: bit_55_1_z_select_i64: 2458; RV64: # %bb.0: 2459; RV64-NEXT: slli a3, a0, 9 2460; RV64-NEXT: mv a0, a1 2461; RV64-NEXT: beqz a3, .LBB83_2 2462; RV64-NEXT: # %bb.1: 2463; RV64-NEXT: mv a0, a2 2464; RV64-NEXT: .LBB83_2: 2465; RV64-NEXT: ret 2466 %1 = and i64 %a, 36028797018963967 2467 %2 = icmp eq i64 %1, 0 2468 %3 = select i1 %2, i64 %b, i64 %c 2469 ret i64 %3 2470} 2471 2472define i64 @bit_55_1_nz_select_i64(i64 %a, i64 %b, i64 %c) { 2473; RV32-LABEL: bit_55_1_nz_select_i64: 2474; RV32: # %bb.0: 2475; RV32-NEXT: slli a1, a1, 9 2476; RV32-NEXT: srli a1, a1, 9 2477; RV32-NEXT: or a1, a0, a1 2478; RV32-NEXT: mv a0, a2 2479; RV32-NEXT: bnez a1, .LBB84_2 2480; RV32-NEXT: # %bb.1: 2481; RV32-NEXT: mv a0, a4 2482; RV32-NEXT: mv a3, a5 2483; RV32-NEXT: .LBB84_2: 2484; RV32-NEXT: mv a1, a3 2485; RV32-NEXT: ret 2486; 2487; RV64-LABEL: bit_55_1_nz_select_i64: 2488; RV64: # %bb.0: 2489; RV64-NEXT: slli a3, a0, 9 2490; RV64-NEXT: mv a0, a1 2491; RV64-NEXT: bnez a3, .LBB84_2 2492; RV64-NEXT: # %bb.1: 2493; RV64-NEXT: mv a0, a2 2494; RV64-NEXT: .LBB84_2: 2495; RV64-NEXT: ret 2496 %1 = and i64 %a, 36028797018963967 2497 %2 = icmp ne i64 %1, 0 2498 %3 = select i1 %2, i64 %b, i64 %c 2499 ret i64 %3 2500} 2501 2502define i64 @bit_63_1_z_select_i64(i64 %a, i64 %b, i64 %c) { 2503; RV32I-LABEL: bit_63_1_z_select_i64: 2504; RV32I: # %bb.0: 2505; RV32I-NEXT: slli a1, a1, 1 2506; RV32I-NEXT: srli a1, a1, 1 2507; RV32I-NEXT: or a1, a0, a1 2508; RV32I-NEXT: mv a0, a2 2509; RV32I-NEXT: beqz a1, .LBB85_2 2510; RV32I-NEXT: # %bb.1: 2511; RV32I-NEXT: mv a0, a4 2512; RV32I-NEXT: mv a3, a5 2513; RV32I-NEXT: .LBB85_2: 2514; RV32I-NEXT: mv a1, a3 2515; RV32I-NEXT: ret 2516; 2517; RV64-LABEL: bit_63_1_z_select_i64: 2518; RV64: # %bb.0: 2519; RV64-NEXT: slli a3, a0, 1 2520; RV64-NEXT: mv a0, a1 2521; RV64-NEXT: beqz a3, .LBB85_2 2522; RV64-NEXT: # %bb.1: 2523; RV64-NEXT: mv a0, a2 2524; RV64-NEXT: .LBB85_2: 2525; RV64-NEXT: ret 2526; 2527; RV32ZBS-LABEL: bit_63_1_z_select_i64: 2528; RV32ZBS: # %bb.0: 2529; RV32ZBS-NEXT: bclri a1, a1, 31 2530; RV32ZBS-NEXT: or a1, a0, a1 2531; RV32ZBS-NEXT: mv a0, a2 2532; RV32ZBS-NEXT: beqz a1, .LBB85_2 2533; RV32ZBS-NEXT: # %bb.1: 2534; RV32ZBS-NEXT: mv a0, a4 2535; RV32ZBS-NEXT: mv a3, a5 2536; RV32ZBS-NEXT: .LBB85_2: 2537; RV32ZBS-NEXT: mv a1, a3 2538; RV32ZBS-NEXT: ret 2539; 2540; RV32XTHEADBS-LABEL: bit_63_1_z_select_i64: 2541; RV32XTHEADBS: # %bb.0: 2542; RV32XTHEADBS-NEXT: slli a1, a1, 1 2543; RV32XTHEADBS-NEXT: srli a1, a1, 1 2544; RV32XTHEADBS-NEXT: or a1, a0, a1 2545; RV32XTHEADBS-NEXT: mv a0, a2 2546; RV32XTHEADBS-NEXT: beqz a1, .LBB85_2 2547; RV32XTHEADBS-NEXT: # %bb.1: 2548; RV32XTHEADBS-NEXT: mv a0, a4 2549; RV32XTHEADBS-NEXT: mv a3, a5 2550; RV32XTHEADBS-NEXT: .LBB85_2: 2551; RV32XTHEADBS-NEXT: mv a1, a3 2552; RV32XTHEADBS-NEXT: ret 2553 %1 = and i64 %a, 9223372036854775807 2554 %2 = icmp eq i64 %1, 0 2555 %3 = select i1 %2, i64 %b, i64 %c 2556 ret i64 %3 2557} 2558 2559define i64 @bit_63_1_nz_select_i64(i64 %a, i64 %b, i64 %c) { 2560; RV32I-LABEL: bit_63_1_nz_select_i64: 2561; RV32I: # %bb.0: 2562; RV32I-NEXT: slli a1, a1, 1 2563; RV32I-NEXT: srli a1, a1, 1 2564; RV32I-NEXT: or a1, a0, a1 2565; RV32I-NEXT: mv a0, a2 2566; RV32I-NEXT: bnez a1, .LBB86_2 2567; RV32I-NEXT: # %bb.1: 2568; RV32I-NEXT: mv a0, a4 2569; RV32I-NEXT: mv a3, a5 2570; RV32I-NEXT: .LBB86_2: 2571; RV32I-NEXT: mv a1, a3 2572; RV32I-NEXT: ret 2573; 2574; RV64-LABEL: bit_63_1_nz_select_i64: 2575; RV64: # %bb.0: 2576; RV64-NEXT: slli a3, a0, 1 2577; RV64-NEXT: mv a0, a1 2578; RV64-NEXT: bnez a3, .LBB86_2 2579; RV64-NEXT: # %bb.1: 2580; RV64-NEXT: mv a0, a2 2581; RV64-NEXT: .LBB86_2: 2582; RV64-NEXT: ret 2583; 2584; RV32ZBS-LABEL: bit_63_1_nz_select_i64: 2585; RV32ZBS: # %bb.0: 2586; RV32ZBS-NEXT: bclri a1, a1, 31 2587; RV32ZBS-NEXT: or a1, a0, a1 2588; RV32ZBS-NEXT: mv a0, a2 2589; RV32ZBS-NEXT: bnez a1, .LBB86_2 2590; RV32ZBS-NEXT: # %bb.1: 2591; RV32ZBS-NEXT: mv a0, a4 2592; RV32ZBS-NEXT: mv a3, a5 2593; RV32ZBS-NEXT: .LBB86_2: 2594; RV32ZBS-NEXT: mv a1, a3 2595; RV32ZBS-NEXT: ret 2596; 2597; RV32XTHEADBS-LABEL: bit_63_1_nz_select_i64: 2598; RV32XTHEADBS: # %bb.0: 2599; RV32XTHEADBS-NEXT: slli a1, a1, 1 2600; RV32XTHEADBS-NEXT: srli a1, a1, 1 2601; RV32XTHEADBS-NEXT: or a1, a0, a1 2602; RV32XTHEADBS-NEXT: mv a0, a2 2603; RV32XTHEADBS-NEXT: bnez a1, .LBB86_2 2604; RV32XTHEADBS-NEXT: # %bb.1: 2605; RV32XTHEADBS-NEXT: mv a0, a4 2606; RV32XTHEADBS-NEXT: mv a3, a5 2607; RV32XTHEADBS-NEXT: .LBB86_2: 2608; RV32XTHEADBS-NEXT: mv a1, a3 2609; RV32XTHEADBS-NEXT: ret 2610 %1 = and i64 %a, 9223372036854775807 2611 %2 = icmp ne i64 %1, 0 2612 %3 = select i1 %2, i64 %b, i64 %c 2613 ret i64 %3 2614} 2615 2616define i64 @bit_64_1_z_select_i64(i64 %a, i64 %b, i64 %c) { 2617; RV32-LABEL: bit_64_1_z_select_i64: 2618; RV32: # %bb.0: 2619; RV32-NEXT: or a1, a0, a1 2620; RV32-NEXT: mv a0, a2 2621; RV32-NEXT: beqz a1, .LBB87_2 2622; RV32-NEXT: # %bb.1: 2623; RV32-NEXT: mv a0, a4 2624; RV32-NEXT: mv a3, a5 2625; RV32-NEXT: .LBB87_2: 2626; RV32-NEXT: mv a1, a3 2627; RV32-NEXT: ret 2628; 2629; RV64-LABEL: bit_64_1_z_select_i64: 2630; RV64: # %bb.0: 2631; RV64-NEXT: beqz a0, .LBB87_2 2632; RV64-NEXT: # %bb.1: 2633; RV64-NEXT: mv a1, a2 2634; RV64-NEXT: .LBB87_2: 2635; RV64-NEXT: mv a0, a1 2636; RV64-NEXT: ret 2637 %1 = and i64 %a, 18446744073709551615 2638 %2 = icmp eq i64 %1, 0 2639 %3 = select i1 %2, i64 %b, i64 %c 2640 ret i64 %3 2641} 2642 2643define i64 @bit_64_1_nz_select_i64(i64 %a, i64 %b, i64 %c) { 2644; RV32-LABEL: bit_64_1_nz_select_i64: 2645; RV32: # %bb.0: 2646; RV32-NEXT: or a1, a0, a1 2647; RV32-NEXT: mv a0, a2 2648; RV32-NEXT: bnez a1, .LBB88_2 2649; RV32-NEXT: # %bb.1: 2650; RV32-NEXT: mv a0, a4 2651; RV32-NEXT: mv a3, a5 2652; RV32-NEXT: .LBB88_2: 2653; RV32-NEXT: mv a1, a3 2654; RV32-NEXT: ret 2655; 2656; RV64-LABEL: bit_64_1_nz_select_i64: 2657; RV64: # %bb.0: 2658; RV64-NEXT: bnez a0, .LBB88_2 2659; RV64-NEXT: # %bb.1: 2660; RV64-NEXT: mv a1, a2 2661; RV64-NEXT: .LBB88_2: 2662; RV64-NEXT: mv a0, a1 2663; RV64-NEXT: ret 2664 %1 = and i64 %a, 18446744073709551615 2665 %2 = icmp ne i64 %1, 0 2666 %3 = select i1 %2, i64 %b, i64 %c 2667 ret i64 %3 2668} 2669 2670define void @bit_10_1_z_branch_i32(i32 signext %0) { 2671; CHECK-LABEL: bit_10_1_z_branch_i32: 2672; CHECK: # %bb.0: 2673; CHECK-NEXT: andi a0, a0, 1023 2674; CHECK-NEXT: beqz a0, .LBB89_2 2675; CHECK-NEXT: # %bb.1: 2676; CHECK-NEXT: ret 2677; CHECK-NEXT: .LBB89_2: 2678; CHECK-NEXT: tail bar 2679 %2 = and i32 %0, 1023 2680 %3 = icmp eq i32 %2, 0 2681 br i1 %3, label %4, label %5 2682 26834: 2684 tail call void @bar() 2685 br label %5 2686 26875: 2688 ret void 2689} 2690 2691define void @bit_10_1_nz_branch_i32(i32 signext %0) { 2692; CHECK-LABEL: bit_10_1_nz_branch_i32: 2693; CHECK: # %bb.0: 2694; CHECK-NEXT: andi a0, a0, 1023 2695; CHECK-NEXT: beqz a0, .LBB90_2 2696; CHECK-NEXT: # %bb.1: 2697; CHECK-NEXT: tail bar 2698; CHECK-NEXT: .LBB90_2: 2699; CHECK-NEXT: ret 2700 %2 = and i32 %0, 1023 2701 %3 = icmp ne i32 %2, 0 2702 br i1 %3, label %4, label %5 2703 27044: 2705 tail call void @bar() 2706 br label %5 2707 27085: 2709 ret void 2710} 2711 2712define void @bit_11_1_z_branch_i32(i32 signext %0) { 2713; CHECK-LABEL: bit_11_1_z_branch_i32: 2714; CHECK: # %bb.0: 2715; CHECK-NEXT: andi a0, a0, 2047 2716; CHECK-NEXT: beqz a0, .LBB91_2 2717; CHECK-NEXT: # %bb.1: 2718; CHECK-NEXT: ret 2719; CHECK-NEXT: .LBB91_2: 2720; CHECK-NEXT: tail bar 2721 %2 = and i32 %0, 2047 2722 %3 = icmp eq i32 %2, 0 2723 br i1 %3, label %4, label %5 2724 27254: 2726 tail call void @bar() 2727 br label %5 2728 27295: 2730 ret void 2731} 2732 2733define void @bit_11_1_nz_branch_i32(i32 signext %0) { 2734; CHECK-LABEL: bit_11_1_nz_branch_i32: 2735; CHECK: # %bb.0: 2736; CHECK-NEXT: andi a0, a0, 2047 2737; CHECK-NEXT: beqz a0, .LBB92_2 2738; CHECK-NEXT: # %bb.1: 2739; CHECK-NEXT: tail bar 2740; CHECK-NEXT: .LBB92_2: 2741; CHECK-NEXT: ret 2742 %2 = and i32 %0, 2047 2743 %3 = icmp ne i32 %2, 0 2744 br i1 %3, label %4, label %5 2745 27464: 2747 tail call void @bar() 2748 br label %5 2749 27505: 2751 ret void 2752} 2753 2754define void @bit_16_1_z_branch_i32(i32 signext %0) { 2755; RV32-LABEL: bit_16_1_z_branch_i32: 2756; RV32: # %bb.0: 2757; RV32-NEXT: slli a0, a0, 16 2758; RV32-NEXT: beqz a0, .LBB93_2 2759; RV32-NEXT: # %bb.1: 2760; RV32-NEXT: ret 2761; RV32-NEXT: .LBB93_2: 2762; RV32-NEXT: tail bar 2763; 2764; RV64-LABEL: bit_16_1_z_branch_i32: 2765; RV64: # %bb.0: 2766; RV64-NEXT: slli a0, a0, 48 2767; RV64-NEXT: beqz a0, .LBB93_2 2768; RV64-NEXT: # %bb.1: 2769; RV64-NEXT: ret 2770; RV64-NEXT: .LBB93_2: 2771; RV64-NEXT: tail bar 2772 %2 = and i32 %0, 65535 2773 %3 = icmp eq i32 %2, 0 2774 br i1 %3, label %4, label %5 2775 27764: 2777 tail call void @bar() 2778 br label %5 2779 27805: 2781 ret void 2782} 2783 2784define void @bit_16_1_nz_branch_i32(i32 signext %0) { 2785; RV32-LABEL: bit_16_1_nz_branch_i32: 2786; RV32: # %bb.0: 2787; RV32-NEXT: slli a0, a0, 16 2788; RV32-NEXT: beqz a0, .LBB94_2 2789; RV32-NEXT: # %bb.1: 2790; RV32-NEXT: tail bar 2791; RV32-NEXT: .LBB94_2: 2792; RV32-NEXT: ret 2793; 2794; RV64-LABEL: bit_16_1_nz_branch_i32: 2795; RV64: # %bb.0: 2796; RV64-NEXT: slli a0, a0, 48 2797; RV64-NEXT: beqz a0, .LBB94_2 2798; RV64-NEXT: # %bb.1: 2799; RV64-NEXT: tail bar 2800; RV64-NEXT: .LBB94_2: 2801; RV64-NEXT: ret 2802 %2 = and i32 %0, 65535 2803 %3 = icmp ne i32 %2, 0 2804 br i1 %3, label %4, label %5 2805 28064: 2807 tail call void @bar() 2808 br label %5 2809 28105: 2811 ret void 2812} 2813 2814define void @bit_24_1_z_branch_i32(i32 signext %0) { 2815; RV32-LABEL: bit_24_1_z_branch_i32: 2816; RV32: # %bb.0: 2817; RV32-NEXT: slli a0, a0, 8 2818; RV32-NEXT: beqz a0, .LBB95_2 2819; RV32-NEXT: # %bb.1: 2820; RV32-NEXT: ret 2821; RV32-NEXT: .LBB95_2: 2822; RV32-NEXT: tail bar 2823; 2824; RV64-LABEL: bit_24_1_z_branch_i32: 2825; RV64: # %bb.0: 2826; RV64-NEXT: slli a0, a0, 40 2827; RV64-NEXT: beqz a0, .LBB95_2 2828; RV64-NEXT: # %bb.1: 2829; RV64-NEXT: ret 2830; RV64-NEXT: .LBB95_2: 2831; RV64-NEXT: tail bar 2832 %2 = and i32 %0, 16777215 2833 %3 = icmp eq i32 %2, 0 2834 br i1 %3, label %4, label %5 2835 28364: 2837 tail call void @bar() 2838 br label %5 2839 28405: 2841 ret void 2842} 2843 2844define void @bit_24_1_nz_branch_i32(i32 signext %0) { 2845; RV32-LABEL: bit_24_1_nz_branch_i32: 2846; RV32: # %bb.0: 2847; RV32-NEXT: slli a0, a0, 8 2848; RV32-NEXT: beqz a0, .LBB96_2 2849; RV32-NEXT: # %bb.1: 2850; RV32-NEXT: tail bar 2851; RV32-NEXT: .LBB96_2: 2852; RV32-NEXT: ret 2853; 2854; RV64-LABEL: bit_24_1_nz_branch_i32: 2855; RV64: # %bb.0: 2856; RV64-NEXT: slli a0, a0, 40 2857; RV64-NEXT: beqz a0, .LBB96_2 2858; RV64-NEXT: # %bb.1: 2859; RV64-NEXT: tail bar 2860; RV64-NEXT: .LBB96_2: 2861; RV64-NEXT: ret 2862 %2 = and i32 %0, 16777215 2863 %3 = icmp ne i32 %2, 0 2864 br i1 %3, label %4, label %5 2865 28664: 2867 tail call void @bar() 2868 br label %5 2869 28705: 2871 ret void 2872} 2873 2874define void @bit_31_1_z_branch_i32(i32 signext %0) { 2875; RV32-LABEL: bit_31_1_z_branch_i32: 2876; RV32: # %bb.0: 2877; RV32-NEXT: slli a0, a0, 1 2878; RV32-NEXT: beqz a0, .LBB97_2 2879; RV32-NEXT: # %bb.1: 2880; RV32-NEXT: ret 2881; RV32-NEXT: .LBB97_2: 2882; RV32-NEXT: tail bar 2883; 2884; RV64-LABEL: bit_31_1_z_branch_i32: 2885; RV64: # %bb.0: 2886; RV64-NEXT: slli a0, a0, 33 2887; RV64-NEXT: beqz a0, .LBB97_2 2888; RV64-NEXT: # %bb.1: 2889; RV64-NEXT: ret 2890; RV64-NEXT: .LBB97_2: 2891; RV64-NEXT: tail bar 2892 %2 = and i32 %0, 2147483647 2893 %3 = icmp eq i32 %2, 0 2894 br i1 %3, label %4, label %5 2895 28964: 2897 tail call void @bar() 2898 br label %5 2899 29005: 2901 ret void 2902} 2903 2904define void @bit_31_1_nz_branch_i32(i32 signext %0) { 2905; RV32-LABEL: bit_31_1_nz_branch_i32: 2906; RV32: # %bb.0: 2907; RV32-NEXT: slli a0, a0, 1 2908; RV32-NEXT: beqz a0, .LBB98_2 2909; RV32-NEXT: # %bb.1: 2910; RV32-NEXT: tail bar 2911; RV32-NEXT: .LBB98_2: 2912; RV32-NEXT: ret 2913; 2914; RV64-LABEL: bit_31_1_nz_branch_i32: 2915; RV64: # %bb.0: 2916; RV64-NEXT: slli a0, a0, 33 2917; RV64-NEXT: beqz a0, .LBB98_2 2918; RV64-NEXT: # %bb.1: 2919; RV64-NEXT: tail bar 2920; RV64-NEXT: .LBB98_2: 2921; RV64-NEXT: ret 2922 %2 = and i32 %0, 2147483647 2923 %3 = icmp ne i32 %2, 0 2924 br i1 %3, label %4, label %5 2925 29264: 2927 tail call void @bar() 2928 br label %5 2929 29305: 2931 ret void 2932} 2933 2934define void @bit_32_1_z_branch_i32(i32 signext %0) { 2935; CHECK-LABEL: bit_32_1_z_branch_i32: 2936; CHECK: # %bb.0: 2937; CHECK-NEXT: beqz a0, .LBB99_2 2938; CHECK-NEXT: # %bb.1: 2939; CHECK-NEXT: ret 2940; CHECK-NEXT: .LBB99_2: 2941; CHECK-NEXT: tail bar 2942 %2 = and i32 %0, 4294967295 2943 %3 = icmp eq i32 %2, 0 2944 br i1 %3, label %4, label %5 2945 29464: 2947 tail call void @bar() 2948 br label %5 2949 29505: 2951 ret void 2952} 2953 2954define void @bit_32_1_nz_branch_i32(i32 signext %0) { 2955; CHECK-LABEL: bit_32_1_nz_branch_i32: 2956; CHECK: # %bb.0: 2957; CHECK-NEXT: beqz a0, .LBB100_2 2958; CHECK-NEXT: # %bb.1: 2959; CHECK-NEXT: tail bar 2960; CHECK-NEXT: .LBB100_2: 2961; CHECK-NEXT: ret 2962 %2 = and i32 %0, 4294967295 2963 %3 = icmp ne i32 %2, 0 2964 br i1 %3, label %4, label %5 2965 29664: 2967 tail call void @bar() 2968 br label %5 2969 29705: 2971 ret void 2972} 2973 2974 2975define void @bit_10_1_z_branch_i64(i64 %0) { 2976; CHECK-LABEL: bit_10_1_z_branch_i64: 2977; CHECK: # %bb.0: 2978; CHECK-NEXT: andi a0, a0, 1023 2979; CHECK-NEXT: beqz a0, .LBB101_2 2980; CHECK-NEXT: # %bb.1: 2981; CHECK-NEXT: ret 2982; CHECK-NEXT: .LBB101_2: 2983; CHECK-NEXT: tail bar 2984 %2 = and i64 %0, 1023 2985 %3 = icmp eq i64 %2, 0 2986 br i1 %3, label %4, label %5 2987 29884: 2989 tail call void @bar() 2990 br label %5 2991 29925: 2993 ret void 2994} 2995 2996define void @bit_10_1_nz_branch_i64(i64 %0) { 2997; CHECK-LABEL: bit_10_1_nz_branch_i64: 2998; CHECK: # %bb.0: 2999; CHECK-NEXT: andi a0, a0, 1023 3000; CHECK-NEXT: beqz a0, .LBB102_2 3001; CHECK-NEXT: # %bb.1: 3002; CHECK-NEXT: tail bar 3003; CHECK-NEXT: .LBB102_2: 3004; CHECK-NEXT: ret 3005 %2 = and i64 %0, 1023 3006 %3 = icmp ne i64 %2, 0 3007 br i1 %3, label %4, label %5 3008 30094: 3010 tail call void @bar() 3011 br label %5 3012 30135: 3014 ret void 3015} 3016 3017define void @bit_11_1_z_branch_i64(i64 %0) { 3018; CHECK-LABEL: bit_11_1_z_branch_i64: 3019; CHECK: # %bb.0: 3020; CHECK-NEXT: andi a0, a0, 2047 3021; CHECK-NEXT: beqz a0, .LBB103_2 3022; CHECK-NEXT: # %bb.1: 3023; CHECK-NEXT: ret 3024; CHECK-NEXT: .LBB103_2: 3025; CHECK-NEXT: tail bar 3026 %2 = and i64 %0, 2047 3027 %3 = icmp eq i64 %2, 0 3028 br i1 %3, label %4, label %5 3029 30304: 3031 tail call void @bar() 3032 br label %5 3033 30345: 3035 ret void 3036} 3037 3038define void @bit_11_1_nz_branch_i64(i64 %0) { 3039; CHECK-LABEL: bit_11_1_nz_branch_i64: 3040; CHECK: # %bb.0: 3041; CHECK-NEXT: andi a0, a0, 2047 3042; CHECK-NEXT: beqz a0, .LBB104_2 3043; CHECK-NEXT: # %bb.1: 3044; CHECK-NEXT: tail bar 3045; CHECK-NEXT: .LBB104_2: 3046; CHECK-NEXT: ret 3047 %2 = and i64 %0, 2047 3048 %3 = icmp ne i64 %2, 0 3049 br i1 %3, label %4, label %5 3050 30514: 3052 tail call void @bar() 3053 br label %5 3054 30555: 3056 ret void 3057} 3058 3059define void @bit_16_1_z_branch_i64(i64 %0) { 3060; RV32-LABEL: bit_16_1_z_branch_i64: 3061; RV32: # %bb.0: 3062; RV32-NEXT: slli a0, a0, 16 3063; RV32-NEXT: beqz a0, .LBB105_2 3064; RV32-NEXT: # %bb.1: 3065; RV32-NEXT: ret 3066; RV32-NEXT: .LBB105_2: 3067; RV32-NEXT: tail bar 3068; 3069; RV64-LABEL: bit_16_1_z_branch_i64: 3070; RV64: # %bb.0: 3071; RV64-NEXT: slli a0, a0, 48 3072; RV64-NEXT: beqz a0, .LBB105_2 3073; RV64-NEXT: # %bb.1: 3074; RV64-NEXT: ret 3075; RV64-NEXT: .LBB105_2: 3076; RV64-NEXT: tail bar 3077 %2 = and i64 %0, 65535 3078 %3 = icmp eq i64 %2, 0 3079 br i1 %3, label %4, label %5 3080 30814: 3082 tail call void @bar() 3083 br label %5 3084 30855: 3086 ret void 3087} 3088 3089define void @bit_16_1_nz_branch_i64(i64 %0) { 3090; RV32-LABEL: bit_16_1_nz_branch_i64: 3091; RV32: # %bb.0: 3092; RV32-NEXT: slli a0, a0, 16 3093; RV32-NEXT: beqz a0, .LBB106_2 3094; RV32-NEXT: # %bb.1: 3095; RV32-NEXT: tail bar 3096; RV32-NEXT: .LBB106_2: 3097; RV32-NEXT: ret 3098; 3099; RV64-LABEL: bit_16_1_nz_branch_i64: 3100; RV64: # %bb.0: 3101; RV64-NEXT: slli a0, a0, 48 3102; RV64-NEXT: beqz a0, .LBB106_2 3103; RV64-NEXT: # %bb.1: 3104; RV64-NEXT: tail bar 3105; RV64-NEXT: .LBB106_2: 3106; RV64-NEXT: ret 3107 %2 = and i64 %0, 65535 3108 %3 = icmp ne i64 %2, 0 3109 br i1 %3, label %4, label %5 3110 31114: 3112 tail call void @bar() 3113 br label %5 3114 31155: 3116 ret void 3117} 3118 3119define void @bit_24_1_z_branch_i64(i64 %0) { 3120; RV32-LABEL: bit_24_1_z_branch_i64: 3121; RV32: # %bb.0: 3122; RV32-NEXT: slli a0, a0, 8 3123; RV32-NEXT: beqz a0, .LBB107_2 3124; RV32-NEXT: # %bb.1: 3125; RV32-NEXT: ret 3126; RV32-NEXT: .LBB107_2: 3127; RV32-NEXT: tail bar 3128; 3129; RV64-LABEL: bit_24_1_z_branch_i64: 3130; RV64: # %bb.0: 3131; RV64-NEXT: slli a0, a0, 40 3132; RV64-NEXT: beqz a0, .LBB107_2 3133; RV64-NEXT: # %bb.1: 3134; RV64-NEXT: ret 3135; RV64-NEXT: .LBB107_2: 3136; RV64-NEXT: tail bar 3137 %2 = and i64 %0, 16777215 3138 %3 = icmp eq i64 %2, 0 3139 br i1 %3, label %4, label %5 3140 31414: 3142 tail call void @bar() 3143 br label %5 3144 31455: 3146 ret void 3147} 3148 3149define void @bit_24_1_nz_branch_i64(i64 %0) { 3150; RV32-LABEL: bit_24_1_nz_branch_i64: 3151; RV32: # %bb.0: 3152; RV32-NEXT: slli a0, a0, 8 3153; RV32-NEXT: beqz a0, .LBB108_2 3154; RV32-NEXT: # %bb.1: 3155; RV32-NEXT: tail bar 3156; RV32-NEXT: .LBB108_2: 3157; RV32-NEXT: ret 3158; 3159; RV64-LABEL: bit_24_1_nz_branch_i64: 3160; RV64: # %bb.0: 3161; RV64-NEXT: slli a0, a0, 40 3162; RV64-NEXT: beqz a0, .LBB108_2 3163; RV64-NEXT: # %bb.1: 3164; RV64-NEXT: tail bar 3165; RV64-NEXT: .LBB108_2: 3166; RV64-NEXT: ret 3167 %2 = and i64 %0, 16777215 3168 %3 = icmp ne i64 %2, 0 3169 br i1 %3, label %4, label %5 3170 31714: 3172 tail call void @bar() 3173 br label %5 3174 31755: 3176 ret void 3177} 3178 3179define void @bit_31_1_z_branch_i64(i64 %0) { 3180; RV32-LABEL: bit_31_1_z_branch_i64: 3181; RV32: # %bb.0: 3182; RV32-NEXT: slli a0, a0, 1 3183; RV32-NEXT: beqz a0, .LBB109_2 3184; RV32-NEXT: # %bb.1: 3185; RV32-NEXT: ret 3186; RV32-NEXT: .LBB109_2: 3187; RV32-NEXT: tail bar 3188; 3189; RV64-LABEL: bit_31_1_z_branch_i64: 3190; RV64: # %bb.0: 3191; RV64-NEXT: slli a0, a0, 33 3192; RV64-NEXT: beqz a0, .LBB109_2 3193; RV64-NEXT: # %bb.1: 3194; RV64-NEXT: ret 3195; RV64-NEXT: .LBB109_2: 3196; RV64-NEXT: tail bar 3197 %2 = and i64 %0, 2147483647 3198 %3 = icmp eq i64 %2, 0 3199 br i1 %3, label %4, label %5 3200 32014: 3202 tail call void @bar() 3203 br label %5 3204 32055: 3206 ret void 3207} 3208 3209define void @bit_31_1_nz_branch_i64(i64 %0) { 3210; RV32-LABEL: bit_31_1_nz_branch_i64: 3211; RV32: # %bb.0: 3212; RV32-NEXT: slli a0, a0, 1 3213; RV32-NEXT: beqz a0, .LBB110_2 3214; RV32-NEXT: # %bb.1: 3215; RV32-NEXT: tail bar 3216; RV32-NEXT: .LBB110_2: 3217; RV32-NEXT: ret 3218; 3219; RV64-LABEL: bit_31_1_nz_branch_i64: 3220; RV64: # %bb.0: 3221; RV64-NEXT: slli a0, a0, 33 3222; RV64-NEXT: beqz a0, .LBB110_2 3223; RV64-NEXT: # %bb.1: 3224; RV64-NEXT: tail bar 3225; RV64-NEXT: .LBB110_2: 3226; RV64-NEXT: ret 3227 %2 = and i64 %0, 2147483647 3228 %3 = icmp ne i64 %2, 0 3229 br i1 %3, label %4, label %5 3230 32314: 3232 tail call void @bar() 3233 br label %5 3234 32355: 3236 ret void 3237} 3238 3239define void @bit_32_1_z_branch_i64(i64 %0) { 3240; RV32-LABEL: bit_32_1_z_branch_i64: 3241; RV32: # %bb.0: 3242; RV32-NEXT: beqz a0, .LBB111_2 3243; RV32-NEXT: # %bb.1: 3244; RV32-NEXT: ret 3245; RV32-NEXT: .LBB111_2: 3246; RV32-NEXT: tail bar 3247; 3248; RV64-LABEL: bit_32_1_z_branch_i64: 3249; RV64: # %bb.0: 3250; RV64-NEXT: sext.w a0, a0 3251; RV64-NEXT: beqz a0, .LBB111_2 3252; RV64-NEXT: # %bb.1: 3253; RV64-NEXT: ret 3254; RV64-NEXT: .LBB111_2: 3255; RV64-NEXT: tail bar 3256 %2 = and i64 %0, 4294967295 3257 %3 = icmp eq i64 %2, 0 3258 br i1 %3, label %4, label %5 3259 32604: 3261 tail call void @bar() 3262 br label %5 3263 32645: 3265 ret void 3266} 3267 3268define void @bit_32_1_nz_branch_i64(i64 %0) { 3269; RV32-LABEL: bit_32_1_nz_branch_i64: 3270; RV32: # %bb.0: 3271; RV32-NEXT: beqz a0, .LBB112_2 3272; RV32-NEXT: # %bb.1: 3273; RV32-NEXT: tail bar 3274; RV32-NEXT: .LBB112_2: 3275; RV32-NEXT: ret 3276; 3277; RV64-LABEL: bit_32_1_nz_branch_i64: 3278; RV64: # %bb.0: 3279; RV64-NEXT: sext.w a0, a0 3280; RV64-NEXT: beqz a0, .LBB112_2 3281; RV64-NEXT: # %bb.1: 3282; RV64-NEXT: tail bar 3283; RV64-NEXT: .LBB112_2: 3284; RV64-NEXT: ret 3285 %2 = and i64 %0, 4294967295 3286 %3 = icmp ne i64 %2, 0 3287 br i1 %3, label %4, label %5 3288 32894: 3290 tail call void @bar() 3291 br label %5 3292 32935: 3294 ret void 3295} 3296 3297define void @bit_62_1_z_branch_i64(i64 %0) { 3298; RV32-LABEL: bit_62_1_z_branch_i64: 3299; RV32: # %bb.0: 3300; RV32-NEXT: slli a1, a1, 2 3301; RV32-NEXT: srli a1, a1, 2 3302; RV32-NEXT: or a0, a0, a1 3303; RV32-NEXT: beqz a0, .LBB113_2 3304; RV32-NEXT: # %bb.1: 3305; RV32-NEXT: ret 3306; RV32-NEXT: .LBB113_2: 3307; RV32-NEXT: tail bar 3308; 3309; RV64-LABEL: bit_62_1_z_branch_i64: 3310; RV64: # %bb.0: 3311; RV64-NEXT: slli a0, a0, 2 3312; RV64-NEXT: beqz a0, .LBB113_2 3313; RV64-NEXT: # %bb.1: 3314; RV64-NEXT: ret 3315; RV64-NEXT: .LBB113_2: 3316; RV64-NEXT: tail bar 3317 %2 = and i64 %0, 4611686018427387903 3318 %3 = icmp eq i64 %2, 0 3319 br i1 %3, label %4, label %5 3320 33214: 3322 tail call void @bar() 3323 br label %5 3324 33255: 3326 ret void 3327} 3328 3329define void @bit_62_1_nz_branch_i64(i64 %0) { 3330; RV32-LABEL: bit_62_1_nz_branch_i64: 3331; RV32: # %bb.0: 3332; RV32-NEXT: slli a1, a1, 2 3333; RV32-NEXT: srli a1, a1, 2 3334; RV32-NEXT: or a0, a0, a1 3335; RV32-NEXT: beqz a0, .LBB114_2 3336; RV32-NEXT: # %bb.1: 3337; RV32-NEXT: tail bar 3338; RV32-NEXT: .LBB114_2: 3339; RV32-NEXT: ret 3340; 3341; RV64-LABEL: bit_62_1_nz_branch_i64: 3342; RV64: # %bb.0: 3343; RV64-NEXT: slli a0, a0, 2 3344; RV64-NEXT: beqz a0, .LBB114_2 3345; RV64-NEXT: # %bb.1: 3346; RV64-NEXT: tail bar 3347; RV64-NEXT: .LBB114_2: 3348; RV64-NEXT: ret 3349 %2 = and i64 %0, 4611686018427387903 3350 %3 = icmp ne i64 %2, 0 3351 br i1 %3, label %4, label %5 3352 33534: 3354 tail call void @bar() 3355 br label %5 3356 33575: 3358 ret void 3359} 3360 3361define void @bit_63_1_z_branch_i64(i64 %0) { 3362; RV32I-LABEL: bit_63_1_z_branch_i64: 3363; RV32I: # %bb.0: 3364; RV32I-NEXT: slli a1, a1, 1 3365; RV32I-NEXT: srli a1, a1, 1 3366; RV32I-NEXT: or a0, a0, a1 3367; RV32I-NEXT: beqz a0, .LBB115_2 3368; RV32I-NEXT: # %bb.1: 3369; RV32I-NEXT: ret 3370; RV32I-NEXT: .LBB115_2: 3371; RV32I-NEXT: tail bar 3372; 3373; RV64-LABEL: bit_63_1_z_branch_i64: 3374; RV64: # %bb.0: 3375; RV64-NEXT: slli a0, a0, 1 3376; RV64-NEXT: beqz a0, .LBB115_2 3377; RV64-NEXT: # %bb.1: 3378; RV64-NEXT: ret 3379; RV64-NEXT: .LBB115_2: 3380; RV64-NEXT: tail bar 3381; 3382; RV32ZBS-LABEL: bit_63_1_z_branch_i64: 3383; RV32ZBS: # %bb.0: 3384; RV32ZBS-NEXT: bclri a1, a1, 31 3385; RV32ZBS-NEXT: or a0, a0, a1 3386; RV32ZBS-NEXT: beqz a0, .LBB115_2 3387; RV32ZBS-NEXT: # %bb.1: 3388; RV32ZBS-NEXT: ret 3389; RV32ZBS-NEXT: .LBB115_2: 3390; RV32ZBS-NEXT: tail bar 3391; 3392; RV32XTHEADBS-LABEL: bit_63_1_z_branch_i64: 3393; RV32XTHEADBS: # %bb.0: 3394; RV32XTHEADBS-NEXT: slli a1, a1, 1 3395; RV32XTHEADBS-NEXT: srli a1, a1, 1 3396; RV32XTHEADBS-NEXT: or a0, a0, a1 3397; RV32XTHEADBS-NEXT: beqz a0, .LBB115_2 3398; RV32XTHEADBS-NEXT: # %bb.1: 3399; RV32XTHEADBS-NEXT: ret 3400; RV32XTHEADBS-NEXT: .LBB115_2: 3401; RV32XTHEADBS-NEXT: tail bar 3402 %2 = and i64 %0, 9223372036854775807 3403 %3 = icmp eq i64 %2, 0 3404 br i1 %3, label %4, label %5 3405 34064: 3407 tail call void @bar() 3408 br label %5 3409 34105: 3411 ret void 3412} 3413 3414define void @bit_63_1_nz_branch_i64(i64 %0) { 3415; RV32I-LABEL: bit_63_1_nz_branch_i64: 3416; RV32I: # %bb.0: 3417; RV32I-NEXT: slli a1, a1, 1 3418; RV32I-NEXT: srli a1, a1, 1 3419; RV32I-NEXT: or a0, a0, a1 3420; RV32I-NEXT: beqz a0, .LBB116_2 3421; RV32I-NEXT: # %bb.1: 3422; RV32I-NEXT: tail bar 3423; RV32I-NEXT: .LBB116_2: 3424; RV32I-NEXT: ret 3425; 3426; RV64-LABEL: bit_63_1_nz_branch_i64: 3427; RV64: # %bb.0: 3428; RV64-NEXT: slli a0, a0, 1 3429; RV64-NEXT: beqz a0, .LBB116_2 3430; RV64-NEXT: # %bb.1: 3431; RV64-NEXT: tail bar 3432; RV64-NEXT: .LBB116_2: 3433; RV64-NEXT: ret 3434; 3435; RV32ZBS-LABEL: bit_63_1_nz_branch_i64: 3436; RV32ZBS: # %bb.0: 3437; RV32ZBS-NEXT: bclri a1, a1, 31 3438; RV32ZBS-NEXT: or a0, a0, a1 3439; RV32ZBS-NEXT: beqz a0, .LBB116_2 3440; RV32ZBS-NEXT: # %bb.1: 3441; RV32ZBS-NEXT: tail bar 3442; RV32ZBS-NEXT: .LBB116_2: 3443; RV32ZBS-NEXT: ret 3444; 3445; RV32XTHEADBS-LABEL: bit_63_1_nz_branch_i64: 3446; RV32XTHEADBS: # %bb.0: 3447; RV32XTHEADBS-NEXT: slli a1, a1, 1 3448; RV32XTHEADBS-NEXT: srli a1, a1, 1 3449; RV32XTHEADBS-NEXT: or a0, a0, a1 3450; RV32XTHEADBS-NEXT: beqz a0, .LBB116_2 3451; RV32XTHEADBS-NEXT: # %bb.1: 3452; RV32XTHEADBS-NEXT: tail bar 3453; RV32XTHEADBS-NEXT: .LBB116_2: 3454; RV32XTHEADBS-NEXT: ret 3455 %2 = and i64 %0, 9223372036854775807 3456 %3 = icmp ne i64 %2, 0 3457 br i1 %3, label %4, label %5 3458 34594: 3460 tail call void @bar() 3461 br label %5 3462 34635: 3464 ret void 3465} 3466 3467define void @bit_64_1_z_branch_i64(i64 %0) { 3468; RV32-LABEL: bit_64_1_z_branch_i64: 3469; RV32: # %bb.0: 3470; RV32-NEXT: or a0, a0, a1 3471; RV32-NEXT: beqz a0, .LBB117_2 3472; RV32-NEXT: # %bb.1: 3473; RV32-NEXT: ret 3474; RV32-NEXT: .LBB117_2: 3475; RV32-NEXT: tail bar 3476; 3477; RV64-LABEL: bit_64_1_z_branch_i64: 3478; RV64: # %bb.0: 3479; RV64-NEXT: beqz a0, .LBB117_2 3480; RV64-NEXT: # %bb.1: 3481; RV64-NEXT: ret 3482; RV64-NEXT: .LBB117_2: 3483; RV64-NEXT: tail bar 3484 %2 = and i64 %0, 18446744073709551615 3485 %3 = icmp eq i64 %2, 0 3486 br i1 %3, label %4, label %5 3487 34884: 3489 tail call void @bar() 3490 br label %5 3491 34925: 3493 ret void 3494} 3495 3496define void @bit_64_1_nz_branch_i64(i64 %0) { 3497; RV32-LABEL: bit_64_1_nz_branch_i64: 3498; RV32: # %bb.0: 3499; RV32-NEXT: or a0, a0, a1 3500; RV32-NEXT: beqz a0, .LBB118_2 3501; RV32-NEXT: # %bb.1: 3502; RV32-NEXT: tail bar 3503; RV32-NEXT: .LBB118_2: 3504; RV32-NEXT: ret 3505; 3506; RV64-LABEL: bit_64_1_nz_branch_i64: 3507; RV64: # %bb.0: 3508; RV64-NEXT: beqz a0, .LBB118_2 3509; RV64-NEXT: # %bb.1: 3510; RV64-NEXT: tail bar 3511; RV64-NEXT: .LBB118_2: 3512; RV64-NEXT: ret 3513 %2 = and i64 %0, 18446744073709551615 3514 %3 = icmp ne i64 %2, 0 3515 br i1 %3, label %4, label %5 3516 35174: 3518 tail call void @bar() 3519 br label %5 3520 35215: 3522 ret void 3523} 3524