1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs -no-integrated-as < %s \ 3; RUN: | FileCheck -check-prefix=RV32I %s 4; RUN: llc -mtriple=riscv64 -verify-machineinstrs -no-integrated-as < %s \ 5; RUN: | FileCheck -check-prefix=RV64I %s 6 7; These test that we can use both the architectural names (x*) and the ABI names 8; (a*, s*, t* etc) to refer to registers in inline asm constraint lists. In each 9; case, the named register should be used for the source register of the `addi`. 10; It is very likely that `a0` will be chosen as the designation register, but 11; this is left to the compiler to choose. 12; 13; The inline assembly will, by default, contain the ABI names for the registers. 14; 15; Parenthesised registers in comments are the other aliases for this register. 16 17; NOTE: This test has to pass in 0 to the inline asm, because that's the only 18; value `x0` (`zero`) can take. 19define i32 @explicit_register_x0() nounwind { 20; RV32I-LABEL: explicit_register_x0: 21; RV32I: # %bb.0: 22; RV32I-NEXT: #APP 23; RV32I-NEXT: addi a0, zero, 0 24; RV32I-NEXT: #NO_APP 25; RV32I-NEXT: ret 26; 27; RV64I-LABEL: explicit_register_x0: 28; RV64I: # %bb.0: 29; RV64I-NEXT: #APP 30; RV64I-NEXT: addi a0, zero, 0 31; RV64I-NEXT: #NO_APP 32; RV64I-NEXT: ret 33 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x0}"(i32 0) 34 ret i32 %1 35} 36 37; NOTE: This test has to pass in 0 to the inline asm, because that's the only 38; value that `zero` (`x0`) can take. 39define i32 @explicit_register_zero() nounwind { 40; RV32I-LABEL: explicit_register_zero: 41; RV32I: # %bb.0: 42; RV32I-NEXT: #APP 43; RV32I-NEXT: addi a0, zero, 0 44; RV32I-NEXT: #NO_APP 45; RV32I-NEXT: ret 46; 47; RV64I-LABEL: explicit_register_zero: 48; RV64I: # %bb.0: 49; RV64I-NEXT: #APP 50; RV64I-NEXT: addi a0, zero, 0 51; RV64I-NEXT: #NO_APP 52; RV64I-NEXT: ret 53 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{zero}"(i32 0) 54 ret i32 %1 55} 56 57; NOTE: This test uses `x1` (`ra`) as an input, so it should be saved. 58define i32 @explicit_register_x1(i32 %a) nounwind { 59; RV32I-LABEL: explicit_register_x1: 60; RV32I: # %bb.0: 61; RV32I-NEXT: addi sp, sp, -16 62; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 63; RV32I-NEXT: mv ra, a0 64; RV32I-NEXT: #APP 65; RV32I-NEXT: addi a0, ra, 0 66; RV32I-NEXT: #NO_APP 67; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 68; RV32I-NEXT: addi sp, sp, 16 69; RV32I-NEXT: ret 70; 71; RV64I-LABEL: explicit_register_x1: 72; RV64I: # %bb.0: 73; RV64I-NEXT: addi sp, sp, -16 74; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 75; RV64I-NEXT: mv ra, a0 76; RV64I-NEXT: #APP 77; RV64I-NEXT: addi a0, ra, 0 78; RV64I-NEXT: #NO_APP 79; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 80; RV64I-NEXT: addi sp, sp, 16 81; RV64I-NEXT: ret 82 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x1}"(i32 %a) 83 ret i32 %1 84} 85 86; NOTE: This test uses `ra` (`x1`) as an input, so it should be saved. 87define i32 @explicit_register_ra(i32 %a) nounwind { 88; RV32I-LABEL: explicit_register_ra: 89; RV32I: # %bb.0: 90; RV32I-NEXT: addi sp, sp, -16 91; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 92; RV32I-NEXT: mv ra, a0 93; RV32I-NEXT: #APP 94; RV32I-NEXT: addi a0, ra, 0 95; RV32I-NEXT: #NO_APP 96; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 97; RV32I-NEXT: addi sp, sp, 16 98; RV32I-NEXT: ret 99; 100; RV64I-LABEL: explicit_register_ra: 101; RV64I: # %bb.0: 102; RV64I-NEXT: addi sp, sp, -16 103; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 104; RV64I-NEXT: mv ra, a0 105; RV64I-NEXT: #APP 106; RV64I-NEXT: addi a0, ra, 0 107; RV64I-NEXT: #NO_APP 108; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 109; RV64I-NEXT: addi sp, sp, 16 110; RV64I-NEXT: ret 111 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{ra}"(i32 %a) 112 ret i32 %1 113} 114 115define i32 @explicit_register_x2(i32 %a) nounwind { 116; RV32I-LABEL: explicit_register_x2: 117; RV32I: # %bb.0: 118; RV32I-NEXT: mv sp, a0 119; RV32I-NEXT: #APP 120; RV32I-NEXT: addi a0, sp, 0 121; RV32I-NEXT: #NO_APP 122; RV32I-NEXT: ret 123; 124; RV64I-LABEL: explicit_register_x2: 125; RV64I: # %bb.0: 126; RV64I-NEXT: mv sp, a0 127; RV64I-NEXT: #APP 128; RV64I-NEXT: addi a0, sp, 0 129; RV64I-NEXT: #NO_APP 130; RV64I-NEXT: ret 131 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x2}"(i32 %a) 132 ret i32 %1 133} 134 135define i32 @explicit_register_sp(i32 %a) nounwind { 136; RV32I-LABEL: explicit_register_sp: 137; RV32I: # %bb.0: 138; RV32I-NEXT: mv sp, a0 139; RV32I-NEXT: #APP 140; RV32I-NEXT: addi a0, sp, 0 141; RV32I-NEXT: #NO_APP 142; RV32I-NEXT: ret 143; 144; RV64I-LABEL: explicit_register_sp: 145; RV64I: # %bb.0: 146; RV64I-NEXT: mv sp, a0 147; RV64I-NEXT: #APP 148; RV64I-NEXT: addi a0, sp, 0 149; RV64I-NEXT: #NO_APP 150; RV64I-NEXT: ret 151 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{sp}"(i32 %a) 152 ret i32 %1 153} 154 155; NOTE: This test uses `x3` (`gp`) as an input, so it should be saved. 156define i32 @explicit_register_x3(i32 %a) nounwind { 157; RV32I-LABEL: explicit_register_x3: 158; RV32I: # %bb.0: 159; RV32I-NEXT: mv gp, a0 160; RV32I-NEXT: #APP 161; RV32I-NEXT: addi a0, gp, 0 162; RV32I-NEXT: #NO_APP 163; RV32I-NEXT: ret 164; 165; RV64I-LABEL: explicit_register_x3: 166; RV64I: # %bb.0: 167; RV64I-NEXT: mv gp, a0 168; RV64I-NEXT: #APP 169; RV64I-NEXT: addi a0, gp, 0 170; RV64I-NEXT: #NO_APP 171; RV64I-NEXT: ret 172 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x3}"(i32 %a) 173 ret i32 %1 174} 175 176; NOTE: This test uses `gp` (`x3`) as an input, so it should be saved. 177define i32 @explicit_register_gp(i32 %a) nounwind { 178; RV32I-LABEL: explicit_register_gp: 179; RV32I: # %bb.0: 180; RV32I-NEXT: mv gp, a0 181; RV32I-NEXT: #APP 182; RV32I-NEXT: addi a0, gp, 0 183; RV32I-NEXT: #NO_APP 184; RV32I-NEXT: ret 185; 186; RV64I-LABEL: explicit_register_gp: 187; RV64I: # %bb.0: 188; RV64I-NEXT: mv gp, a0 189; RV64I-NEXT: #APP 190; RV64I-NEXT: addi a0, gp, 0 191; RV64I-NEXT: #NO_APP 192; RV64I-NEXT: ret 193 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{gp}"(i32 %a) 194 ret i32 %1 195} 196 197; NOTE: This test uses `x4` (`tp`) as an input, so it should be saved. 198define i32 @explicit_register_x4(i32 %a) nounwind { 199; RV32I-LABEL: explicit_register_x4: 200; RV32I: # %bb.0: 201; RV32I-NEXT: mv tp, a0 202; RV32I-NEXT: #APP 203; RV32I-NEXT: addi a0, tp, 0 204; RV32I-NEXT: #NO_APP 205; RV32I-NEXT: ret 206; 207; RV64I-LABEL: explicit_register_x4: 208; RV64I: # %bb.0: 209; RV64I-NEXT: mv tp, a0 210; RV64I-NEXT: #APP 211; RV64I-NEXT: addi a0, tp, 0 212; RV64I-NEXT: #NO_APP 213; RV64I-NEXT: ret 214 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x4}"(i32 %a) 215 ret i32 %1 216} 217 218; NOTE: This test uses `tp` (`x4`) as an input, so it should be saved. 219define i32 @explicit_register_tp(i32 %a) nounwind { 220; RV32I-LABEL: explicit_register_tp: 221; RV32I: # %bb.0: 222; RV32I-NEXT: mv tp, a0 223; RV32I-NEXT: #APP 224; RV32I-NEXT: addi a0, tp, 0 225; RV32I-NEXT: #NO_APP 226; RV32I-NEXT: ret 227; 228; RV64I-LABEL: explicit_register_tp: 229; RV64I: # %bb.0: 230; RV64I-NEXT: mv tp, a0 231; RV64I-NEXT: #APP 232; RV64I-NEXT: addi a0, tp, 0 233; RV64I-NEXT: #NO_APP 234; RV64I-NEXT: ret 235 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{tp}"(i32 %a) 236 ret i32 %1 237} 238 239define i32 @explicit_register_x5(i32 %a) nounwind { 240; RV32I-LABEL: explicit_register_x5: 241; RV32I: # %bb.0: 242; RV32I-NEXT: mv t0, a0 243; RV32I-NEXT: #APP 244; RV32I-NEXT: addi a0, t0, 0 245; RV32I-NEXT: #NO_APP 246; RV32I-NEXT: ret 247; 248; RV64I-LABEL: explicit_register_x5: 249; RV64I: # %bb.0: 250; RV64I-NEXT: mv t0, a0 251; RV64I-NEXT: #APP 252; RV64I-NEXT: addi a0, t0, 0 253; RV64I-NEXT: #NO_APP 254; RV64I-NEXT: ret 255 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x5}"(i32 %a) 256 ret i32 %1 257} 258 259define i32 @explicit_register_t0(i32 %a) nounwind { 260; RV32I-LABEL: explicit_register_t0: 261; RV32I: # %bb.0: 262; RV32I-NEXT: mv t0, a0 263; RV32I-NEXT: #APP 264; RV32I-NEXT: addi a0, t0, 0 265; RV32I-NEXT: #NO_APP 266; RV32I-NEXT: ret 267; 268; RV64I-LABEL: explicit_register_t0: 269; RV64I: # %bb.0: 270; RV64I-NEXT: mv t0, a0 271; RV64I-NEXT: #APP 272; RV64I-NEXT: addi a0, t0, 0 273; RV64I-NEXT: #NO_APP 274; RV64I-NEXT: ret 275 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t0}"(i32 %a) 276 ret i32 %1 277} 278 279define i32 @explicit_register_x6(i32 %a) nounwind { 280; RV32I-LABEL: explicit_register_x6: 281; RV32I: # %bb.0: 282; RV32I-NEXT: mv t1, a0 283; RV32I-NEXT: #APP 284; RV32I-NEXT: addi a0, t1, 0 285; RV32I-NEXT: #NO_APP 286; RV32I-NEXT: ret 287; 288; RV64I-LABEL: explicit_register_x6: 289; RV64I: # %bb.0: 290; RV64I-NEXT: mv t1, a0 291; RV64I-NEXT: #APP 292; RV64I-NEXT: addi a0, t1, 0 293; RV64I-NEXT: #NO_APP 294; RV64I-NEXT: ret 295 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x6}"(i32 %a) 296 ret i32 %1 297} 298 299define i32 @explicit_register_t1(i32 %a) nounwind { 300; RV32I-LABEL: explicit_register_t1: 301; RV32I: # %bb.0: 302; RV32I-NEXT: mv t1, a0 303; RV32I-NEXT: #APP 304; RV32I-NEXT: addi a0, t1, 0 305; RV32I-NEXT: #NO_APP 306; RV32I-NEXT: ret 307; 308; RV64I-LABEL: explicit_register_t1: 309; RV64I: # %bb.0: 310; RV64I-NEXT: mv t1, a0 311; RV64I-NEXT: #APP 312; RV64I-NEXT: addi a0, t1, 0 313; RV64I-NEXT: #NO_APP 314; RV64I-NEXT: ret 315 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t1}"(i32 %a) 316 ret i32 %1 317} 318 319define i32 @explicit_register_x7(i32 %a) nounwind { 320; RV32I-LABEL: explicit_register_x7: 321; RV32I: # %bb.0: 322; RV32I-NEXT: mv t2, a0 323; RV32I-NEXT: #APP 324; RV32I-NEXT: addi a0, t2, 0 325; RV32I-NEXT: #NO_APP 326; RV32I-NEXT: ret 327; 328; RV64I-LABEL: explicit_register_x7: 329; RV64I: # %bb.0: 330; RV64I-NEXT: mv t2, a0 331; RV64I-NEXT: #APP 332; RV64I-NEXT: addi a0, t2, 0 333; RV64I-NEXT: #NO_APP 334; RV64I-NEXT: ret 335 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x7}"(i32 %a) 336 ret i32 %1 337} 338 339define i32 @explicit_register_t2(i32 %a) nounwind { 340; RV32I-LABEL: explicit_register_t2: 341; RV32I: # %bb.0: 342; RV32I-NEXT: mv t2, a0 343; RV32I-NEXT: #APP 344; RV32I-NEXT: addi a0, t2, 0 345; RV32I-NEXT: #NO_APP 346; RV32I-NEXT: ret 347; 348; RV64I-LABEL: explicit_register_t2: 349; RV64I: # %bb.0: 350; RV64I-NEXT: mv t2, a0 351; RV64I-NEXT: #APP 352; RV64I-NEXT: addi a0, t2, 0 353; RV64I-NEXT: #NO_APP 354; RV64I-NEXT: ret 355 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t2}"(i32 %a) 356 ret i32 %1 357} 358 359; NOTE: This test uses `x8` (`s0`, `fp`) as an input, so it should be saved. 360define i32 @explicit_register_x8(i32 %a) nounwind { 361; RV32I-LABEL: explicit_register_x8: 362; RV32I: # %bb.0: 363; RV32I-NEXT: addi sp, sp, -16 364; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill 365; RV32I-NEXT: mv s0, a0 366; RV32I-NEXT: #APP 367; RV32I-NEXT: addi a0, s0, 0 368; RV32I-NEXT: #NO_APP 369; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload 370; RV32I-NEXT: addi sp, sp, 16 371; RV32I-NEXT: ret 372; 373; RV64I-LABEL: explicit_register_x8: 374; RV64I: # %bb.0: 375; RV64I-NEXT: addi sp, sp, -16 376; RV64I-NEXT: sd s0, 8(sp) # 8-byte Folded Spill 377; RV64I-NEXT: mv s0, a0 378; RV64I-NEXT: #APP 379; RV64I-NEXT: addi a0, s0, 0 380; RV64I-NEXT: #NO_APP 381; RV64I-NEXT: ld s0, 8(sp) # 8-byte Folded Reload 382; RV64I-NEXT: addi sp, sp, 16 383; RV64I-NEXT: ret 384 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x8}"(i32 %a) 385 ret i32 %1 386} 387 388; NOTE: This test uses `s0` (`x8`, `fp`) as an input, so it should be saved. 389define i32 @explicit_register_s0(i32 %a) nounwind { 390; RV32I-LABEL: explicit_register_s0: 391; RV32I: # %bb.0: 392; RV32I-NEXT: addi sp, sp, -16 393; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill 394; RV32I-NEXT: mv s0, a0 395; RV32I-NEXT: #APP 396; RV32I-NEXT: addi a0, s0, 0 397; RV32I-NEXT: #NO_APP 398; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload 399; RV32I-NEXT: addi sp, sp, 16 400; RV32I-NEXT: ret 401; 402; RV64I-LABEL: explicit_register_s0: 403; RV64I: # %bb.0: 404; RV64I-NEXT: addi sp, sp, -16 405; RV64I-NEXT: sd s0, 8(sp) # 8-byte Folded Spill 406; RV64I-NEXT: mv s0, a0 407; RV64I-NEXT: #APP 408; RV64I-NEXT: addi a0, s0, 0 409; RV64I-NEXT: #NO_APP 410; RV64I-NEXT: ld s0, 8(sp) # 8-byte Folded Reload 411; RV64I-NEXT: addi sp, sp, 16 412; RV64I-NEXT: ret 413 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s0}"(i32 %a) 414 ret i32 %1 415} 416 417; NOTE: This test uses `fp` (`x8`, `s0`) as an input, so it should be saved. 418define i32 @explicit_register_fp(i32 %a) nounwind { 419; RV32I-LABEL: explicit_register_fp: 420; RV32I: # %bb.0: 421; RV32I-NEXT: addi sp, sp, -16 422; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill 423; RV32I-NEXT: mv s0, a0 424; RV32I-NEXT: #APP 425; RV32I-NEXT: addi a0, s0, 0 426; RV32I-NEXT: #NO_APP 427; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload 428; RV32I-NEXT: addi sp, sp, 16 429; RV32I-NEXT: ret 430; 431; RV64I-LABEL: explicit_register_fp: 432; RV64I: # %bb.0: 433; RV64I-NEXT: addi sp, sp, -16 434; RV64I-NEXT: sd s0, 8(sp) # 8-byte Folded Spill 435; RV64I-NEXT: mv s0, a0 436; RV64I-NEXT: #APP 437; RV64I-NEXT: addi a0, s0, 0 438; RV64I-NEXT: #NO_APP 439; RV64I-NEXT: ld s0, 8(sp) # 8-byte Folded Reload 440; RV64I-NEXT: addi sp, sp, 16 441; RV64I-NEXT: ret 442 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{fp}"(i32 %a) 443 ret i32 %1 444} 445 446; NOTE: This test uses `x9` (`s1`) as an input, so it should be saved. 447define i32 @explicit_register_x9(i32 %a) nounwind { 448; RV32I-LABEL: explicit_register_x9: 449; RV32I: # %bb.0: 450; RV32I-NEXT: addi sp, sp, -16 451; RV32I-NEXT: sw s1, 12(sp) # 4-byte Folded Spill 452; RV32I-NEXT: mv s1, a0 453; RV32I-NEXT: #APP 454; RV32I-NEXT: addi a0, s1, 0 455; RV32I-NEXT: #NO_APP 456; RV32I-NEXT: lw s1, 12(sp) # 4-byte Folded Reload 457; RV32I-NEXT: addi sp, sp, 16 458; RV32I-NEXT: ret 459; 460; RV64I-LABEL: explicit_register_x9: 461; RV64I: # %bb.0: 462; RV64I-NEXT: addi sp, sp, -16 463; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 464; RV64I-NEXT: mv s1, a0 465; RV64I-NEXT: #APP 466; RV64I-NEXT: addi a0, s1, 0 467; RV64I-NEXT: #NO_APP 468; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 469; RV64I-NEXT: addi sp, sp, 16 470; RV64I-NEXT: ret 471 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x9}"(i32 %a) 472 ret i32 %1 473} 474 475; NOTE: This test uses `s1` (`x9`) as an input, so it should be saved. 476define i32 @explicit_register_s1(i32 %a) nounwind { 477; RV32I-LABEL: explicit_register_s1: 478; RV32I: # %bb.0: 479; RV32I-NEXT: addi sp, sp, -16 480; RV32I-NEXT: sw s1, 12(sp) # 4-byte Folded Spill 481; RV32I-NEXT: mv s1, a0 482; RV32I-NEXT: #APP 483; RV32I-NEXT: addi a0, s1, 0 484; RV32I-NEXT: #NO_APP 485; RV32I-NEXT: lw s1, 12(sp) # 4-byte Folded Reload 486; RV32I-NEXT: addi sp, sp, 16 487; RV32I-NEXT: ret 488; 489; RV64I-LABEL: explicit_register_s1: 490; RV64I: # %bb.0: 491; RV64I-NEXT: addi sp, sp, -16 492; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 493; RV64I-NEXT: mv s1, a0 494; RV64I-NEXT: #APP 495; RV64I-NEXT: addi a0, s1, 0 496; RV64I-NEXT: #NO_APP 497; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 498; RV64I-NEXT: addi sp, sp, 16 499; RV64I-NEXT: ret 500 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s1}"(i32 %a) 501 ret i32 %1 502} 503 504define i32 @explicit_register_x10(i32 %a) nounwind { 505; RV32I-LABEL: explicit_register_x10: 506; RV32I: # %bb.0: 507; RV32I-NEXT: #APP 508; RV32I-NEXT: addi a0, a0, 0 509; RV32I-NEXT: #NO_APP 510; RV32I-NEXT: ret 511; 512; RV64I-LABEL: explicit_register_x10: 513; RV64I: # %bb.0: 514; RV64I-NEXT: #APP 515; RV64I-NEXT: addi a0, a0, 0 516; RV64I-NEXT: #NO_APP 517; RV64I-NEXT: ret 518 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x10}"(i32 %a) 519 ret i32 %1 520} 521 522define i32 @explicit_register_a0(i32 %a) nounwind { 523; RV32I-LABEL: explicit_register_a0: 524; RV32I: # %bb.0: 525; RV32I-NEXT: #APP 526; RV32I-NEXT: addi a0, a0, 0 527; RV32I-NEXT: #NO_APP 528; RV32I-NEXT: ret 529; 530; RV64I-LABEL: explicit_register_a0: 531; RV64I: # %bb.0: 532; RV64I-NEXT: #APP 533; RV64I-NEXT: addi a0, a0, 0 534; RV64I-NEXT: #NO_APP 535; RV64I-NEXT: ret 536 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a0}"(i32 %a) 537 ret i32 %1 538} 539 540define i32 @explicit_register_x11(i32 %a) nounwind { 541; RV32I-LABEL: explicit_register_x11: 542; RV32I: # %bb.0: 543; RV32I-NEXT: mv a1, a0 544; RV32I-NEXT: #APP 545; RV32I-NEXT: addi a0, a1, 0 546; RV32I-NEXT: #NO_APP 547; RV32I-NEXT: ret 548; 549; RV64I-LABEL: explicit_register_x11: 550; RV64I: # %bb.0: 551; RV64I-NEXT: mv a1, a0 552; RV64I-NEXT: #APP 553; RV64I-NEXT: addi a0, a1, 0 554; RV64I-NEXT: #NO_APP 555; RV64I-NEXT: ret 556 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x11}"(i32 %a) 557 ret i32 %1 558} 559 560define i32 @explicit_register_a1(i32 %a) nounwind { 561; RV32I-LABEL: explicit_register_a1: 562; RV32I: # %bb.0: 563; RV32I-NEXT: mv a1, a0 564; RV32I-NEXT: #APP 565; RV32I-NEXT: addi a0, a1, 0 566; RV32I-NEXT: #NO_APP 567; RV32I-NEXT: ret 568; 569; RV64I-LABEL: explicit_register_a1: 570; RV64I: # %bb.0: 571; RV64I-NEXT: mv a1, a0 572; RV64I-NEXT: #APP 573; RV64I-NEXT: addi a0, a1, 0 574; RV64I-NEXT: #NO_APP 575; RV64I-NEXT: ret 576 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a1}"(i32 %a) 577 ret i32 %1 578} 579 580define i32 @explicit_register_x12(i32 %a) nounwind { 581; RV32I-LABEL: explicit_register_x12: 582; RV32I: # %bb.0: 583; RV32I-NEXT: mv a2, a0 584; RV32I-NEXT: #APP 585; RV32I-NEXT: addi a0, a2, 0 586; RV32I-NEXT: #NO_APP 587; RV32I-NEXT: ret 588; 589; RV64I-LABEL: explicit_register_x12: 590; RV64I: # %bb.0: 591; RV64I-NEXT: mv a2, a0 592; RV64I-NEXT: #APP 593; RV64I-NEXT: addi a0, a2, 0 594; RV64I-NEXT: #NO_APP 595; RV64I-NEXT: ret 596 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x12}"(i32 %a) 597 ret i32 %1 598} 599 600define i32 @explicit_register_a2(i32 %a) nounwind { 601; RV32I-LABEL: explicit_register_a2: 602; RV32I: # %bb.0: 603; RV32I-NEXT: mv a2, a0 604; RV32I-NEXT: #APP 605; RV32I-NEXT: addi a0, a2, 0 606; RV32I-NEXT: #NO_APP 607; RV32I-NEXT: ret 608; 609; RV64I-LABEL: explicit_register_a2: 610; RV64I: # %bb.0: 611; RV64I-NEXT: mv a2, a0 612; RV64I-NEXT: #APP 613; RV64I-NEXT: addi a0, a2, 0 614; RV64I-NEXT: #NO_APP 615; RV64I-NEXT: ret 616 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a2}"(i32 %a) 617 ret i32 %1 618} 619 620define i32 @explicit_register_x13(i32 %a) nounwind { 621; RV32I-LABEL: explicit_register_x13: 622; RV32I: # %bb.0: 623; RV32I-NEXT: mv a3, a0 624; RV32I-NEXT: #APP 625; RV32I-NEXT: addi a0, a3, 0 626; RV32I-NEXT: #NO_APP 627; RV32I-NEXT: ret 628; 629; RV64I-LABEL: explicit_register_x13: 630; RV64I: # %bb.0: 631; RV64I-NEXT: mv a3, a0 632; RV64I-NEXT: #APP 633; RV64I-NEXT: addi a0, a3, 0 634; RV64I-NEXT: #NO_APP 635; RV64I-NEXT: ret 636 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x13}"(i32 %a) 637 ret i32 %1 638} 639 640define i32 @explicit_register_a3(i32 %a) nounwind { 641; RV32I-LABEL: explicit_register_a3: 642; RV32I: # %bb.0: 643; RV32I-NEXT: mv a3, a0 644; RV32I-NEXT: #APP 645; RV32I-NEXT: addi a0, a3, 0 646; RV32I-NEXT: #NO_APP 647; RV32I-NEXT: ret 648; 649; RV64I-LABEL: explicit_register_a3: 650; RV64I: # %bb.0: 651; RV64I-NEXT: mv a3, a0 652; RV64I-NEXT: #APP 653; RV64I-NEXT: addi a0, a3, 0 654; RV64I-NEXT: #NO_APP 655; RV64I-NEXT: ret 656 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a3}"(i32 %a) 657 ret i32 %1 658} 659 660define i32 @explicit_register_x14(i32 %a) nounwind { 661; RV32I-LABEL: explicit_register_x14: 662; RV32I: # %bb.0: 663; RV32I-NEXT: mv a4, a0 664; RV32I-NEXT: #APP 665; RV32I-NEXT: addi a0, a4, 0 666; RV32I-NEXT: #NO_APP 667; RV32I-NEXT: ret 668; 669; RV64I-LABEL: explicit_register_x14: 670; RV64I: # %bb.0: 671; RV64I-NEXT: mv a4, a0 672; RV64I-NEXT: #APP 673; RV64I-NEXT: addi a0, a4, 0 674; RV64I-NEXT: #NO_APP 675; RV64I-NEXT: ret 676 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x14}"(i32 %a) 677 ret i32 %1 678} 679 680define i32 @explicit_register_a4(i32 %a) nounwind { 681; RV32I-LABEL: explicit_register_a4: 682; RV32I: # %bb.0: 683; RV32I-NEXT: mv a4, a0 684; RV32I-NEXT: #APP 685; RV32I-NEXT: addi a0, a4, 0 686; RV32I-NEXT: #NO_APP 687; RV32I-NEXT: ret 688; 689; RV64I-LABEL: explicit_register_a4: 690; RV64I: # %bb.0: 691; RV64I-NEXT: mv a4, a0 692; RV64I-NEXT: #APP 693; RV64I-NEXT: addi a0, a4, 0 694; RV64I-NEXT: #NO_APP 695; RV64I-NEXT: ret 696 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a4}"(i32 %a) 697 ret i32 %1 698} 699 700define i32 @explicit_register_x15(i32 %a) nounwind { 701; RV32I-LABEL: explicit_register_x15: 702; RV32I: # %bb.0: 703; RV32I-NEXT: mv a5, a0 704; RV32I-NEXT: #APP 705; RV32I-NEXT: addi a0, a5, 0 706; RV32I-NEXT: #NO_APP 707; RV32I-NEXT: ret 708; 709; RV64I-LABEL: explicit_register_x15: 710; RV64I: # %bb.0: 711; RV64I-NEXT: mv a5, a0 712; RV64I-NEXT: #APP 713; RV64I-NEXT: addi a0, a5, 0 714; RV64I-NEXT: #NO_APP 715; RV64I-NEXT: ret 716 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x15}"(i32 %a) 717 ret i32 %1 718} 719 720define i32 @explicit_register_a5(i32 %a) nounwind { 721; RV32I-LABEL: explicit_register_a5: 722; RV32I: # %bb.0: 723; RV32I-NEXT: mv a5, a0 724; RV32I-NEXT: #APP 725; RV32I-NEXT: addi a0, a5, 0 726; RV32I-NEXT: #NO_APP 727; RV32I-NEXT: ret 728; 729; RV64I-LABEL: explicit_register_a5: 730; RV64I: # %bb.0: 731; RV64I-NEXT: mv a5, a0 732; RV64I-NEXT: #APP 733; RV64I-NEXT: addi a0, a5, 0 734; RV64I-NEXT: #NO_APP 735; RV64I-NEXT: ret 736 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a5}"(i32 %a) 737 ret i32 %1 738} 739 740define i32 @explicit_register_x16(i32 %a) nounwind { 741; RV32I-LABEL: explicit_register_x16: 742; RV32I: # %bb.0: 743; RV32I-NEXT: mv a6, a0 744; RV32I-NEXT: #APP 745; RV32I-NEXT: addi a0, a6, 0 746; RV32I-NEXT: #NO_APP 747; RV32I-NEXT: ret 748; 749; RV64I-LABEL: explicit_register_x16: 750; RV64I: # %bb.0: 751; RV64I-NEXT: mv a6, a0 752; RV64I-NEXT: #APP 753; RV64I-NEXT: addi a0, a6, 0 754; RV64I-NEXT: #NO_APP 755; RV64I-NEXT: ret 756 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x16}"(i32 %a) 757 ret i32 %1 758} 759 760define i32 @explicit_register_a6(i32 %a) nounwind { 761; RV32I-LABEL: explicit_register_a6: 762; RV32I: # %bb.0: 763; RV32I-NEXT: mv a6, a0 764; RV32I-NEXT: #APP 765; RV32I-NEXT: addi a0, a6, 0 766; RV32I-NEXT: #NO_APP 767; RV32I-NEXT: ret 768; 769; RV64I-LABEL: explicit_register_a6: 770; RV64I: # %bb.0: 771; RV64I-NEXT: mv a6, a0 772; RV64I-NEXT: #APP 773; RV64I-NEXT: addi a0, a6, 0 774; RV64I-NEXT: #NO_APP 775; RV64I-NEXT: ret 776 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a6}"(i32 %a) 777 ret i32 %1 778} 779 780define i32 @explicit_register_x17(i32 %a) nounwind { 781; RV32I-LABEL: explicit_register_x17: 782; RV32I: # %bb.0: 783; RV32I-NEXT: mv a7, a0 784; RV32I-NEXT: #APP 785; RV32I-NEXT: addi a0, a7, 0 786; RV32I-NEXT: #NO_APP 787; RV32I-NEXT: ret 788; 789; RV64I-LABEL: explicit_register_x17: 790; RV64I: # %bb.0: 791; RV64I-NEXT: mv a7, a0 792; RV64I-NEXT: #APP 793; RV64I-NEXT: addi a0, a7, 0 794; RV64I-NEXT: #NO_APP 795; RV64I-NEXT: ret 796 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x17}"(i32 %a) 797 ret i32 %1 798} 799 800define i32 @explicit_register_a7(i32 %a) nounwind { 801; RV32I-LABEL: explicit_register_a7: 802; RV32I: # %bb.0: 803; RV32I-NEXT: mv a7, a0 804; RV32I-NEXT: #APP 805; RV32I-NEXT: addi a0, a7, 0 806; RV32I-NEXT: #NO_APP 807; RV32I-NEXT: ret 808; 809; RV64I-LABEL: explicit_register_a7: 810; RV64I: # %bb.0: 811; RV64I-NEXT: mv a7, a0 812; RV64I-NEXT: #APP 813; RV64I-NEXT: addi a0, a7, 0 814; RV64I-NEXT: #NO_APP 815; RV64I-NEXT: ret 816 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a7}"(i32 %a) 817 ret i32 %1 818} 819 820; NOTE: This test uses `x18` (`s2`) as an input, so it should be saved. 821define i32 @explicit_register_x18(i32 %a) nounwind { 822; RV32I-LABEL: explicit_register_x18: 823; RV32I: # %bb.0: 824; RV32I-NEXT: addi sp, sp, -16 825; RV32I-NEXT: sw s2, 12(sp) # 4-byte Folded Spill 826; RV32I-NEXT: mv s2, a0 827; RV32I-NEXT: #APP 828; RV32I-NEXT: addi a0, s2, 0 829; RV32I-NEXT: #NO_APP 830; RV32I-NEXT: lw s2, 12(sp) # 4-byte Folded Reload 831; RV32I-NEXT: addi sp, sp, 16 832; RV32I-NEXT: ret 833; 834; RV64I-LABEL: explicit_register_x18: 835; RV64I: # %bb.0: 836; RV64I-NEXT: addi sp, sp, -16 837; RV64I-NEXT: sd s2, 8(sp) # 8-byte Folded Spill 838; RV64I-NEXT: mv s2, a0 839; RV64I-NEXT: #APP 840; RV64I-NEXT: addi a0, s2, 0 841; RV64I-NEXT: #NO_APP 842; RV64I-NEXT: ld s2, 8(sp) # 8-byte Folded Reload 843; RV64I-NEXT: addi sp, sp, 16 844; RV64I-NEXT: ret 845 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x18}"(i32 %a) 846 ret i32 %1 847} 848 849; NOTE: This test uses `s2` (`x18`) as an input, so it should be saved. 850define i32 @explicit_register_s2(i32 %a) nounwind { 851; RV32I-LABEL: explicit_register_s2: 852; RV32I: # %bb.0: 853; RV32I-NEXT: addi sp, sp, -16 854; RV32I-NEXT: sw s2, 12(sp) # 4-byte Folded Spill 855; RV32I-NEXT: mv s2, a0 856; RV32I-NEXT: #APP 857; RV32I-NEXT: addi a0, s2, 0 858; RV32I-NEXT: #NO_APP 859; RV32I-NEXT: lw s2, 12(sp) # 4-byte Folded Reload 860; RV32I-NEXT: addi sp, sp, 16 861; RV32I-NEXT: ret 862; 863; RV64I-LABEL: explicit_register_s2: 864; RV64I: # %bb.0: 865; RV64I-NEXT: addi sp, sp, -16 866; RV64I-NEXT: sd s2, 8(sp) # 8-byte Folded Spill 867; RV64I-NEXT: mv s2, a0 868; RV64I-NEXT: #APP 869; RV64I-NEXT: addi a0, s2, 0 870; RV64I-NEXT: #NO_APP 871; RV64I-NEXT: ld s2, 8(sp) # 8-byte Folded Reload 872; RV64I-NEXT: addi sp, sp, 16 873; RV64I-NEXT: ret 874 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s2}"(i32 %a) 875 ret i32 %1 876} 877 878; NOTE: This test uses `x19` (`s3`) as an input, so it should be saved. 879define i32 @explicit_register_x19(i32 %a) nounwind { 880; RV32I-LABEL: explicit_register_x19: 881; RV32I: # %bb.0: 882; RV32I-NEXT: addi sp, sp, -16 883; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill 884; RV32I-NEXT: mv s3, a0 885; RV32I-NEXT: #APP 886; RV32I-NEXT: addi a0, s3, 0 887; RV32I-NEXT: #NO_APP 888; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload 889; RV32I-NEXT: addi sp, sp, 16 890; RV32I-NEXT: ret 891; 892; RV64I-LABEL: explicit_register_x19: 893; RV64I: # %bb.0: 894; RV64I-NEXT: addi sp, sp, -16 895; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill 896; RV64I-NEXT: mv s3, a0 897; RV64I-NEXT: #APP 898; RV64I-NEXT: addi a0, s3, 0 899; RV64I-NEXT: #NO_APP 900; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload 901; RV64I-NEXT: addi sp, sp, 16 902; RV64I-NEXT: ret 903 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x19}"(i32 %a) 904 ret i32 %1 905} 906 907; NOTE: This test uses `s3` (`x19`) as an input, so it should be saved. 908define i32 @explicit_register_s3(i32 %a) nounwind { 909; RV32I-LABEL: explicit_register_s3: 910; RV32I: # %bb.0: 911; RV32I-NEXT: addi sp, sp, -16 912; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill 913; RV32I-NEXT: mv s3, a0 914; RV32I-NEXT: #APP 915; RV32I-NEXT: addi a0, s3, 0 916; RV32I-NEXT: #NO_APP 917; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload 918; RV32I-NEXT: addi sp, sp, 16 919; RV32I-NEXT: ret 920; 921; RV64I-LABEL: explicit_register_s3: 922; RV64I: # %bb.0: 923; RV64I-NEXT: addi sp, sp, -16 924; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill 925; RV64I-NEXT: mv s3, a0 926; RV64I-NEXT: #APP 927; RV64I-NEXT: addi a0, s3, 0 928; RV64I-NEXT: #NO_APP 929; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload 930; RV64I-NEXT: addi sp, sp, 16 931; RV64I-NEXT: ret 932 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s3}"(i32 %a) 933 ret i32 %1 934} 935 936; NOTE: This test uses `x20` (`s4`) as an input, so it should be saved. 937define i32 @explicit_register_x20(i32 %a) nounwind { 938; RV32I-LABEL: explicit_register_x20: 939; RV32I: # %bb.0: 940; RV32I-NEXT: addi sp, sp, -16 941; RV32I-NEXT: sw s4, 12(sp) # 4-byte Folded Spill 942; RV32I-NEXT: mv s4, a0 943; RV32I-NEXT: #APP 944; RV32I-NEXT: addi a0, s4, 0 945; RV32I-NEXT: #NO_APP 946; RV32I-NEXT: lw s4, 12(sp) # 4-byte Folded Reload 947; RV32I-NEXT: addi sp, sp, 16 948; RV32I-NEXT: ret 949; 950; RV64I-LABEL: explicit_register_x20: 951; RV64I: # %bb.0: 952; RV64I-NEXT: addi sp, sp, -16 953; RV64I-NEXT: sd s4, 8(sp) # 8-byte Folded Spill 954; RV64I-NEXT: mv s4, a0 955; RV64I-NEXT: #APP 956; RV64I-NEXT: addi a0, s4, 0 957; RV64I-NEXT: #NO_APP 958; RV64I-NEXT: ld s4, 8(sp) # 8-byte Folded Reload 959; RV64I-NEXT: addi sp, sp, 16 960; RV64I-NEXT: ret 961 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x20}"(i32 %a) 962 ret i32 %1 963} 964 965; NOTE: This test uses `s4` (`x20`) as an input, so it should be saved. 966define i32 @explicit_register_s4(i32 %a) nounwind { 967; RV32I-LABEL: explicit_register_s4: 968; RV32I: # %bb.0: 969; RV32I-NEXT: addi sp, sp, -16 970; RV32I-NEXT: sw s4, 12(sp) # 4-byte Folded Spill 971; RV32I-NEXT: mv s4, a0 972; RV32I-NEXT: #APP 973; RV32I-NEXT: addi a0, s4, 0 974; RV32I-NEXT: #NO_APP 975; RV32I-NEXT: lw s4, 12(sp) # 4-byte Folded Reload 976; RV32I-NEXT: addi sp, sp, 16 977; RV32I-NEXT: ret 978; 979; RV64I-LABEL: explicit_register_s4: 980; RV64I: # %bb.0: 981; RV64I-NEXT: addi sp, sp, -16 982; RV64I-NEXT: sd s4, 8(sp) # 8-byte Folded Spill 983; RV64I-NEXT: mv s4, a0 984; RV64I-NEXT: #APP 985; RV64I-NEXT: addi a0, s4, 0 986; RV64I-NEXT: #NO_APP 987; RV64I-NEXT: ld s4, 8(sp) # 8-byte Folded Reload 988; RV64I-NEXT: addi sp, sp, 16 989; RV64I-NEXT: ret 990 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s4}"(i32 %a) 991 ret i32 %1 992} 993 994; NOTE: This test uses `x21` (`s5`) as an input, so it should be saved. 995define i32 @explicit_register_x21(i32 %a) nounwind { 996; RV32I-LABEL: explicit_register_x21: 997; RV32I: # %bb.0: 998; RV32I-NEXT: addi sp, sp, -16 999; RV32I-NEXT: sw s5, 12(sp) # 4-byte Folded Spill 1000; RV32I-NEXT: mv s5, a0 1001; RV32I-NEXT: #APP 1002; RV32I-NEXT: addi a0, s5, 0 1003; RV32I-NEXT: #NO_APP 1004; RV32I-NEXT: lw s5, 12(sp) # 4-byte Folded Reload 1005; RV32I-NEXT: addi sp, sp, 16 1006; RV32I-NEXT: ret 1007; 1008; RV64I-LABEL: explicit_register_x21: 1009; RV64I: # %bb.0: 1010; RV64I-NEXT: addi sp, sp, -16 1011; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill 1012; RV64I-NEXT: mv s5, a0 1013; RV64I-NEXT: #APP 1014; RV64I-NEXT: addi a0, s5, 0 1015; RV64I-NEXT: #NO_APP 1016; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload 1017; RV64I-NEXT: addi sp, sp, 16 1018; RV64I-NEXT: ret 1019 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x21}"(i32 %a) 1020 ret i32 %1 1021} 1022 1023; NOTE: This test uses `s5` (`x21`) as an input, so it should be saved. 1024define i32 @explicit_register_s5(i32 %a) nounwind { 1025; RV32I-LABEL: explicit_register_s5: 1026; RV32I: # %bb.0: 1027; RV32I-NEXT: addi sp, sp, -16 1028; RV32I-NEXT: sw s5, 12(sp) # 4-byte Folded Spill 1029; RV32I-NEXT: mv s5, a0 1030; RV32I-NEXT: #APP 1031; RV32I-NEXT: addi a0, s5, 0 1032; RV32I-NEXT: #NO_APP 1033; RV32I-NEXT: lw s5, 12(sp) # 4-byte Folded Reload 1034; RV32I-NEXT: addi sp, sp, 16 1035; RV32I-NEXT: ret 1036; 1037; RV64I-LABEL: explicit_register_s5: 1038; RV64I: # %bb.0: 1039; RV64I-NEXT: addi sp, sp, -16 1040; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill 1041; RV64I-NEXT: mv s5, a0 1042; RV64I-NEXT: #APP 1043; RV64I-NEXT: addi a0, s5, 0 1044; RV64I-NEXT: #NO_APP 1045; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload 1046; RV64I-NEXT: addi sp, sp, 16 1047; RV64I-NEXT: ret 1048 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s5}"(i32 %a) 1049 ret i32 %1 1050} 1051 1052; NOTE: This test uses `x22` (`s6`) as an input, so it should be saved. 1053define i32 @explicit_register_x22(i32 %a) nounwind { 1054; RV32I-LABEL: explicit_register_x22: 1055; RV32I: # %bb.0: 1056; RV32I-NEXT: addi sp, sp, -16 1057; RV32I-NEXT: sw s6, 12(sp) # 4-byte Folded Spill 1058; RV32I-NEXT: mv s6, a0 1059; RV32I-NEXT: #APP 1060; RV32I-NEXT: addi a0, s6, 0 1061; RV32I-NEXT: #NO_APP 1062; RV32I-NEXT: lw s6, 12(sp) # 4-byte Folded Reload 1063; RV32I-NEXT: addi sp, sp, 16 1064; RV32I-NEXT: ret 1065; 1066; RV64I-LABEL: explicit_register_x22: 1067; RV64I: # %bb.0: 1068; RV64I-NEXT: addi sp, sp, -16 1069; RV64I-NEXT: sd s6, 8(sp) # 8-byte Folded Spill 1070; RV64I-NEXT: mv s6, a0 1071; RV64I-NEXT: #APP 1072; RV64I-NEXT: addi a0, s6, 0 1073; RV64I-NEXT: #NO_APP 1074; RV64I-NEXT: ld s6, 8(sp) # 8-byte Folded Reload 1075; RV64I-NEXT: addi sp, sp, 16 1076; RV64I-NEXT: ret 1077 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x22}"(i32 %a) 1078 ret i32 %1 1079} 1080 1081; NOTE: This test uses `s6` (`x22`) as an input, so it should be saved. 1082define i32 @explicit_register_s6(i32 %a) nounwind { 1083; RV32I-LABEL: explicit_register_s6: 1084; RV32I: # %bb.0: 1085; RV32I-NEXT: addi sp, sp, -16 1086; RV32I-NEXT: sw s6, 12(sp) # 4-byte Folded Spill 1087; RV32I-NEXT: mv s6, a0 1088; RV32I-NEXT: #APP 1089; RV32I-NEXT: addi a0, s6, 0 1090; RV32I-NEXT: #NO_APP 1091; RV32I-NEXT: lw s6, 12(sp) # 4-byte Folded Reload 1092; RV32I-NEXT: addi sp, sp, 16 1093; RV32I-NEXT: ret 1094; 1095; RV64I-LABEL: explicit_register_s6: 1096; RV64I: # %bb.0: 1097; RV64I-NEXT: addi sp, sp, -16 1098; RV64I-NEXT: sd s6, 8(sp) # 8-byte Folded Spill 1099; RV64I-NEXT: mv s6, a0 1100; RV64I-NEXT: #APP 1101; RV64I-NEXT: addi a0, s6, 0 1102; RV64I-NEXT: #NO_APP 1103; RV64I-NEXT: ld s6, 8(sp) # 8-byte Folded Reload 1104; RV64I-NEXT: addi sp, sp, 16 1105; RV64I-NEXT: ret 1106 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s6}"(i32 %a) 1107 ret i32 %1 1108} 1109 1110; NOTE: This test uses `x23` (`s7`) as an input, so it should be saved. 1111define i32 @explicit_register_x23(i32 %a) nounwind { 1112; RV32I-LABEL: explicit_register_x23: 1113; RV32I: # %bb.0: 1114; RV32I-NEXT: addi sp, sp, -16 1115; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill 1116; RV32I-NEXT: mv s7, a0 1117; RV32I-NEXT: #APP 1118; RV32I-NEXT: addi a0, s7, 0 1119; RV32I-NEXT: #NO_APP 1120; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload 1121; RV32I-NEXT: addi sp, sp, 16 1122; RV32I-NEXT: ret 1123; 1124; RV64I-LABEL: explicit_register_x23: 1125; RV64I: # %bb.0: 1126; RV64I-NEXT: addi sp, sp, -16 1127; RV64I-NEXT: sd s7, 8(sp) # 8-byte Folded Spill 1128; RV64I-NEXT: mv s7, a0 1129; RV64I-NEXT: #APP 1130; RV64I-NEXT: addi a0, s7, 0 1131; RV64I-NEXT: #NO_APP 1132; RV64I-NEXT: ld s7, 8(sp) # 8-byte Folded Reload 1133; RV64I-NEXT: addi sp, sp, 16 1134; RV64I-NEXT: ret 1135 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x23}"(i32 %a) 1136 ret i32 %1 1137} 1138 1139; NOTE: This test uses `s7` (`x23`) as an input, so it should be saved. 1140define i32 @explicit_register_s7(i32 %a) nounwind { 1141; RV32I-LABEL: explicit_register_s7: 1142; RV32I: # %bb.0: 1143; RV32I-NEXT: addi sp, sp, -16 1144; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill 1145; RV32I-NEXT: mv s7, a0 1146; RV32I-NEXT: #APP 1147; RV32I-NEXT: addi a0, s7, 0 1148; RV32I-NEXT: #NO_APP 1149; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload 1150; RV32I-NEXT: addi sp, sp, 16 1151; RV32I-NEXT: ret 1152; 1153; RV64I-LABEL: explicit_register_s7: 1154; RV64I: # %bb.0: 1155; RV64I-NEXT: addi sp, sp, -16 1156; RV64I-NEXT: sd s7, 8(sp) # 8-byte Folded Spill 1157; RV64I-NEXT: mv s7, a0 1158; RV64I-NEXT: #APP 1159; RV64I-NEXT: addi a0, s7, 0 1160; RV64I-NEXT: #NO_APP 1161; RV64I-NEXT: ld s7, 8(sp) # 8-byte Folded Reload 1162; RV64I-NEXT: addi sp, sp, 16 1163; RV64I-NEXT: ret 1164 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s7}"(i32 %a) 1165 ret i32 %1 1166} 1167 1168; NOTE: This test uses `x24` (`s8`) as an input, so it should be saved. 1169define i32 @explicit_register_x24(i32 %a) nounwind { 1170; RV32I-LABEL: explicit_register_x24: 1171; RV32I: # %bb.0: 1172; RV32I-NEXT: addi sp, sp, -16 1173; RV32I-NEXT: sw s8, 12(sp) # 4-byte Folded Spill 1174; RV32I-NEXT: mv s8, a0 1175; RV32I-NEXT: #APP 1176; RV32I-NEXT: addi a0, s8, 0 1177; RV32I-NEXT: #NO_APP 1178; RV32I-NEXT: lw s8, 12(sp) # 4-byte Folded Reload 1179; RV32I-NEXT: addi sp, sp, 16 1180; RV32I-NEXT: ret 1181; 1182; RV64I-LABEL: explicit_register_x24: 1183; RV64I: # %bb.0: 1184; RV64I-NEXT: addi sp, sp, -16 1185; RV64I-NEXT: sd s8, 8(sp) # 8-byte Folded Spill 1186; RV64I-NEXT: mv s8, a0 1187; RV64I-NEXT: #APP 1188; RV64I-NEXT: addi a0, s8, 0 1189; RV64I-NEXT: #NO_APP 1190; RV64I-NEXT: ld s8, 8(sp) # 8-byte Folded Reload 1191; RV64I-NEXT: addi sp, sp, 16 1192; RV64I-NEXT: ret 1193 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x24}"(i32 %a) 1194 ret i32 %1 1195} 1196 1197; NOTE: This test uses `s8` (`x24`) as an input, so it should be saved. 1198define i32 @explicit_register_s8(i32 %a) nounwind { 1199; RV32I-LABEL: explicit_register_s8: 1200; RV32I: # %bb.0: 1201; RV32I-NEXT: addi sp, sp, -16 1202; RV32I-NEXT: sw s8, 12(sp) # 4-byte Folded Spill 1203; RV32I-NEXT: mv s8, a0 1204; RV32I-NEXT: #APP 1205; RV32I-NEXT: addi a0, s8, 0 1206; RV32I-NEXT: #NO_APP 1207; RV32I-NEXT: lw s8, 12(sp) # 4-byte Folded Reload 1208; RV32I-NEXT: addi sp, sp, 16 1209; RV32I-NEXT: ret 1210; 1211; RV64I-LABEL: explicit_register_s8: 1212; RV64I: # %bb.0: 1213; RV64I-NEXT: addi sp, sp, -16 1214; RV64I-NEXT: sd s8, 8(sp) # 8-byte Folded Spill 1215; RV64I-NEXT: mv s8, a0 1216; RV64I-NEXT: #APP 1217; RV64I-NEXT: addi a0, s8, 0 1218; RV64I-NEXT: #NO_APP 1219; RV64I-NEXT: ld s8, 8(sp) # 8-byte Folded Reload 1220; RV64I-NEXT: addi sp, sp, 16 1221; RV64I-NEXT: ret 1222 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s8}"(i32 %a) 1223 ret i32 %1 1224} 1225 1226; NOTE: This test uses `x25` (`s9`) as an input, so it should be saved. 1227define i32 @explicit_register_x25(i32 %a) nounwind { 1228; RV32I-LABEL: explicit_register_x25: 1229; RV32I: # %bb.0: 1230; RV32I-NEXT: addi sp, sp, -16 1231; RV32I-NEXT: sw s9, 12(sp) # 4-byte Folded Spill 1232; RV32I-NEXT: mv s9, a0 1233; RV32I-NEXT: #APP 1234; RV32I-NEXT: addi a0, s9, 0 1235; RV32I-NEXT: #NO_APP 1236; RV32I-NEXT: lw s9, 12(sp) # 4-byte Folded Reload 1237; RV32I-NEXT: addi sp, sp, 16 1238; RV32I-NEXT: ret 1239; 1240; RV64I-LABEL: explicit_register_x25: 1241; RV64I: # %bb.0: 1242; RV64I-NEXT: addi sp, sp, -16 1243; RV64I-NEXT: sd s9, 8(sp) # 8-byte Folded Spill 1244; RV64I-NEXT: mv s9, a0 1245; RV64I-NEXT: #APP 1246; RV64I-NEXT: addi a0, s9, 0 1247; RV64I-NEXT: #NO_APP 1248; RV64I-NEXT: ld s9, 8(sp) # 8-byte Folded Reload 1249; RV64I-NEXT: addi sp, sp, 16 1250; RV64I-NEXT: ret 1251 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x25}"(i32 %a) 1252 ret i32 %1 1253} 1254 1255; NOTE: This test uses `s9` (`x25`) as an input, so it should be saved. 1256define i32 @explicit_register_s9(i32 %a) nounwind { 1257; RV32I-LABEL: explicit_register_s9: 1258; RV32I: # %bb.0: 1259; RV32I-NEXT: addi sp, sp, -16 1260; RV32I-NEXT: sw s9, 12(sp) # 4-byte Folded Spill 1261; RV32I-NEXT: mv s9, a0 1262; RV32I-NEXT: #APP 1263; RV32I-NEXT: addi a0, s9, 0 1264; RV32I-NEXT: #NO_APP 1265; RV32I-NEXT: lw s9, 12(sp) # 4-byte Folded Reload 1266; RV32I-NEXT: addi sp, sp, 16 1267; RV32I-NEXT: ret 1268; 1269; RV64I-LABEL: explicit_register_s9: 1270; RV64I: # %bb.0: 1271; RV64I-NEXT: addi sp, sp, -16 1272; RV64I-NEXT: sd s9, 8(sp) # 8-byte Folded Spill 1273; RV64I-NEXT: mv s9, a0 1274; RV64I-NEXT: #APP 1275; RV64I-NEXT: addi a0, s9, 0 1276; RV64I-NEXT: #NO_APP 1277; RV64I-NEXT: ld s9, 8(sp) # 8-byte Folded Reload 1278; RV64I-NEXT: addi sp, sp, 16 1279; RV64I-NEXT: ret 1280 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s9}"(i32 %a) 1281 ret i32 %1 1282} 1283 1284; NOTE: This test uses `x26` (`s10`) as an input, so it should be saved. 1285define i32 @explicit_register_x26(i32 %a) nounwind { 1286; RV32I-LABEL: explicit_register_x26: 1287; RV32I: # %bb.0: 1288; RV32I-NEXT: addi sp, sp, -16 1289; RV32I-NEXT: sw s10, 12(sp) # 4-byte Folded Spill 1290; RV32I-NEXT: mv s10, a0 1291; RV32I-NEXT: #APP 1292; RV32I-NEXT: addi a0, s10, 0 1293; RV32I-NEXT: #NO_APP 1294; RV32I-NEXT: lw s10, 12(sp) # 4-byte Folded Reload 1295; RV32I-NEXT: addi sp, sp, 16 1296; RV32I-NEXT: ret 1297; 1298; RV64I-LABEL: explicit_register_x26: 1299; RV64I: # %bb.0: 1300; RV64I-NEXT: addi sp, sp, -16 1301; RV64I-NEXT: sd s10, 8(sp) # 8-byte Folded Spill 1302; RV64I-NEXT: mv s10, a0 1303; RV64I-NEXT: #APP 1304; RV64I-NEXT: addi a0, s10, 0 1305; RV64I-NEXT: #NO_APP 1306; RV64I-NEXT: ld s10, 8(sp) # 8-byte Folded Reload 1307; RV64I-NEXT: addi sp, sp, 16 1308; RV64I-NEXT: ret 1309 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x26}"(i32 %a) 1310 ret i32 %1 1311} 1312 1313; NOTE: This test uses `s10` (`x28`) as an input, so it should be saved. 1314define i32 @explicit_register_s10(i32 %a) nounwind { 1315; RV32I-LABEL: explicit_register_s10: 1316; RV32I: # %bb.0: 1317; RV32I-NEXT: addi sp, sp, -16 1318; RV32I-NEXT: sw s10, 12(sp) # 4-byte Folded Spill 1319; RV32I-NEXT: mv s10, a0 1320; RV32I-NEXT: #APP 1321; RV32I-NEXT: addi a0, s10, 0 1322; RV32I-NEXT: #NO_APP 1323; RV32I-NEXT: lw s10, 12(sp) # 4-byte Folded Reload 1324; RV32I-NEXT: addi sp, sp, 16 1325; RV32I-NEXT: ret 1326; 1327; RV64I-LABEL: explicit_register_s10: 1328; RV64I: # %bb.0: 1329; RV64I-NEXT: addi sp, sp, -16 1330; RV64I-NEXT: sd s10, 8(sp) # 8-byte Folded Spill 1331; RV64I-NEXT: mv s10, a0 1332; RV64I-NEXT: #APP 1333; RV64I-NEXT: addi a0, s10, 0 1334; RV64I-NEXT: #NO_APP 1335; RV64I-NEXT: ld s10, 8(sp) # 8-byte Folded Reload 1336; RV64I-NEXT: addi sp, sp, 16 1337; RV64I-NEXT: ret 1338 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s10}"(i32 %a) 1339 ret i32 %1 1340} 1341 1342; NOTE: This test uses `x27` (`s11`) as an input, so it should be saved. 1343define i32 @explicit_register_x27(i32 %a) nounwind { 1344; RV32I-LABEL: explicit_register_x27: 1345; RV32I: # %bb.0: 1346; RV32I-NEXT: addi sp, sp, -16 1347; RV32I-NEXT: sw s11, 12(sp) # 4-byte Folded Spill 1348; RV32I-NEXT: mv s11, a0 1349; RV32I-NEXT: #APP 1350; RV32I-NEXT: addi a0, s11, 0 1351; RV32I-NEXT: #NO_APP 1352; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload 1353; RV32I-NEXT: addi sp, sp, 16 1354; RV32I-NEXT: ret 1355; 1356; RV64I-LABEL: explicit_register_x27: 1357; RV64I: # %bb.0: 1358; RV64I-NEXT: addi sp, sp, -16 1359; RV64I-NEXT: sd s11, 8(sp) # 8-byte Folded Spill 1360; RV64I-NEXT: mv s11, a0 1361; RV64I-NEXT: #APP 1362; RV64I-NEXT: addi a0, s11, 0 1363; RV64I-NEXT: #NO_APP 1364; RV64I-NEXT: ld s11, 8(sp) # 8-byte Folded Reload 1365; RV64I-NEXT: addi sp, sp, 16 1366; RV64I-NEXT: ret 1367 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x27}"(i32 %a) 1368 ret i32 %1 1369} 1370 1371; NOTE: This test uses `s11` (`x27`) as an input, so it should be saved. 1372define i32 @explicit_register_s11(i32 %a) nounwind { 1373; RV32I-LABEL: explicit_register_s11: 1374; RV32I: # %bb.0: 1375; RV32I-NEXT: addi sp, sp, -16 1376; RV32I-NEXT: sw s11, 12(sp) # 4-byte Folded Spill 1377; RV32I-NEXT: mv s11, a0 1378; RV32I-NEXT: #APP 1379; RV32I-NEXT: addi a0, s11, 0 1380; RV32I-NEXT: #NO_APP 1381; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload 1382; RV32I-NEXT: addi sp, sp, 16 1383; RV32I-NEXT: ret 1384; 1385; RV64I-LABEL: explicit_register_s11: 1386; RV64I: # %bb.0: 1387; RV64I-NEXT: addi sp, sp, -16 1388; RV64I-NEXT: sd s11, 8(sp) # 8-byte Folded Spill 1389; RV64I-NEXT: mv s11, a0 1390; RV64I-NEXT: #APP 1391; RV64I-NEXT: addi a0, s11, 0 1392; RV64I-NEXT: #NO_APP 1393; RV64I-NEXT: ld s11, 8(sp) # 8-byte Folded Reload 1394; RV64I-NEXT: addi sp, sp, 16 1395; RV64I-NEXT: ret 1396 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s11}"(i32 %a) 1397 ret i32 %1 1398} 1399 1400define i32 @explicit_register_x28(i32 %a) nounwind { 1401; RV32I-LABEL: explicit_register_x28: 1402; RV32I: # %bb.0: 1403; RV32I-NEXT: mv t3, a0 1404; RV32I-NEXT: #APP 1405; RV32I-NEXT: addi a0, t3, 0 1406; RV32I-NEXT: #NO_APP 1407; RV32I-NEXT: ret 1408; 1409; RV64I-LABEL: explicit_register_x28: 1410; RV64I: # %bb.0: 1411; RV64I-NEXT: mv t3, a0 1412; RV64I-NEXT: #APP 1413; RV64I-NEXT: addi a0, t3, 0 1414; RV64I-NEXT: #NO_APP 1415; RV64I-NEXT: ret 1416 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x28}"(i32 %a) 1417 ret i32 %1 1418} 1419 1420define i32 @explicit_register_t3(i32 %a) nounwind { 1421; RV32I-LABEL: explicit_register_t3: 1422; RV32I: # %bb.0: 1423; RV32I-NEXT: mv t3, a0 1424; RV32I-NEXT: #APP 1425; RV32I-NEXT: addi a0, t3, 0 1426; RV32I-NEXT: #NO_APP 1427; RV32I-NEXT: ret 1428; 1429; RV64I-LABEL: explicit_register_t3: 1430; RV64I: # %bb.0: 1431; RV64I-NEXT: mv t3, a0 1432; RV64I-NEXT: #APP 1433; RV64I-NEXT: addi a0, t3, 0 1434; RV64I-NEXT: #NO_APP 1435; RV64I-NEXT: ret 1436 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t3}"(i32 %a) 1437 ret i32 %1 1438} 1439 1440define i32 @explicit_register_x29(i32 %a) nounwind { 1441; RV32I-LABEL: explicit_register_x29: 1442; RV32I: # %bb.0: 1443; RV32I-NEXT: mv t4, a0 1444; RV32I-NEXT: #APP 1445; RV32I-NEXT: addi a0, t4, 0 1446; RV32I-NEXT: #NO_APP 1447; RV32I-NEXT: ret 1448; 1449; RV64I-LABEL: explicit_register_x29: 1450; RV64I: # %bb.0: 1451; RV64I-NEXT: mv t4, a0 1452; RV64I-NEXT: #APP 1453; RV64I-NEXT: addi a0, t4, 0 1454; RV64I-NEXT: #NO_APP 1455; RV64I-NEXT: ret 1456 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x29}"(i32 %a) 1457 ret i32 %1 1458} 1459 1460define i32 @explicit_register_t4(i32 %a) nounwind { 1461; RV32I-LABEL: explicit_register_t4: 1462; RV32I: # %bb.0: 1463; RV32I-NEXT: mv t4, a0 1464; RV32I-NEXT: #APP 1465; RV32I-NEXT: addi a0, t4, 0 1466; RV32I-NEXT: #NO_APP 1467; RV32I-NEXT: ret 1468; 1469; RV64I-LABEL: explicit_register_t4: 1470; RV64I: # %bb.0: 1471; RV64I-NEXT: mv t4, a0 1472; RV64I-NEXT: #APP 1473; RV64I-NEXT: addi a0, t4, 0 1474; RV64I-NEXT: #NO_APP 1475; RV64I-NEXT: ret 1476 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t4}"(i32 %a) 1477 ret i32 %1 1478} 1479 1480define i32 @explicit_register_x30(i32 %a) nounwind { 1481; RV32I-LABEL: explicit_register_x30: 1482; RV32I: # %bb.0: 1483; RV32I-NEXT: mv t5, a0 1484; RV32I-NEXT: #APP 1485; RV32I-NEXT: addi a0, t5, 0 1486; RV32I-NEXT: #NO_APP 1487; RV32I-NEXT: ret 1488; 1489; RV64I-LABEL: explicit_register_x30: 1490; RV64I: # %bb.0: 1491; RV64I-NEXT: mv t5, a0 1492; RV64I-NEXT: #APP 1493; RV64I-NEXT: addi a0, t5, 0 1494; RV64I-NEXT: #NO_APP 1495; RV64I-NEXT: ret 1496 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x30}"(i32 %a) 1497 ret i32 %1 1498} 1499 1500define i32 @explicit_register_t5(i32 %a) nounwind { 1501; RV32I-LABEL: explicit_register_t5: 1502; RV32I: # %bb.0: 1503; RV32I-NEXT: mv t5, a0 1504; RV32I-NEXT: #APP 1505; RV32I-NEXT: addi a0, t5, 0 1506; RV32I-NEXT: #NO_APP 1507; RV32I-NEXT: ret 1508; 1509; RV64I-LABEL: explicit_register_t5: 1510; RV64I: # %bb.0: 1511; RV64I-NEXT: mv t5, a0 1512; RV64I-NEXT: #APP 1513; RV64I-NEXT: addi a0, t5, 0 1514; RV64I-NEXT: #NO_APP 1515; RV64I-NEXT: ret 1516 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t5}"(i32 %a) 1517 ret i32 %1 1518} 1519 1520define i32 @explicit_register_x31(i32 %a) nounwind { 1521; RV32I-LABEL: explicit_register_x31: 1522; RV32I: # %bb.0: 1523; RV32I-NEXT: mv t6, a0 1524; RV32I-NEXT: #APP 1525; RV32I-NEXT: addi a0, t6, 0 1526; RV32I-NEXT: #NO_APP 1527; RV32I-NEXT: ret 1528; 1529; RV64I-LABEL: explicit_register_x31: 1530; RV64I: # %bb.0: 1531; RV64I-NEXT: mv t6, a0 1532; RV64I-NEXT: #APP 1533; RV64I-NEXT: addi a0, t6, 0 1534; RV64I-NEXT: #NO_APP 1535; RV64I-NEXT: ret 1536 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x31}"(i32 %a) 1537 ret i32 %1 1538} 1539 1540define i32 @explicit_register_t6(i32 %a) nounwind { 1541; RV32I-LABEL: explicit_register_t6: 1542; RV32I: # %bb.0: 1543; RV32I-NEXT: mv t6, a0 1544; RV32I-NEXT: #APP 1545; RV32I-NEXT: addi a0, t6, 0 1546; RV32I-NEXT: #NO_APP 1547; RV32I-NEXT: ret 1548; 1549; RV64I-LABEL: explicit_register_t6: 1550; RV64I: # %bb.0: 1551; RV64I-NEXT: mv t6, a0 1552; RV64I-NEXT: #APP 1553; RV64I-NEXT: addi a0, t6, 0 1554; RV64I-NEXT: #NO_APP 1555; RV64I-NEXT: ret 1556 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t6}"(i32 %a) 1557 ret i32 %1 1558} 1559