xref: /llvm-project/llvm/test/CodeGen/RISCV/double-select-icmp.ll (revision 576d81baa5cf1801bae0fd05892be34acde33c6a) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2
3; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
4; RUN:   -target-abi=ilp32d | FileCheck %s
5; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
6; RUN:   -target-abi=lp64d | FileCheck %s
7; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \
8; RUN:   -target-abi=ilp32 | FileCheck -check-prefixes=RV32ZDINX %s
9; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \
10; RUN:   -target-abi=lp64 | FileCheck -check-prefixes=RV64ZDINX %s
11
12define double @select_icmp_eq(i32 signext %a, i32 signext %b, double %c, double %d) {
13; CHECK-LABEL: select_icmp_eq:
14; CHECK:       # %bb.0:
15; CHECK-NEXT:    beq a0, a1, .LBB0_2
16; CHECK-NEXT:  # %bb.1:
17; CHECK-NEXT:    fmv.d fa0, fa1
18; CHECK-NEXT:  .LBB0_2:
19; CHECK-NEXT:    ret
20;
21; RV32ZDINX-LABEL: select_icmp_eq:
22; RV32ZDINX:       # %bb.0:
23; RV32ZDINX-NEXT:    beq a0, a1, .LBB0_2
24; RV32ZDINX-NEXT:  # %bb.1:
25; RV32ZDINX-NEXT:    mv a2, a4
26; RV32ZDINX-NEXT:    mv a3, a5
27; RV32ZDINX-NEXT:  .LBB0_2:
28; RV32ZDINX-NEXT:    mv a0, a2
29; RV32ZDINX-NEXT:    mv a1, a3
30; RV32ZDINX-NEXT:    ret
31;
32; RV64ZDINX-LABEL: select_icmp_eq:
33; RV64ZDINX:       # %bb.0:
34; RV64ZDINX-NEXT:    beq a0, a1, .LBB0_2
35; RV64ZDINX-NEXT:  # %bb.1:
36; RV64ZDINX-NEXT:    mv a2, a3
37; RV64ZDINX-NEXT:  .LBB0_2:
38; RV64ZDINX-NEXT:    mv a0, a2
39; RV64ZDINX-NEXT:    ret
40  %1 = icmp eq i32 %a, %b
41  %2 = select i1 %1, double %c, double %d
42  ret double %2
43}
44
45define double @select_icmp_ne(i32 signext %a, i32 signext %b, double %c, double %d) {
46; CHECK-LABEL: select_icmp_ne:
47; CHECK:       # %bb.0:
48; CHECK-NEXT:    bne a0, a1, .LBB1_2
49; CHECK-NEXT:  # %bb.1:
50; CHECK-NEXT:    fmv.d fa0, fa1
51; CHECK-NEXT:  .LBB1_2:
52; CHECK-NEXT:    ret
53;
54; RV32ZDINX-LABEL: select_icmp_ne:
55; RV32ZDINX:       # %bb.0:
56; RV32ZDINX-NEXT:    bne a0, a1, .LBB1_2
57; RV32ZDINX-NEXT:  # %bb.1:
58; RV32ZDINX-NEXT:    mv a2, a4
59; RV32ZDINX-NEXT:    mv a3, a5
60; RV32ZDINX-NEXT:  .LBB1_2:
61; RV32ZDINX-NEXT:    mv a0, a2
62; RV32ZDINX-NEXT:    mv a1, a3
63; RV32ZDINX-NEXT:    ret
64;
65; RV64ZDINX-LABEL: select_icmp_ne:
66; RV64ZDINX:       # %bb.0:
67; RV64ZDINX-NEXT:    bne a0, a1, .LBB1_2
68; RV64ZDINX-NEXT:  # %bb.1:
69; RV64ZDINX-NEXT:    mv a2, a3
70; RV64ZDINX-NEXT:  .LBB1_2:
71; RV64ZDINX-NEXT:    mv a0, a2
72; RV64ZDINX-NEXT:    ret
73  %1 = icmp ne i32 %a, %b
74  %2 = select i1 %1, double %c, double %d
75  ret double %2
76}
77
78define double @select_icmp_ugt(i32 signext %a, i32 signext %b, double %c, double %d) {
79; CHECK-LABEL: select_icmp_ugt:
80; CHECK:       # %bb.0:
81; CHECK-NEXT:    bltu a1, a0, .LBB2_2
82; CHECK-NEXT:  # %bb.1:
83; CHECK-NEXT:    fmv.d fa0, fa1
84; CHECK-NEXT:  .LBB2_2:
85; CHECK-NEXT:    ret
86;
87; RV32ZDINX-LABEL: select_icmp_ugt:
88; RV32ZDINX:       # %bb.0:
89; RV32ZDINX-NEXT:    bltu a1, a0, .LBB2_2
90; RV32ZDINX-NEXT:  # %bb.1:
91; RV32ZDINX-NEXT:    mv a2, a4
92; RV32ZDINX-NEXT:    mv a3, a5
93; RV32ZDINX-NEXT:  .LBB2_2:
94; RV32ZDINX-NEXT:    mv a0, a2
95; RV32ZDINX-NEXT:    mv a1, a3
96; RV32ZDINX-NEXT:    ret
97;
98; RV64ZDINX-LABEL: select_icmp_ugt:
99; RV64ZDINX:       # %bb.0:
100; RV64ZDINX-NEXT:    bltu a1, a0, .LBB2_2
101; RV64ZDINX-NEXT:  # %bb.1:
102; RV64ZDINX-NEXT:    mv a2, a3
103; RV64ZDINX-NEXT:  .LBB2_2:
104; RV64ZDINX-NEXT:    mv a0, a2
105; RV64ZDINX-NEXT:    ret
106  %1 = icmp ugt i32 %a, %b
107  %2 = select i1 %1, double %c, double %d
108  ret double %2
109}
110
111define double @select_icmp_uge(i32 signext %a, i32 signext %b, double %c, double %d) {
112; CHECK-LABEL: select_icmp_uge:
113; CHECK:       # %bb.0:
114; CHECK-NEXT:    bgeu a0, a1, .LBB3_2
115; CHECK-NEXT:  # %bb.1:
116; CHECK-NEXT:    fmv.d fa0, fa1
117; CHECK-NEXT:  .LBB3_2:
118; CHECK-NEXT:    ret
119;
120; RV32ZDINX-LABEL: select_icmp_uge:
121; RV32ZDINX:       # %bb.0:
122; RV32ZDINX-NEXT:    bgeu a0, a1, .LBB3_2
123; RV32ZDINX-NEXT:  # %bb.1:
124; RV32ZDINX-NEXT:    mv a2, a4
125; RV32ZDINX-NEXT:    mv a3, a5
126; RV32ZDINX-NEXT:  .LBB3_2:
127; RV32ZDINX-NEXT:    mv a0, a2
128; RV32ZDINX-NEXT:    mv a1, a3
129; RV32ZDINX-NEXT:    ret
130;
131; RV64ZDINX-LABEL: select_icmp_uge:
132; RV64ZDINX:       # %bb.0:
133; RV64ZDINX-NEXT:    bgeu a0, a1, .LBB3_2
134; RV64ZDINX-NEXT:  # %bb.1:
135; RV64ZDINX-NEXT:    mv a2, a3
136; RV64ZDINX-NEXT:  .LBB3_2:
137; RV64ZDINX-NEXT:    mv a0, a2
138; RV64ZDINX-NEXT:    ret
139  %1 = icmp uge i32 %a, %b
140  %2 = select i1 %1, double %c, double %d
141  ret double %2
142}
143
144define double @select_icmp_ult(i32 signext %a, i32 signext %b, double %c, double %d) {
145; CHECK-LABEL: select_icmp_ult:
146; CHECK:       # %bb.0:
147; CHECK-NEXT:    bltu a0, a1, .LBB4_2
148; CHECK-NEXT:  # %bb.1:
149; CHECK-NEXT:    fmv.d fa0, fa1
150; CHECK-NEXT:  .LBB4_2:
151; CHECK-NEXT:    ret
152;
153; RV32ZDINX-LABEL: select_icmp_ult:
154; RV32ZDINX:       # %bb.0:
155; RV32ZDINX-NEXT:    bltu a0, a1, .LBB4_2
156; RV32ZDINX-NEXT:  # %bb.1:
157; RV32ZDINX-NEXT:    mv a2, a4
158; RV32ZDINX-NEXT:    mv a3, a5
159; RV32ZDINX-NEXT:  .LBB4_2:
160; RV32ZDINX-NEXT:    mv a0, a2
161; RV32ZDINX-NEXT:    mv a1, a3
162; RV32ZDINX-NEXT:    ret
163;
164; RV64ZDINX-LABEL: select_icmp_ult:
165; RV64ZDINX:       # %bb.0:
166; RV64ZDINX-NEXT:    bltu a0, a1, .LBB4_2
167; RV64ZDINX-NEXT:  # %bb.1:
168; RV64ZDINX-NEXT:    mv a2, a3
169; RV64ZDINX-NEXT:  .LBB4_2:
170; RV64ZDINX-NEXT:    mv a0, a2
171; RV64ZDINX-NEXT:    ret
172  %1 = icmp ult i32 %a, %b
173  %2 = select i1 %1, double %c, double %d
174  ret double %2
175}
176
177define double @select_icmp_ule(i32 signext %a, i32 signext %b, double %c, double %d) {
178; CHECK-LABEL: select_icmp_ule:
179; CHECK:       # %bb.0:
180; CHECK-NEXT:    bgeu a1, a0, .LBB5_2
181; CHECK-NEXT:  # %bb.1:
182; CHECK-NEXT:    fmv.d fa0, fa1
183; CHECK-NEXT:  .LBB5_2:
184; CHECK-NEXT:    ret
185;
186; RV32ZDINX-LABEL: select_icmp_ule:
187; RV32ZDINX:       # %bb.0:
188; RV32ZDINX-NEXT:    bgeu a1, a0, .LBB5_2
189; RV32ZDINX-NEXT:  # %bb.1:
190; RV32ZDINX-NEXT:    mv a2, a4
191; RV32ZDINX-NEXT:    mv a3, a5
192; RV32ZDINX-NEXT:  .LBB5_2:
193; RV32ZDINX-NEXT:    mv a0, a2
194; RV32ZDINX-NEXT:    mv a1, a3
195; RV32ZDINX-NEXT:    ret
196;
197; RV64ZDINX-LABEL: select_icmp_ule:
198; RV64ZDINX:       # %bb.0:
199; RV64ZDINX-NEXT:    bgeu a1, a0, .LBB5_2
200; RV64ZDINX-NEXT:  # %bb.1:
201; RV64ZDINX-NEXT:    mv a2, a3
202; RV64ZDINX-NEXT:  .LBB5_2:
203; RV64ZDINX-NEXT:    mv a0, a2
204; RV64ZDINX-NEXT:    ret
205  %1 = icmp ule i32 %a, %b
206  %2 = select i1 %1, double %c, double %d
207  ret double %2
208}
209
210define double @select_icmp_sgt(i32 signext %a, i32 signext %b, double %c, double %d) {
211; CHECK-LABEL: select_icmp_sgt:
212; CHECK:       # %bb.0:
213; CHECK-NEXT:    blt a1, a0, .LBB6_2
214; CHECK-NEXT:  # %bb.1:
215; CHECK-NEXT:    fmv.d fa0, fa1
216; CHECK-NEXT:  .LBB6_2:
217; CHECK-NEXT:    ret
218;
219; RV32ZDINX-LABEL: select_icmp_sgt:
220; RV32ZDINX:       # %bb.0:
221; RV32ZDINX-NEXT:    blt a1, a0, .LBB6_2
222; RV32ZDINX-NEXT:  # %bb.1:
223; RV32ZDINX-NEXT:    mv a2, a4
224; RV32ZDINX-NEXT:    mv a3, a5
225; RV32ZDINX-NEXT:  .LBB6_2:
226; RV32ZDINX-NEXT:    mv a0, a2
227; RV32ZDINX-NEXT:    mv a1, a3
228; RV32ZDINX-NEXT:    ret
229;
230; RV64ZDINX-LABEL: select_icmp_sgt:
231; RV64ZDINX:       # %bb.0:
232; RV64ZDINX-NEXT:    blt a1, a0, .LBB6_2
233; RV64ZDINX-NEXT:  # %bb.1:
234; RV64ZDINX-NEXT:    mv a2, a3
235; RV64ZDINX-NEXT:  .LBB6_2:
236; RV64ZDINX-NEXT:    mv a0, a2
237; RV64ZDINX-NEXT:    ret
238  %1 = icmp sgt i32 %a, %b
239  %2 = select i1 %1, double %c, double %d
240  ret double %2
241}
242
243define double @select_icmp_sge(i32 signext %a, i32 signext %b, double %c, double %d) {
244; CHECK-LABEL: select_icmp_sge:
245; CHECK:       # %bb.0:
246; CHECK-NEXT:    bge a0, a1, .LBB7_2
247; CHECK-NEXT:  # %bb.1:
248; CHECK-NEXT:    fmv.d fa0, fa1
249; CHECK-NEXT:  .LBB7_2:
250; CHECK-NEXT:    ret
251;
252; RV32ZDINX-LABEL: select_icmp_sge:
253; RV32ZDINX:       # %bb.0:
254; RV32ZDINX-NEXT:    bge a0, a1, .LBB7_2
255; RV32ZDINX-NEXT:  # %bb.1:
256; RV32ZDINX-NEXT:    mv a2, a4
257; RV32ZDINX-NEXT:    mv a3, a5
258; RV32ZDINX-NEXT:  .LBB7_2:
259; RV32ZDINX-NEXT:    mv a0, a2
260; RV32ZDINX-NEXT:    mv a1, a3
261; RV32ZDINX-NEXT:    ret
262;
263; RV64ZDINX-LABEL: select_icmp_sge:
264; RV64ZDINX:       # %bb.0:
265; RV64ZDINX-NEXT:    bge a0, a1, .LBB7_2
266; RV64ZDINX-NEXT:  # %bb.1:
267; RV64ZDINX-NEXT:    mv a2, a3
268; RV64ZDINX-NEXT:  .LBB7_2:
269; RV64ZDINX-NEXT:    mv a0, a2
270; RV64ZDINX-NEXT:    ret
271  %1 = icmp sge i32 %a, %b
272  %2 = select i1 %1, double %c, double %d
273  ret double %2
274}
275
276define double @select_icmp_slt(i32 signext %a, i32 signext %b, double %c, double %d) {
277; CHECK-LABEL: select_icmp_slt:
278; CHECK:       # %bb.0:
279; CHECK-NEXT:    blt a0, a1, .LBB8_2
280; CHECK-NEXT:  # %bb.1:
281; CHECK-NEXT:    fmv.d fa0, fa1
282; CHECK-NEXT:  .LBB8_2:
283; CHECK-NEXT:    ret
284;
285; RV32ZDINX-LABEL: select_icmp_slt:
286; RV32ZDINX:       # %bb.0:
287; RV32ZDINX-NEXT:    blt a0, a1, .LBB8_2
288; RV32ZDINX-NEXT:  # %bb.1:
289; RV32ZDINX-NEXT:    mv a2, a4
290; RV32ZDINX-NEXT:    mv a3, a5
291; RV32ZDINX-NEXT:  .LBB8_2:
292; RV32ZDINX-NEXT:    mv a0, a2
293; RV32ZDINX-NEXT:    mv a1, a3
294; RV32ZDINX-NEXT:    ret
295;
296; RV64ZDINX-LABEL: select_icmp_slt:
297; RV64ZDINX:       # %bb.0:
298; RV64ZDINX-NEXT:    blt a0, a1, .LBB8_2
299; RV64ZDINX-NEXT:  # %bb.1:
300; RV64ZDINX-NEXT:    mv a2, a3
301; RV64ZDINX-NEXT:  .LBB8_2:
302; RV64ZDINX-NEXT:    mv a0, a2
303; RV64ZDINX-NEXT:    ret
304  %1 = icmp slt i32 %a, %b
305  %2 = select i1 %1, double %c, double %d
306  ret double %2
307}
308
309define double @select_icmp_sle(i32 signext %a, i32 signext %b, double %c, double %d) {
310; CHECK-LABEL: select_icmp_sle:
311; CHECK:       # %bb.0:
312; CHECK-NEXT:    bge a1, a0, .LBB9_2
313; CHECK-NEXT:  # %bb.1:
314; CHECK-NEXT:    fmv.d fa0, fa1
315; CHECK-NEXT:  .LBB9_2:
316; CHECK-NEXT:    ret
317;
318; RV32ZDINX-LABEL: select_icmp_sle:
319; RV32ZDINX:       # %bb.0:
320; RV32ZDINX-NEXT:    bge a1, a0, .LBB9_2
321; RV32ZDINX-NEXT:  # %bb.1:
322; RV32ZDINX-NEXT:    mv a2, a4
323; RV32ZDINX-NEXT:    mv a3, a5
324; RV32ZDINX-NEXT:  .LBB9_2:
325; RV32ZDINX-NEXT:    mv a0, a2
326; RV32ZDINX-NEXT:    mv a1, a3
327; RV32ZDINX-NEXT:    ret
328;
329; RV64ZDINX-LABEL: select_icmp_sle:
330; RV64ZDINX:       # %bb.0:
331; RV64ZDINX-NEXT:    bge a1, a0, .LBB9_2
332; RV64ZDINX-NEXT:  # %bb.1:
333; RV64ZDINX-NEXT:    mv a2, a3
334; RV64ZDINX-NEXT:  .LBB9_2:
335; RV64ZDINX-NEXT:    mv a0, a2
336; RV64ZDINX-NEXT:    ret
337  %1 = icmp sle i32 %a, %b
338  %2 = select i1 %1, double %c, double %d
339  ret double %2
340}
341
342define double @select_icmp_slt_one(i32 signext %a) {
343; CHECK-LABEL: select_icmp_slt_one:
344; CHECK:       # %bb.0:
345; CHECK-NEXT:    slti a0, a0, 1
346; CHECK-NEXT:    fcvt.d.w fa0, a0
347; CHECK-NEXT:    ret
348;
349; RV32ZDINX-LABEL: select_icmp_slt_one:
350; RV32ZDINX:       # %bb.0:
351; RV32ZDINX-NEXT:    slti a0, a0, 1
352; RV32ZDINX-NEXT:    fcvt.d.w a0, a0
353; RV32ZDINX-NEXT:    ret
354;
355; RV64ZDINX-LABEL: select_icmp_slt_one:
356; RV64ZDINX:       # %bb.0:
357; RV64ZDINX-NEXT:    slti a0, a0, 1
358; RV64ZDINX-NEXT:    fcvt.d.w a0, a0
359; RV64ZDINX-NEXT:    ret
360  %1 = icmp slt i32 %a, 1
361  %2 = select i1 %1, double 1.000000e+00, double 0.000000e+00
362  ret double %2
363}
364
365define double @select_icmp_sgt_zero(i32 signext %a) {
366; CHECK-LABEL: select_icmp_sgt_zero:
367; CHECK:       # %bb.0:
368; CHECK-NEXT:    slti a0, a0, 1
369; CHECK-NEXT:    fcvt.d.w fa0, a0
370; CHECK-NEXT:    ret
371;
372; RV32ZDINX-LABEL: select_icmp_sgt_zero:
373; RV32ZDINX:       # %bb.0:
374; RV32ZDINX-NEXT:    slti a0, a0, 1
375; RV32ZDINX-NEXT:    fcvt.d.w a0, a0
376; RV32ZDINX-NEXT:    ret
377;
378; RV64ZDINX-LABEL: select_icmp_sgt_zero:
379; RV64ZDINX:       # %bb.0:
380; RV64ZDINX-NEXT:    slti a0, a0, 1
381; RV64ZDINX-NEXT:    fcvt.d.w a0, a0
382; RV64ZDINX-NEXT:    ret
383  %1 = icmp sgt i32 %a, 0
384  %2 = select i1 %1, double 0.000000e+00, double 1.000000e+00
385  ret double %2
386}
387