Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2 |
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#
2967e5f8 |
| 11-Oct-2024 |
Alex Bradbury <asb@igalia.com> |
[RISCV] Enable store clustering by default (#73796)
Builds on #73789, enabling store clustering by default using the same
heuristic.
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Revision tags: llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1 |
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#
7b0c4184 |
| 28-Mar-2023 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Move compressible registers to the beginning of the FP allocation order.
We don't have very many compressible FP instructions, just load and store. These instruction require the FP register
[RISCV] Move compressible registers to the beginning of the FP allocation order.
We don't have very many compressible FP instructions, just load and store. These instruction require the FP register to be f8-f15.
This patch changes the FP allocation order to prioritize f10-f15 first. These are also the FP argument registers. So I allocated them in reverse order starting at f15 to avoid taking the first argument registers. This appears to match gcc allocation order.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D146488
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Revision tags: llvmorg-16.0.0, llvmorg-16.0.0-rc4 |
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#
5fdab3c8 |
| 07-Mar-2023 |
wangpc <pc.wang@linux.alibaba.com> |
[RISCV] Enable machine copy propagation for copy-like instructions
Like what has been done in AArch64 (D125335).
We enable this under `-O2` to show the codegen diffs here but we may only do this un
[RISCV] Enable machine copy propagation for copy-like instructions
Like what has been done in AArch64 (D125335).
We enable this under `-O2` to show the codegen diffs here but we may only do this under `-O3` like AArch64.
There are two cases that we may produce these eliminable copies: 1. ISel of `FrameIndex`. Like `rvv/fixed-vectors-calling-conv.ll`. 2. Tail duplication. Like `select-optimize-multiple.ll`.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D144535
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Revision tags: llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2 |
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#
d02b9869 |
| 31-Jan-2023 |
Han-Kuan Chen <hankuan.chen@sifive.com> |
[RISCV] Don't use constantpool for floating-point value if the value can be easily constructed by integer sequence and a floating-point move.
In addition, this commit does the following combine
vfm
[RISCV] Don't use constantpool for floating-point value if the value can be easily constructed by integer sequence and a floating-point move.
In addition, this commit does the following combine
vfmv.v.f + fmv.[dhw].x -> vmv.v.x vfmv.s.f + fmv.[dhw].x -> vmv.s.x vfmerge.vfm + fmv.[dhw].x -> vmerge.vxm
Differential Revision: https://reviews.llvm.org/D142953
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Revision tags: llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
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#
df7ab6a5 |
| 01-Dec-2022 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Add ANDI to getRegAllocationHints.
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Revision tags: llvmorg-15.0.6 |
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#
a2b5b584 |
| 25-Nov-2022 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Use register allocation hints to improve use of compressed instructions.
Compressed instructions usually require one of the source registers to also be the source register. The register allo
[RISCV] Use register allocation hints to improve use of compressed instructions.
Compressed instructions usually require one of the source registers to also be the source register. The register allocator doesn't have that bias on its own.
This patch adds register allocation hints to introduce this bias. I've started with ADDI, ADDIW, and SLLI. These all have a 5-bit field for the register. If the source and dest register are the same they are guaranteed to compress as long as the immediate is also 6 bits.
This code was inspired by similar code from the SystemZ target.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D138242
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Revision tags: llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2 |
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#
70a64fe7 |
| 21-Sep-2022 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Remove support for the unratified Zbt extension.
This extension does not appear to be on its way to ratification.
Out of the unratified bitmanip extensions, this one had the largest impact
[RISCV] Remove support for the unratified Zbt extension.
This extension does not appear to be on its way to ratification.
Out of the unratified bitmanip extensions, this one had the largest impact on the compiler.
Posting this patch to start a discussion about whether we should remove these extensions. We'll talk more at the RISC-V sync meeting this Thursday.
Reviewed By: asb, reames
Differential Revision: https://reviews.llvm.org/D133834
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Revision tags: llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init |
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#
3f68f0f8 |
| 09-Jul-2022 |
LiaoChunyu <chunyu@iscas.ac.cn> |
[RISCV] Optimize 2x SELECT for floating-point types
Including the following opcode: Select_FPR16_Using_CC_GPR Select_FPR32_Using_CC_GPR Select_FPR64_Using_CC_GPR
Reviewed By: craig.topper
Diffe
[RISCV] Optimize 2x SELECT for floating-point types
Including the following opcode: Select_FPR16_Using_CC_GPR Select_FPR32_Using_CC_GPR Select_FPR64_Using_CC_GPR
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D127871
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#
bf1758c3 |
| 07-Jul-2022 |
Diego Caballero <diegocaballero@google.com> |
Revert "[RISCV] Optimize 2x SELECT for floating-point types"
This reverts commit 1178992c72b002c3b2c87203252c566eeb273cc1.
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Revision tags: llvmorg-14.0.6 |
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#
1178992c |
| 16-Jun-2022 |
LiaoChunyu <chunyu@iscas.ac.cn> |
[RISCV] Optimize 2x SELECT for floating-point types
Including the following opcode: Select_FPR16_Using_CC_GPR Select_FPR32_Using_CC_GPR Select_FPR64_Using_CC_GPR
Reviewed By: craig.topper
Diffe
[RISCV] Optimize 2x SELECT for floating-point types
Including the following opcode: Select_FPR16_Using_CC_GPR Select_FPR32_Using_CC_GPR Select_FPR64_Using_CC_GPR
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D127871
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Revision tags: llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2 |
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#
4e115b7d |
| 25-Feb-2022 |
Zakk Chen <zakk.chen@sifive.com> |
[RISCV] Update computeTargetABI from llc as well as clang
Clang computes the default ABI if -mabi is empty and encode it in LLVM IR module flag since D105555. For correctness, llc need to give the s
[RISCV] Update computeTargetABI from llc as well as clang
Clang computes the default ABI if -mabi is empty and encode it in LLVM IR module flag since D105555. For correctness, llc need to give the same target-abi (Options.MCOptions.ABIName) with ABI encoded in IR. The getSubtargetImpl already has a check for them only if Options.MCOptions.ABIName is not empty.
In order to get more robustness we could have a check for explicit ABI, but now we have two different logic to compute the default ABI.
The front-end ABI is defautl to the ilp32/ilp32e/lp64, and ilp32d/lp64d when hardware support for extension D. The backend ABI is default to the ilp32/ilp32e/lp64.
Reviewed by: asb, jrtc27
Differential Revision: https://reviews.llvm.org/D118333
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Revision tags: llvmorg-14.0.0-rc1, llvmorg-15-init |
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#
8def89b5 |
| 21-Jan-2022 |
wangpc <pc.wang@linux.alibaba.com> |
[RISCV] Set CostPerUse to 1 iff RVC is enabled
After D86836, we can define multiple cost values for different cost models. So here we set CostPerUse to 1 iff RVC is enabled to avoid potential impact
[RISCV] Set CostPerUse to 1 iff RVC is enabled
After D86836, we can define multiple cost values for different cost models. So here we set CostPerUse to 1 iff RVC is enabled to avoid potential impact on RA.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D117741
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Revision tags: llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1 |
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#
af0ecfcc |
| 22-Nov-2021 |
wangpc <pc.wang@linux.alibaba.com> |
[RISCV] Generate pseudo instruction li
Add an alias of `addi [x], zero, imm` to generate pseudo instruction li, which makes assembly mush more readable. For existed tests, users can update them by r
[RISCV] Generate pseudo instruction li
Add an alias of `addi [x], zero, imm` to generate pseudo instruction li, which makes assembly mush more readable. For existed tests, users can update them by running script `llvm/utils/update_llc_test_checks.py`.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D112692
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Revision tags: llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init |
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#
d65e8ee5 |
| 22-Jan-2021 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Add more cmov isel patterns to handle seteq/ne with a small non-zero immediate.
Similar to our free standing setcc patterns, we can use ADDI to subtract the immediate from the other operand.
[RISCV] Add more cmov isel patterns to handle seteq/ne with a small non-zero immediate.
Similar to our free standing setcc patterns, we can use ADDI to subtract the immediate from the other operand. Then the cmov can check if the result is zero or non-zero.
Reviewed By: mundaym
Differential Revision: https://reviews.llvm.org/D95169
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Revision tags: llvmorg-11.1.0-rc2 |
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#
4ab0f51a |
| 21-Jan-2021 |
Michael Munday <mike.munday@lowrisc.org> |
Recommit "[RISCV] Legalize select when Zbt extension available"
This recommits 71ed4b6ce57d8843ef705af8f98305976a8f107a with the polarity of some of the pattern corrected.
Original commit message:
Recommit "[RISCV] Legalize select when Zbt extension available"
This recommits 71ed4b6ce57d8843ef705af8f98305976a8f107a with the polarity of some of the pattern corrected.
Original commit message: The custom expansion of select operations in the RISC-V backend interferes with the matching of cmov instructions. Legalizing select when the Zbt extension is available solves that problem.
Reviewed By: luismarques, craig.topper
Differential Revision: https://reviews.llvm.org/D93767
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#
b42ff9fb |
| 18-Jan-2021 |
Michael Munday <mike.munday@lowrisc.org> |
[RISCV][NFC] Increase test coverage of Zbt extension
Add Zbt (ternary) extension code generation to the select lowering tests since it can have a significant impact on how select is lowered.
While
[RISCV][NFC] Increase test coverage of Zbt extension
Add Zbt (ternary) extension code generation to the select lowering tests since it can have a significant impact on how select is lowered.
While we are here make the neg-abs commands more consistent with the other tests.
Reviewed By: lenary
Differential Revision: https://reviews.llvm.org/D94798
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Revision tags: llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1 |
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#
6b0fc1f3 |
| 19-Nov-2020 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Add MemOperand to the instruction created by storeRegToStackSlot/loadRegFromStackSlot
Differential Revision: https://reviews.llvm.org/D91730
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#
24a31922 |
| 02-Nov-2020 |
Chen Zheng <czhengsz@cn.ibm.com> |
[MachineSink] sink more profitable loads
Reviewed By: qcolombet
Differential Revision: https://reviews.llvm.org/D86864
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Revision tags: llvmorg-11.0.0, llvmorg-11.0.0-rc6, llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2, llvmorg-11.0.0-rc1, llvmorg-12-init, llvmorg-10.0.1, llvmorg-10.0.1-rc4, llvmorg-10.0.1-rc3, llvmorg-10.0.1-rc2, llvmorg-10.0.1-rc1, llvmorg-10.0.0, llvmorg-10.0.0-rc6, llvmorg-10.0.0-rc5, llvmorg-10.0.0-rc4, llvmorg-10.0.0-rc3, llvmorg-10.0.0-rc2, llvmorg-10.0.0-rc1, llvmorg-11-init, llvmorg-9.0.1, llvmorg-9.0.1-rc3, llvmorg-9.0.1-rc2, llvmorg-9.0.1-rc1, llvmorg-9.0.0 |
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#
3d0fbafd |
| 17-Sep-2019 |
Luis Marques <luismarques@lowrisc.org> |
[RISCV] Switch to the Machine Scheduler
Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact.
Differential Revisio
[RISCV] Switch to the Machine Scheduler
Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact.
Differential Revision: https://reviews.llvm.org/D66973
llvm-svn: 372106
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#
2d550d19 |
| 17-Sep-2019 |
Luis Marques <luismarques@lowrisc.org> |
Revert Patch from Phabricator
This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04)
llvm-svn: 372104
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Revision tags: llvmorg-9.0.0-rc6 |
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#
e38695a0 |
| 17-Sep-2019 |
Luis Marques <luismarques@lowrisc.org> |
Patch from Phabricator
llvm-svn: 372092
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Revision tags: llvmorg-9.0.0-rc5, llvmorg-9.0.0-rc4, llvmorg-9.0.0-rc3, llvmorg-9.0.0-rc2 |
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#
b12056bd |
| 06-Aug-2019 |
Shiva Chen <shiva0217@gmail.com> |
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
Differential Revision: https://reviews.llvm.org/D65434
llvm-svn: 367960
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Revision tags: llvmorg-9.0.0-rc1, llvmorg-10-init, llvmorg-8.0.1, llvmorg-8.0.1-rc4, llvmorg-8.0.1-rc3, llvmorg-8.0.1-rc2, llvmorg-8.0.1-rc1 |
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#
b9e78c39 |
| 22-Mar-2019 |
Alex Bradbury <asb@lowrisc.org> |
[RISCV] Optimize emission of SELECT sequences
This patch optimizes the emission of a sequence of SELECTs with the same condition, avoiding the insertion of unnecessary control flow. Such a sequence
[RISCV] Optimize emission of SELECT sequences
This patch optimizes the emission of a sequence of SELECTs with the same condition, avoiding the insertion of unnecessary control flow. Such a sequence often occurs when a SELECT of values wider than XLEN is legalized into two SELECTs with legal types. We have identified several use cases where the SELECTs could be interleaved with other instructions. Therefore, we extend the sequence to include non-SELECT instructions if we are able to detect that the non-SELECT instructions do not impact the optimization.
This patch supersedes https://reviews.llvm.org/D59096, which attempted to address this issue by introducing a new SelectionDAG node. Hat tip to Eli Friedman for his feedback on how to best handle this issue.
Differential Revision: https://reviews.llvm.org/D59355 Patch by Luís Marques.
llvm-svn: 356741
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