xref: /llvm-project/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll (revision 3d0fbafd0bce43bb9106230a45d1130f7a40e5ec) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV32I
4; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s -check-prefix=RV64I
6
7; Selects of wide values are split into two selects, which can easily cause
8; unnecessary control flow. Here we check some cases where we can currently
9; emit a sequence of selects with shared control flow.
10
11define i64 @cmovcc64(i32 signext %a, i64 %b, i64 %c) nounwind {
12; RV32I-LABEL: cmovcc64:
13; RV32I:       # %bb.0: # %entry
14; RV32I-NEXT:    addi a5, zero, 123
15; RV32I-NEXT:    beq a0, a5, .LBB0_2
16; RV32I-NEXT:  # %bb.1: # %entry
17; RV32I-NEXT:    mv a1, a3
18; RV32I-NEXT:    mv a2, a4
19; RV32I-NEXT:  .LBB0_2: # %entry
20; RV32I-NEXT:    mv a0, a1
21; RV32I-NEXT:    mv a1, a2
22; RV32I-NEXT:    ret
23;
24; RV64I-LABEL: cmovcc64:
25; RV64I:       # %bb.0: # %entry
26; RV64I-NEXT:    addi a3, zero, 123
27; RV64I-NEXT:    beq a0, a3, .LBB0_2
28; RV64I-NEXT:  # %bb.1: # %entry
29; RV64I-NEXT:    mv a1, a2
30; RV64I-NEXT:  .LBB0_2: # %entry
31; RV64I-NEXT:    mv a0, a1
32; RV64I-NEXT:    ret
33entry:
34  %cmp = icmp eq i32 %a, 123
35  %cond = select i1 %cmp, i64 %b, i64 %c
36  ret i64 %cond
37}
38
39define i128 @cmovcc128(i64 signext %a, i128 %b, i128 %c) nounwind {
40; RV32I-LABEL: cmovcc128:
41; RV32I:       # %bb.0: # %entry
42; RV32I-NEXT:    xori a1, a1, 123
43; RV32I-NEXT:    or a2, a1, a2
44; RV32I-NEXT:    mv a1, a3
45; RV32I-NEXT:    beqz a2, .LBB1_2
46; RV32I-NEXT:  # %bb.1: # %entry
47; RV32I-NEXT:    mv a1, a4
48; RV32I-NEXT:  .LBB1_2: # %entry
49; RV32I-NEXT:    lw a6, 0(a1)
50; RV32I-NEXT:    beqz a2, .LBB1_6
51; RV32I-NEXT:  # %bb.3: # %entry
52; RV32I-NEXT:    addi a1, a4, 4
53; RV32I-NEXT:    lw a5, 0(a1)
54; RV32I-NEXT:    bnez a2, .LBB1_7
55; RV32I-NEXT:  .LBB1_4:
56; RV32I-NEXT:    addi a1, a3, 8
57; RV32I-NEXT:    lw a1, 0(a1)
58; RV32I-NEXT:    bnez a2, .LBB1_8
59; RV32I-NEXT:  .LBB1_5:
60; RV32I-NEXT:    addi a2, a3, 12
61; RV32I-NEXT:    j .LBB1_9
62; RV32I-NEXT:  .LBB1_6:
63; RV32I-NEXT:    addi a1, a3, 4
64; RV32I-NEXT:    lw a5, 0(a1)
65; RV32I-NEXT:    beqz a2, .LBB1_4
66; RV32I-NEXT:  .LBB1_7: # %entry
67; RV32I-NEXT:    addi a1, a4, 8
68; RV32I-NEXT:    lw a1, 0(a1)
69; RV32I-NEXT:    beqz a2, .LBB1_5
70; RV32I-NEXT:  .LBB1_8: # %entry
71; RV32I-NEXT:    addi a2, a4, 12
72; RV32I-NEXT:  .LBB1_9: # %entry
73; RV32I-NEXT:    lw a2, 0(a2)
74; RV32I-NEXT:    sw a2, 12(a0)
75; RV32I-NEXT:    sw a1, 8(a0)
76; RV32I-NEXT:    sw a5, 4(a0)
77; RV32I-NEXT:    sw a6, 0(a0)
78; RV32I-NEXT:    ret
79;
80; RV64I-LABEL: cmovcc128:
81; RV64I:       # %bb.0: # %entry
82; RV64I-NEXT:    addi a5, zero, 123
83; RV64I-NEXT:    beq a0, a5, .LBB1_2
84; RV64I-NEXT:  # %bb.1: # %entry
85; RV64I-NEXT:    mv a1, a3
86; RV64I-NEXT:    mv a2, a4
87; RV64I-NEXT:  .LBB1_2: # %entry
88; RV64I-NEXT:    mv a0, a1
89; RV64I-NEXT:    mv a1, a2
90; RV64I-NEXT:    ret
91entry:
92  %cmp = icmp eq i64 %a, 123
93  %cond = select i1 %cmp, i128 %b, i128 %c
94  ret i128 %cond
95}
96
97define i64 @cmov64(i1 %a, i64 %b, i64 %c) nounwind {
98; RV32I-LABEL: cmov64:
99; RV32I:       # %bb.0: # %entry
100; RV32I-NEXT:    andi a5, a0, 1
101; RV32I-NEXT:    mv a0, a1
102; RV32I-NEXT:    bnez a5, .LBB2_2
103; RV32I-NEXT:  # %bb.1: # %entry
104; RV32I-NEXT:    mv a0, a3
105; RV32I-NEXT:    mv a2, a4
106; RV32I-NEXT:  .LBB2_2: # %entry
107; RV32I-NEXT:    mv a1, a2
108; RV32I-NEXT:    ret
109;
110; RV64I-LABEL: cmov64:
111; RV64I:       # %bb.0: # %entry
112; RV64I-NEXT:    andi a3, a0, 1
113; RV64I-NEXT:    mv a0, a1
114; RV64I-NEXT:    bnez a3, .LBB2_2
115; RV64I-NEXT:  # %bb.1: # %entry
116; RV64I-NEXT:    mv a0, a2
117; RV64I-NEXT:  .LBB2_2: # %entry
118; RV64I-NEXT:    ret
119entry:
120  %cond = select i1 %a, i64 %b, i64 %c
121  ret i64 %cond
122}
123
124define i128 @cmov128(i1 %a, i128 %b, i128 %c) nounwind {
125; RV32I-LABEL: cmov128:
126; RV32I:       # %bb.0: # %entry
127; RV32I-NEXT:    andi a4, a1, 1
128; RV32I-NEXT:    mv a1, a2
129; RV32I-NEXT:    bnez a4, .LBB3_2
130; RV32I-NEXT:  # %bb.1: # %entry
131; RV32I-NEXT:    mv a1, a3
132; RV32I-NEXT:  .LBB3_2: # %entry
133; RV32I-NEXT:    lw a6, 0(a1)
134; RV32I-NEXT:    bnez a4, .LBB3_6
135; RV32I-NEXT:  # %bb.3: # %entry
136; RV32I-NEXT:    addi a1, a3, 4
137; RV32I-NEXT:    lw a5, 0(a1)
138; RV32I-NEXT:    beqz a4, .LBB3_7
139; RV32I-NEXT:  .LBB3_4:
140; RV32I-NEXT:    addi a1, a2, 8
141; RV32I-NEXT:    lw a1, 0(a1)
142; RV32I-NEXT:    beqz a4, .LBB3_8
143; RV32I-NEXT:  .LBB3_5:
144; RV32I-NEXT:    addi a2, a2, 12
145; RV32I-NEXT:    j .LBB3_9
146; RV32I-NEXT:  .LBB3_6:
147; RV32I-NEXT:    addi a1, a2, 4
148; RV32I-NEXT:    lw a5, 0(a1)
149; RV32I-NEXT:    bnez a4, .LBB3_4
150; RV32I-NEXT:  .LBB3_7: # %entry
151; RV32I-NEXT:    addi a1, a3, 8
152; RV32I-NEXT:    lw a1, 0(a1)
153; RV32I-NEXT:    bnez a4, .LBB3_5
154; RV32I-NEXT:  .LBB3_8: # %entry
155; RV32I-NEXT:    addi a2, a3, 12
156; RV32I-NEXT:  .LBB3_9: # %entry
157; RV32I-NEXT:    lw a2, 0(a2)
158; RV32I-NEXT:    sw a2, 12(a0)
159; RV32I-NEXT:    sw a1, 8(a0)
160; RV32I-NEXT:    sw a5, 4(a0)
161; RV32I-NEXT:    sw a6, 0(a0)
162; RV32I-NEXT:    ret
163;
164; RV64I-LABEL: cmov128:
165; RV64I:       # %bb.0: # %entry
166; RV64I-NEXT:    andi a5, a0, 1
167; RV64I-NEXT:    mv a0, a1
168; RV64I-NEXT:    bnez a5, .LBB3_2
169; RV64I-NEXT:  # %bb.1: # %entry
170; RV64I-NEXT:    mv a0, a3
171; RV64I-NEXT:    mv a2, a4
172; RV64I-NEXT:  .LBB3_2: # %entry
173; RV64I-NEXT:    mv a1, a2
174; RV64I-NEXT:    ret
175entry:
176  %cond = select i1 %a, i128 %b, i128 %c
177  ret i128 %cond
178}
179
180define float @cmovfloat(i1 %a, float %b, float %c, float %d, float %e) nounwind {
181; RV32I-LABEL: cmovfloat:
182; RV32I:       # %bb.0: # %entry
183; RV32I-NEXT:    andi a0, a0, 1
184; RV32I-NEXT:    bnez a0, .LBB4_2
185; RV32I-NEXT:  # %bb.1: # %entry
186; RV32I-NEXT:    fmv.w.x ft0, a4
187; RV32I-NEXT:    fmv.w.x ft1, a2
188; RV32I-NEXT:    j .LBB4_3
189; RV32I-NEXT:  .LBB4_2:
190; RV32I-NEXT:    fmv.w.x ft0, a3
191; RV32I-NEXT:    fmv.w.x ft1, a1
192; RV32I-NEXT:  .LBB4_3: # %entry
193; RV32I-NEXT:    fadd.s ft0, ft1, ft0
194; RV32I-NEXT:    fmv.x.w a0, ft0
195; RV32I-NEXT:    ret
196;
197; RV64I-LABEL: cmovfloat:
198; RV64I:       # %bb.0: # %entry
199; RV64I-NEXT:    andi a0, a0, 1
200; RV64I-NEXT:    bnez a0, .LBB4_2
201; RV64I-NEXT:  # %bb.1: # %entry
202; RV64I-NEXT:    fmv.w.x ft0, a4
203; RV64I-NEXT:    fmv.w.x ft1, a2
204; RV64I-NEXT:    j .LBB4_3
205; RV64I-NEXT:  .LBB4_2:
206; RV64I-NEXT:    fmv.w.x ft0, a3
207; RV64I-NEXT:    fmv.w.x ft1, a1
208; RV64I-NEXT:  .LBB4_3: # %entry
209; RV64I-NEXT:    fadd.s ft0, ft1, ft0
210; RV64I-NEXT:    fmv.x.w a0, ft0
211; RV64I-NEXT:    ret
212entry:
213  %cond1 = select i1 %a, float %b, float %c
214  %cond2 = select i1 %a, float %d, float %e
215  %ret = fadd float %cond1, %cond2
216  ret float %ret
217}
218
219define double @cmovdouble(i1 %a, double %b, double %c) nounwind {
220; RV32I-LABEL: cmovdouble:
221; RV32I:       # %bb.0: # %entry
222; RV32I-NEXT:    addi sp, sp, -16
223; RV32I-NEXT:    sw a3, 8(sp)
224; RV32I-NEXT:    sw a4, 12(sp)
225; RV32I-NEXT:    fld ft0, 8(sp)
226; RV32I-NEXT:    sw a1, 8(sp)
227; RV32I-NEXT:    sw a2, 12(sp)
228; RV32I-NEXT:    fld ft1, 8(sp)
229; RV32I-NEXT:    andi a0, a0, 1
230; RV32I-NEXT:    bnez a0, .LBB5_2
231; RV32I-NEXT:  # %bb.1: # %entry
232; RV32I-NEXT:    fmv.d ft1, ft0
233; RV32I-NEXT:  .LBB5_2: # %entry
234; RV32I-NEXT:    fsd ft1, 8(sp)
235; RV32I-NEXT:    lw a0, 8(sp)
236; RV32I-NEXT:    lw a1, 12(sp)
237; RV32I-NEXT:    addi sp, sp, 16
238; RV32I-NEXT:    ret
239;
240; RV64I-LABEL: cmovdouble:
241; RV64I:       # %bb.0: # %entry
242; RV64I-NEXT:    andi a0, a0, 1
243; RV64I-NEXT:    bnez a0, .LBB5_2
244; RV64I-NEXT:  # %bb.1: # %entry
245; RV64I-NEXT:    fmv.d.x ft0, a2
246; RV64I-NEXT:    fmv.x.d a0, ft0
247; RV64I-NEXT:    ret
248; RV64I-NEXT:  .LBB5_2:
249; RV64I-NEXT:    fmv.d.x ft0, a1
250; RV64I-NEXT:    fmv.x.d a0, ft0
251; RV64I-NEXT:    ret
252entry:
253  %cond = select i1 %a, double %b, double %c
254  ret double %cond
255}
256
257; Check that selects with dependencies on previous ones aren't incorrectly
258; optimized.
259
260define i32 @cmovccdep(i32 signext %a, i32 %b, i32 %c, i32 %d) nounwind {
261; RV32I-LABEL: cmovccdep:
262; RV32I:       # %bb.0: # %entry
263; RV32I-NEXT:    addi a4, zero, 123
264; RV32I-NEXT:    bne a0, a4, .LBB6_3
265; RV32I-NEXT:  # %bb.1: # %entry
266; RV32I-NEXT:    mv a2, a1
267; RV32I-NEXT:    bne a0, a4, .LBB6_4
268; RV32I-NEXT:  .LBB6_2: # %entry
269; RV32I-NEXT:    add a0, a1, a2
270; RV32I-NEXT:    ret
271; RV32I-NEXT:  .LBB6_3: # %entry
272; RV32I-NEXT:    mv a1, a2
273; RV32I-NEXT:    mv a2, a1
274; RV32I-NEXT:    beq a0, a4, .LBB6_2
275; RV32I-NEXT:  .LBB6_4: # %entry
276; RV32I-NEXT:    mv a2, a3
277; RV32I-NEXT:    add a0, a1, a2
278; RV32I-NEXT:    ret
279;
280; RV64I-LABEL: cmovccdep:
281; RV64I:       # %bb.0: # %entry
282; RV64I-NEXT:    addi a4, zero, 123
283; RV64I-NEXT:    bne a0, a4, .LBB6_3
284; RV64I-NEXT:  # %bb.1: # %entry
285; RV64I-NEXT:    mv a2, a1
286; RV64I-NEXT:    bne a0, a4, .LBB6_4
287; RV64I-NEXT:  .LBB6_2: # %entry
288; RV64I-NEXT:    addw a0, a1, a2
289; RV64I-NEXT:    ret
290; RV64I-NEXT:  .LBB6_3: # %entry
291; RV64I-NEXT:    mv a1, a2
292; RV64I-NEXT:    mv a2, a1
293; RV64I-NEXT:    beq a0, a4, .LBB6_2
294; RV64I-NEXT:  .LBB6_4: # %entry
295; RV64I-NEXT:    mv a2, a3
296; RV64I-NEXT:    addw a0, a1, a2
297; RV64I-NEXT:    ret
298entry:
299  %cmp = icmp eq i32 %a, 123
300  %cond1 = select i1 %cmp, i32 %b, i32 %c
301  %cond2 = select i1 %cmp, i32 %cond1, i32 %d
302  %ret = add i32 %cond1, %cond2
303  ret i32 %ret
304}
305
306; Check that selects with different conditions aren't incorrectly optimized.
307
308define i32 @cmovdiffcc(i1 %a, i1 %b, i32 %c, i32 %d, i32 %e, i32 %f) nounwind {
309; RV32I-LABEL: cmovdiffcc:
310; RV32I:       # %bb.0: # %entry
311; RV32I-NEXT:    andi a0, a0, 1
312; RV32I-NEXT:    andi a1, a1, 1
313; RV32I-NEXT:    beqz a0, .LBB7_3
314; RV32I-NEXT:  # %bb.1: # %entry
315; RV32I-NEXT:    beqz a1, .LBB7_4
316; RV32I-NEXT:  .LBB7_2: # %entry
317; RV32I-NEXT:    add a0, a2, a4
318; RV32I-NEXT:    ret
319; RV32I-NEXT:  .LBB7_3: # %entry
320; RV32I-NEXT:    mv a2, a3
321; RV32I-NEXT:    bnez a1, .LBB7_2
322; RV32I-NEXT:  .LBB7_4: # %entry
323; RV32I-NEXT:    mv a4, a5
324; RV32I-NEXT:    add a0, a2, a4
325; RV32I-NEXT:    ret
326;
327; RV64I-LABEL: cmovdiffcc:
328; RV64I:       # %bb.0: # %entry
329; RV64I-NEXT:    andi a0, a0, 1
330; RV64I-NEXT:    andi a1, a1, 1
331; RV64I-NEXT:    beqz a0, .LBB7_3
332; RV64I-NEXT:  # %bb.1: # %entry
333; RV64I-NEXT:    beqz a1, .LBB7_4
334; RV64I-NEXT:  .LBB7_2: # %entry
335; RV64I-NEXT:    addw a0, a2, a4
336; RV64I-NEXT:    ret
337; RV64I-NEXT:  .LBB7_3: # %entry
338; RV64I-NEXT:    mv a2, a3
339; RV64I-NEXT:    bnez a1, .LBB7_2
340; RV64I-NEXT:  .LBB7_4: # %entry
341; RV64I-NEXT:    mv a4, a5
342; RV64I-NEXT:    addw a0, a2, a4
343; RV64I-NEXT:    ret
344entry:
345  %cond1 = select i1 %a, i32 %c, i32 %d
346  %cond2 = select i1 %b, i32 %e, i32 %f
347  %ret = add i32 %cond1, %cond2
348  ret i32 %ret
349}
350