xref: /llvm-project/llvm/test/CodeGen/RISCV/double-select-fcmp.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
3; RUN:   -target-abi=ilp32d | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
5; RUN:   -target-abi=lp64d | FileCheck %s
6; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \
7; RUN:   -target-abi=ilp32 | FileCheck --check-prefix=CHECKRV32ZDINX %s
8; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \
9; RUN:   -target-abi=lp64 | FileCheck --check-prefix=CHECKRV64ZDINX %s
10
11define double @select_fcmp_false(double %a, double %b) nounwind {
12; CHECK-LABEL: select_fcmp_false:
13; CHECK:       # %bb.0:
14; CHECK-NEXT:    fmv.d fa0, fa1
15; CHECK-NEXT:    ret
16;
17; CHECKRV32ZDINX-LABEL: select_fcmp_false:
18; CHECKRV32ZDINX:       # %bb.0:
19; CHECKRV32ZDINX-NEXT:    mv a1, a3
20; CHECKRV32ZDINX-NEXT:    mv a0, a2
21; CHECKRV32ZDINX-NEXT:    ret
22;
23; CHECKRV64ZDINX-LABEL: select_fcmp_false:
24; CHECKRV64ZDINX:       # %bb.0:
25; CHECKRV64ZDINX-NEXT:    mv a0, a1
26; CHECKRV64ZDINX-NEXT:    ret
27  %1 = fcmp false double %a, %b
28  %2 = select i1 %1, double %a, double %b
29  ret double %2
30}
31
32define double @select_fcmp_oeq(double %a, double %b) nounwind {
33; CHECK-LABEL: select_fcmp_oeq:
34; CHECK:       # %bb.0:
35; CHECK-NEXT:    feq.d a0, fa0, fa1
36; CHECK-NEXT:    bnez a0, .LBB1_2
37; CHECK-NEXT:  # %bb.1:
38; CHECK-NEXT:    fmv.d fa0, fa1
39; CHECK-NEXT:  .LBB1_2:
40; CHECK-NEXT:    ret
41;
42; CHECKRV32ZDINX-LABEL: select_fcmp_oeq:
43; CHECKRV32ZDINX:       # %bb.0:
44; CHECKRV32ZDINX-NEXT:    feq.d a4, a0, a2
45; CHECKRV32ZDINX-NEXT:    bnez a4, .LBB1_2
46; CHECKRV32ZDINX-NEXT:  # %bb.1:
47; CHECKRV32ZDINX-NEXT:    mv a0, a2
48; CHECKRV32ZDINX-NEXT:    mv a1, a3
49; CHECKRV32ZDINX-NEXT:  .LBB1_2:
50; CHECKRV32ZDINX-NEXT:    ret
51;
52; CHECKRV64ZDINX-LABEL: select_fcmp_oeq:
53; CHECKRV64ZDINX:       # %bb.0:
54; CHECKRV64ZDINX-NEXT:    feq.d a2, a0, a1
55; CHECKRV64ZDINX-NEXT:    bnez a2, .LBB1_2
56; CHECKRV64ZDINX-NEXT:  # %bb.1:
57; CHECKRV64ZDINX-NEXT:    mv a0, a1
58; CHECKRV64ZDINX-NEXT:  .LBB1_2:
59; CHECKRV64ZDINX-NEXT:    ret
60  %1 = fcmp oeq double %a, %b
61  %2 = select i1 %1, double %a, double %b
62  ret double %2
63}
64
65define double @select_fcmp_ogt(double %a, double %b) nounwind {
66; CHECK-LABEL: select_fcmp_ogt:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    flt.d a0, fa1, fa0
69; CHECK-NEXT:    bnez a0, .LBB2_2
70; CHECK-NEXT:  # %bb.1:
71; CHECK-NEXT:    fmv.d fa0, fa1
72; CHECK-NEXT:  .LBB2_2:
73; CHECK-NEXT:    ret
74;
75; CHECKRV32ZDINX-LABEL: select_fcmp_ogt:
76; CHECKRV32ZDINX:       # %bb.0:
77; CHECKRV32ZDINX-NEXT:    flt.d a4, a2, a0
78; CHECKRV32ZDINX-NEXT:    bnez a4, .LBB2_2
79; CHECKRV32ZDINX-NEXT:  # %bb.1:
80; CHECKRV32ZDINX-NEXT:    mv a0, a2
81; CHECKRV32ZDINX-NEXT:    mv a1, a3
82; CHECKRV32ZDINX-NEXT:  .LBB2_2:
83; CHECKRV32ZDINX-NEXT:    ret
84;
85; CHECKRV64ZDINX-LABEL: select_fcmp_ogt:
86; CHECKRV64ZDINX:       # %bb.0:
87; CHECKRV64ZDINX-NEXT:    flt.d a2, a1, a0
88; CHECKRV64ZDINX-NEXT:    bnez a2, .LBB2_2
89; CHECKRV64ZDINX-NEXT:  # %bb.1:
90; CHECKRV64ZDINX-NEXT:    mv a0, a1
91; CHECKRV64ZDINX-NEXT:  .LBB2_2:
92; CHECKRV64ZDINX-NEXT:    ret
93  %1 = fcmp ogt double %a, %b
94  %2 = select i1 %1, double %a, double %b
95  ret double %2
96}
97
98define double @select_fcmp_oge(double %a, double %b) nounwind {
99; CHECK-LABEL: select_fcmp_oge:
100; CHECK:       # %bb.0:
101; CHECK-NEXT:    fle.d a0, fa1, fa0
102; CHECK-NEXT:    bnez a0, .LBB3_2
103; CHECK-NEXT:  # %bb.1:
104; CHECK-NEXT:    fmv.d fa0, fa1
105; CHECK-NEXT:  .LBB3_2:
106; CHECK-NEXT:    ret
107;
108; CHECKRV32ZDINX-LABEL: select_fcmp_oge:
109; CHECKRV32ZDINX:       # %bb.0:
110; CHECKRV32ZDINX-NEXT:    fle.d a4, a2, a0
111; CHECKRV32ZDINX-NEXT:    bnez a4, .LBB3_2
112; CHECKRV32ZDINX-NEXT:  # %bb.1:
113; CHECKRV32ZDINX-NEXT:    mv a0, a2
114; CHECKRV32ZDINX-NEXT:    mv a1, a3
115; CHECKRV32ZDINX-NEXT:  .LBB3_2:
116; CHECKRV32ZDINX-NEXT:    ret
117;
118; CHECKRV64ZDINX-LABEL: select_fcmp_oge:
119; CHECKRV64ZDINX:       # %bb.0:
120; CHECKRV64ZDINX-NEXT:    fle.d a2, a1, a0
121; CHECKRV64ZDINX-NEXT:    bnez a2, .LBB3_2
122; CHECKRV64ZDINX-NEXT:  # %bb.1:
123; CHECKRV64ZDINX-NEXT:    mv a0, a1
124; CHECKRV64ZDINX-NEXT:  .LBB3_2:
125; CHECKRV64ZDINX-NEXT:    ret
126  %1 = fcmp oge double %a, %b
127  %2 = select i1 %1, double %a, double %b
128  ret double %2
129}
130
131define double @select_fcmp_olt(double %a, double %b) nounwind {
132; CHECK-LABEL: select_fcmp_olt:
133; CHECK:       # %bb.0:
134; CHECK-NEXT:    flt.d a0, fa0, fa1
135; CHECK-NEXT:    bnez a0, .LBB4_2
136; CHECK-NEXT:  # %bb.1:
137; CHECK-NEXT:    fmv.d fa0, fa1
138; CHECK-NEXT:  .LBB4_2:
139; CHECK-NEXT:    ret
140;
141; CHECKRV32ZDINX-LABEL: select_fcmp_olt:
142; CHECKRV32ZDINX:       # %bb.0:
143; CHECKRV32ZDINX-NEXT:    flt.d a4, a0, a2
144; CHECKRV32ZDINX-NEXT:    bnez a4, .LBB4_2
145; CHECKRV32ZDINX-NEXT:  # %bb.1:
146; CHECKRV32ZDINX-NEXT:    mv a0, a2
147; CHECKRV32ZDINX-NEXT:    mv a1, a3
148; CHECKRV32ZDINX-NEXT:  .LBB4_2:
149; CHECKRV32ZDINX-NEXT:    ret
150;
151; CHECKRV64ZDINX-LABEL: select_fcmp_olt:
152; CHECKRV64ZDINX:       # %bb.0:
153; CHECKRV64ZDINX-NEXT:    flt.d a2, a0, a1
154; CHECKRV64ZDINX-NEXT:    bnez a2, .LBB4_2
155; CHECKRV64ZDINX-NEXT:  # %bb.1:
156; CHECKRV64ZDINX-NEXT:    mv a0, a1
157; CHECKRV64ZDINX-NEXT:  .LBB4_2:
158; CHECKRV64ZDINX-NEXT:    ret
159  %1 = fcmp olt double %a, %b
160  %2 = select i1 %1, double %a, double %b
161  ret double %2
162}
163
164define double @select_fcmp_ole(double %a, double %b) nounwind {
165; CHECK-LABEL: select_fcmp_ole:
166; CHECK:       # %bb.0:
167; CHECK-NEXT:    fle.d a0, fa0, fa1
168; CHECK-NEXT:    bnez a0, .LBB5_2
169; CHECK-NEXT:  # %bb.1:
170; CHECK-NEXT:    fmv.d fa0, fa1
171; CHECK-NEXT:  .LBB5_2:
172; CHECK-NEXT:    ret
173;
174; CHECKRV32ZDINX-LABEL: select_fcmp_ole:
175; CHECKRV32ZDINX:       # %bb.0:
176; CHECKRV32ZDINX-NEXT:    fle.d a4, a0, a2
177; CHECKRV32ZDINX-NEXT:    bnez a4, .LBB5_2
178; CHECKRV32ZDINX-NEXT:  # %bb.1:
179; CHECKRV32ZDINX-NEXT:    mv a0, a2
180; CHECKRV32ZDINX-NEXT:    mv a1, a3
181; CHECKRV32ZDINX-NEXT:  .LBB5_2:
182; CHECKRV32ZDINX-NEXT:    ret
183;
184; CHECKRV64ZDINX-LABEL: select_fcmp_ole:
185; CHECKRV64ZDINX:       # %bb.0:
186; CHECKRV64ZDINX-NEXT:    fle.d a2, a0, a1
187; CHECKRV64ZDINX-NEXT:    bnez a2, .LBB5_2
188; CHECKRV64ZDINX-NEXT:  # %bb.1:
189; CHECKRV64ZDINX-NEXT:    mv a0, a1
190; CHECKRV64ZDINX-NEXT:  .LBB5_2:
191; CHECKRV64ZDINX-NEXT:    ret
192  %1 = fcmp ole double %a, %b
193  %2 = select i1 %1, double %a, double %b
194  ret double %2
195}
196
197define double @select_fcmp_one(double %a, double %b) nounwind {
198; CHECK-LABEL: select_fcmp_one:
199; CHECK:       # %bb.0:
200; CHECK-NEXT:    flt.d a0, fa0, fa1
201; CHECK-NEXT:    flt.d a1, fa1, fa0
202; CHECK-NEXT:    or a0, a1, a0
203; CHECK-NEXT:    bnez a0, .LBB6_2
204; CHECK-NEXT:  # %bb.1:
205; CHECK-NEXT:    fmv.d fa0, fa1
206; CHECK-NEXT:  .LBB6_2:
207; CHECK-NEXT:    ret
208;
209; CHECKRV32ZDINX-LABEL: select_fcmp_one:
210; CHECKRV32ZDINX:       # %bb.0:
211; CHECKRV32ZDINX-NEXT:    flt.d a4, a0, a2
212; CHECKRV32ZDINX-NEXT:    flt.d a5, a2, a0
213; CHECKRV32ZDINX-NEXT:    or a4, a5, a4
214; CHECKRV32ZDINX-NEXT:    bnez a4, .LBB6_2
215; CHECKRV32ZDINX-NEXT:  # %bb.1:
216; CHECKRV32ZDINX-NEXT:    mv a0, a2
217; CHECKRV32ZDINX-NEXT:    mv a1, a3
218; CHECKRV32ZDINX-NEXT:  .LBB6_2:
219; CHECKRV32ZDINX-NEXT:    ret
220;
221; CHECKRV64ZDINX-LABEL: select_fcmp_one:
222; CHECKRV64ZDINX:       # %bb.0:
223; CHECKRV64ZDINX-NEXT:    flt.d a2, a0, a1
224; CHECKRV64ZDINX-NEXT:    flt.d a3, a1, a0
225; CHECKRV64ZDINX-NEXT:    or a2, a3, a2
226; CHECKRV64ZDINX-NEXT:    bnez a2, .LBB6_2
227; CHECKRV64ZDINX-NEXT:  # %bb.1:
228; CHECKRV64ZDINX-NEXT:    mv a0, a1
229; CHECKRV64ZDINX-NEXT:  .LBB6_2:
230; CHECKRV64ZDINX-NEXT:    ret
231  %1 = fcmp one double %a, %b
232  %2 = select i1 %1, double %a, double %b
233  ret double %2
234}
235
236define double @select_fcmp_ord(double %a, double %b) nounwind {
237; CHECK-LABEL: select_fcmp_ord:
238; CHECK:       # %bb.0:
239; CHECK-NEXT:    feq.d a0, fa1, fa1
240; CHECK-NEXT:    feq.d a1, fa0, fa0
241; CHECK-NEXT:    and a0, a1, a0
242; CHECK-NEXT:    bnez a0, .LBB7_2
243; CHECK-NEXT:  # %bb.1:
244; CHECK-NEXT:    fmv.d fa0, fa1
245; CHECK-NEXT:  .LBB7_2:
246; CHECK-NEXT:    ret
247;
248; CHECKRV32ZDINX-LABEL: select_fcmp_ord:
249; CHECKRV32ZDINX:       # %bb.0:
250; CHECKRV32ZDINX-NEXT:    feq.d a4, a2, a2
251; CHECKRV32ZDINX-NEXT:    feq.d a5, a0, a0
252; CHECKRV32ZDINX-NEXT:    and a4, a5, a4
253; CHECKRV32ZDINX-NEXT:    bnez a4, .LBB7_2
254; CHECKRV32ZDINX-NEXT:  # %bb.1:
255; CHECKRV32ZDINX-NEXT:    mv a0, a2
256; CHECKRV32ZDINX-NEXT:    mv a1, a3
257; CHECKRV32ZDINX-NEXT:  .LBB7_2:
258; CHECKRV32ZDINX-NEXT:    ret
259;
260; CHECKRV64ZDINX-LABEL: select_fcmp_ord:
261; CHECKRV64ZDINX:       # %bb.0:
262; CHECKRV64ZDINX-NEXT:    feq.d a2, a1, a1
263; CHECKRV64ZDINX-NEXT:    feq.d a3, a0, a0
264; CHECKRV64ZDINX-NEXT:    and a2, a3, a2
265; CHECKRV64ZDINX-NEXT:    bnez a2, .LBB7_2
266; CHECKRV64ZDINX-NEXT:  # %bb.1:
267; CHECKRV64ZDINX-NEXT:    mv a0, a1
268; CHECKRV64ZDINX-NEXT:  .LBB7_2:
269; CHECKRV64ZDINX-NEXT:    ret
270  %1 = fcmp ord double %a, %b
271  %2 = select i1 %1, double %a, double %b
272  ret double %2
273}
274
275define double @select_fcmp_ueq(double %a, double %b) nounwind {
276; CHECK-LABEL: select_fcmp_ueq:
277; CHECK:       # %bb.0:
278; CHECK-NEXT:    flt.d a0, fa0, fa1
279; CHECK-NEXT:    flt.d a1, fa1, fa0
280; CHECK-NEXT:    or a0, a1, a0
281; CHECK-NEXT:    beqz a0, .LBB8_2
282; CHECK-NEXT:  # %bb.1:
283; CHECK-NEXT:    fmv.d fa0, fa1
284; CHECK-NEXT:  .LBB8_2:
285; CHECK-NEXT:    ret
286;
287; CHECKRV32ZDINX-LABEL: select_fcmp_ueq:
288; CHECKRV32ZDINX:       # %bb.0:
289; CHECKRV32ZDINX-NEXT:    flt.d a4, a0, a2
290; CHECKRV32ZDINX-NEXT:    flt.d a5, a2, a0
291; CHECKRV32ZDINX-NEXT:    or a4, a5, a4
292; CHECKRV32ZDINX-NEXT:    beqz a4, .LBB8_2
293; CHECKRV32ZDINX-NEXT:  # %bb.1:
294; CHECKRV32ZDINX-NEXT:    mv a0, a2
295; CHECKRV32ZDINX-NEXT:    mv a1, a3
296; CHECKRV32ZDINX-NEXT:  .LBB8_2:
297; CHECKRV32ZDINX-NEXT:    ret
298;
299; CHECKRV64ZDINX-LABEL: select_fcmp_ueq:
300; CHECKRV64ZDINX:       # %bb.0:
301; CHECKRV64ZDINX-NEXT:    flt.d a2, a0, a1
302; CHECKRV64ZDINX-NEXT:    flt.d a3, a1, a0
303; CHECKRV64ZDINX-NEXT:    or a2, a3, a2
304; CHECKRV64ZDINX-NEXT:    beqz a2, .LBB8_2
305; CHECKRV64ZDINX-NEXT:  # %bb.1:
306; CHECKRV64ZDINX-NEXT:    mv a0, a1
307; CHECKRV64ZDINX-NEXT:  .LBB8_2:
308; CHECKRV64ZDINX-NEXT:    ret
309  %1 = fcmp ueq double %a, %b
310  %2 = select i1 %1, double %a, double %b
311  ret double %2
312}
313
314define double @select_fcmp_ugt(double %a, double %b) nounwind {
315; CHECK-LABEL: select_fcmp_ugt:
316; CHECK:       # %bb.0:
317; CHECK-NEXT:    fle.d a0, fa0, fa1
318; CHECK-NEXT:    beqz a0, .LBB9_2
319; CHECK-NEXT:  # %bb.1:
320; CHECK-NEXT:    fmv.d fa0, fa1
321; CHECK-NEXT:  .LBB9_2:
322; CHECK-NEXT:    ret
323;
324; CHECKRV32ZDINX-LABEL: select_fcmp_ugt:
325; CHECKRV32ZDINX:       # %bb.0:
326; CHECKRV32ZDINX-NEXT:    fle.d a4, a0, a2
327; CHECKRV32ZDINX-NEXT:    beqz a4, .LBB9_2
328; CHECKRV32ZDINX-NEXT:  # %bb.1:
329; CHECKRV32ZDINX-NEXT:    mv a0, a2
330; CHECKRV32ZDINX-NEXT:    mv a1, a3
331; CHECKRV32ZDINX-NEXT:  .LBB9_2:
332; CHECKRV32ZDINX-NEXT:    ret
333;
334; CHECKRV64ZDINX-LABEL: select_fcmp_ugt:
335; CHECKRV64ZDINX:       # %bb.0:
336; CHECKRV64ZDINX-NEXT:    fle.d a2, a0, a1
337; CHECKRV64ZDINX-NEXT:    beqz a2, .LBB9_2
338; CHECKRV64ZDINX-NEXT:  # %bb.1:
339; CHECKRV64ZDINX-NEXT:    mv a0, a1
340; CHECKRV64ZDINX-NEXT:  .LBB9_2:
341; CHECKRV64ZDINX-NEXT:    ret
342  %1 = fcmp ugt double %a, %b
343  %2 = select i1 %1, double %a, double %b
344  ret double %2
345}
346
347define double @select_fcmp_uge(double %a, double %b) nounwind {
348; CHECK-LABEL: select_fcmp_uge:
349; CHECK:       # %bb.0:
350; CHECK-NEXT:    flt.d a0, fa0, fa1
351; CHECK-NEXT:    beqz a0, .LBB10_2
352; CHECK-NEXT:  # %bb.1:
353; CHECK-NEXT:    fmv.d fa0, fa1
354; CHECK-NEXT:  .LBB10_2:
355; CHECK-NEXT:    ret
356;
357; CHECKRV32ZDINX-LABEL: select_fcmp_uge:
358; CHECKRV32ZDINX:       # %bb.0:
359; CHECKRV32ZDINX-NEXT:    flt.d a4, a0, a2
360; CHECKRV32ZDINX-NEXT:    beqz a4, .LBB10_2
361; CHECKRV32ZDINX-NEXT:  # %bb.1:
362; CHECKRV32ZDINX-NEXT:    mv a0, a2
363; CHECKRV32ZDINX-NEXT:    mv a1, a3
364; CHECKRV32ZDINX-NEXT:  .LBB10_2:
365; CHECKRV32ZDINX-NEXT:    ret
366;
367; CHECKRV64ZDINX-LABEL: select_fcmp_uge:
368; CHECKRV64ZDINX:       # %bb.0:
369; CHECKRV64ZDINX-NEXT:    flt.d a2, a0, a1
370; CHECKRV64ZDINX-NEXT:    beqz a2, .LBB10_2
371; CHECKRV64ZDINX-NEXT:  # %bb.1:
372; CHECKRV64ZDINX-NEXT:    mv a0, a1
373; CHECKRV64ZDINX-NEXT:  .LBB10_2:
374; CHECKRV64ZDINX-NEXT:    ret
375  %1 = fcmp uge double %a, %b
376  %2 = select i1 %1, double %a, double %b
377  ret double %2
378}
379
380define double @select_fcmp_ult(double %a, double %b) nounwind {
381; CHECK-LABEL: select_fcmp_ult:
382; CHECK:       # %bb.0:
383; CHECK-NEXT:    fle.d a0, fa1, fa0
384; CHECK-NEXT:    beqz a0, .LBB11_2
385; CHECK-NEXT:  # %bb.1:
386; CHECK-NEXT:    fmv.d fa0, fa1
387; CHECK-NEXT:  .LBB11_2:
388; CHECK-NEXT:    ret
389;
390; CHECKRV32ZDINX-LABEL: select_fcmp_ult:
391; CHECKRV32ZDINX:       # %bb.0:
392; CHECKRV32ZDINX-NEXT:    fle.d a4, a2, a0
393; CHECKRV32ZDINX-NEXT:    beqz a4, .LBB11_2
394; CHECKRV32ZDINX-NEXT:  # %bb.1:
395; CHECKRV32ZDINX-NEXT:    mv a0, a2
396; CHECKRV32ZDINX-NEXT:    mv a1, a3
397; CHECKRV32ZDINX-NEXT:  .LBB11_2:
398; CHECKRV32ZDINX-NEXT:    ret
399;
400; CHECKRV64ZDINX-LABEL: select_fcmp_ult:
401; CHECKRV64ZDINX:       # %bb.0:
402; CHECKRV64ZDINX-NEXT:    fle.d a2, a1, a0
403; CHECKRV64ZDINX-NEXT:    beqz a2, .LBB11_2
404; CHECKRV64ZDINX-NEXT:  # %bb.1:
405; CHECKRV64ZDINX-NEXT:    mv a0, a1
406; CHECKRV64ZDINX-NEXT:  .LBB11_2:
407; CHECKRV64ZDINX-NEXT:    ret
408  %1 = fcmp ult double %a, %b
409  %2 = select i1 %1, double %a, double %b
410  ret double %2
411}
412
413define double @select_fcmp_ule(double %a, double %b) nounwind {
414; CHECK-LABEL: select_fcmp_ule:
415; CHECK:       # %bb.0:
416; CHECK-NEXT:    flt.d a0, fa1, fa0
417; CHECK-NEXT:    beqz a0, .LBB12_2
418; CHECK-NEXT:  # %bb.1:
419; CHECK-NEXT:    fmv.d fa0, fa1
420; CHECK-NEXT:  .LBB12_2:
421; CHECK-NEXT:    ret
422;
423; CHECKRV32ZDINX-LABEL: select_fcmp_ule:
424; CHECKRV32ZDINX:       # %bb.0:
425; CHECKRV32ZDINX-NEXT:    flt.d a4, a2, a0
426; CHECKRV32ZDINX-NEXT:    beqz a4, .LBB12_2
427; CHECKRV32ZDINX-NEXT:  # %bb.1:
428; CHECKRV32ZDINX-NEXT:    mv a0, a2
429; CHECKRV32ZDINX-NEXT:    mv a1, a3
430; CHECKRV32ZDINX-NEXT:  .LBB12_2:
431; CHECKRV32ZDINX-NEXT:    ret
432;
433; CHECKRV64ZDINX-LABEL: select_fcmp_ule:
434; CHECKRV64ZDINX:       # %bb.0:
435; CHECKRV64ZDINX-NEXT:    flt.d a2, a1, a0
436; CHECKRV64ZDINX-NEXT:    beqz a2, .LBB12_2
437; CHECKRV64ZDINX-NEXT:  # %bb.1:
438; CHECKRV64ZDINX-NEXT:    mv a0, a1
439; CHECKRV64ZDINX-NEXT:  .LBB12_2:
440; CHECKRV64ZDINX-NEXT:    ret
441  %1 = fcmp ule double %a, %b
442  %2 = select i1 %1, double %a, double %b
443  ret double %2
444}
445
446define double @select_fcmp_une(double %a, double %b) nounwind {
447; CHECK-LABEL: select_fcmp_une:
448; CHECK:       # %bb.0:
449; CHECK-NEXT:    feq.d a0, fa0, fa1
450; CHECK-NEXT:    beqz a0, .LBB13_2
451; CHECK-NEXT:  # %bb.1:
452; CHECK-NEXT:    fmv.d fa0, fa1
453; CHECK-NEXT:  .LBB13_2:
454; CHECK-NEXT:    ret
455;
456; CHECKRV32ZDINX-LABEL: select_fcmp_une:
457; CHECKRV32ZDINX:       # %bb.0:
458; CHECKRV32ZDINX-NEXT:    feq.d a4, a0, a2
459; CHECKRV32ZDINX-NEXT:    beqz a4, .LBB13_2
460; CHECKRV32ZDINX-NEXT:  # %bb.1:
461; CHECKRV32ZDINX-NEXT:    mv a0, a2
462; CHECKRV32ZDINX-NEXT:    mv a1, a3
463; CHECKRV32ZDINX-NEXT:  .LBB13_2:
464; CHECKRV32ZDINX-NEXT:    ret
465;
466; CHECKRV64ZDINX-LABEL: select_fcmp_une:
467; CHECKRV64ZDINX:       # %bb.0:
468; CHECKRV64ZDINX-NEXT:    feq.d a2, a0, a1
469; CHECKRV64ZDINX-NEXT:    beqz a2, .LBB13_2
470; CHECKRV64ZDINX-NEXT:  # %bb.1:
471; CHECKRV64ZDINX-NEXT:    mv a0, a1
472; CHECKRV64ZDINX-NEXT:  .LBB13_2:
473; CHECKRV64ZDINX-NEXT:    ret
474  %1 = fcmp une double %a, %b
475  %2 = select i1 %1, double %a, double %b
476  ret double %2
477}
478
479define double @select_fcmp_uno(double %a, double %b) nounwind {
480; CHECK-LABEL: select_fcmp_uno:
481; CHECK:       # %bb.0:
482; CHECK-NEXT:    feq.d a0, fa1, fa1
483; CHECK-NEXT:    feq.d a1, fa0, fa0
484; CHECK-NEXT:    and a0, a1, a0
485; CHECK-NEXT:    beqz a0, .LBB14_2
486; CHECK-NEXT:  # %bb.1:
487; CHECK-NEXT:    fmv.d fa0, fa1
488; CHECK-NEXT:  .LBB14_2:
489; CHECK-NEXT:    ret
490;
491; CHECKRV32ZDINX-LABEL: select_fcmp_uno:
492; CHECKRV32ZDINX:       # %bb.0:
493; CHECKRV32ZDINX-NEXT:    feq.d a4, a2, a2
494; CHECKRV32ZDINX-NEXT:    feq.d a5, a0, a0
495; CHECKRV32ZDINX-NEXT:    and a4, a5, a4
496; CHECKRV32ZDINX-NEXT:    beqz a4, .LBB14_2
497; CHECKRV32ZDINX-NEXT:  # %bb.1:
498; CHECKRV32ZDINX-NEXT:    mv a0, a2
499; CHECKRV32ZDINX-NEXT:    mv a1, a3
500; CHECKRV32ZDINX-NEXT:  .LBB14_2:
501; CHECKRV32ZDINX-NEXT:    ret
502;
503; CHECKRV64ZDINX-LABEL: select_fcmp_uno:
504; CHECKRV64ZDINX:       # %bb.0:
505; CHECKRV64ZDINX-NEXT:    feq.d a2, a1, a1
506; CHECKRV64ZDINX-NEXT:    feq.d a3, a0, a0
507; CHECKRV64ZDINX-NEXT:    and a2, a3, a2
508; CHECKRV64ZDINX-NEXT:    beqz a2, .LBB14_2
509; CHECKRV64ZDINX-NEXT:  # %bb.1:
510; CHECKRV64ZDINX-NEXT:    mv a0, a1
511; CHECKRV64ZDINX-NEXT:  .LBB14_2:
512; CHECKRV64ZDINX-NEXT:    ret
513  %1 = fcmp uno double %a, %b
514  %2 = select i1 %1, double %a, double %b
515  ret double %2
516}
517
518define double @select_fcmp_true(double %a, double %b) nounwind {
519; CHECK-LABEL: select_fcmp_true:
520; CHECK:       # %bb.0:
521; CHECK-NEXT:    ret
522;
523; CHECKRV32ZDINX-LABEL: select_fcmp_true:
524; CHECKRV32ZDINX:       # %bb.0:
525; CHECKRV32ZDINX-NEXT:    ret
526;
527; CHECKRV64ZDINX-LABEL: select_fcmp_true:
528; CHECKRV64ZDINX:       # %bb.0:
529; CHECKRV64ZDINX-NEXT:    ret
530  %1 = fcmp true double %a, %b
531  %2 = select i1 %1, double %a, double %b
532  ret double %2
533}
534
535; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
536define i32 @i32_select_fcmp_oeq(double %a, double %b, i32 %c, i32 %d) nounwind {
537; CHECK-LABEL: i32_select_fcmp_oeq:
538; CHECK:       # %bb.0:
539; CHECK-NEXT:    feq.d a2, fa0, fa1
540; CHECK-NEXT:    bnez a2, .LBB16_2
541; CHECK-NEXT:  # %bb.1:
542; CHECK-NEXT:    mv a0, a1
543; CHECK-NEXT:  .LBB16_2:
544; CHECK-NEXT:    ret
545;
546; CHECKRV32ZDINX-LABEL: i32_select_fcmp_oeq:
547; CHECKRV32ZDINX:       # %bb.0:
548; CHECKRV32ZDINX-NEXT:    feq.d a1, a0, a2
549; CHECKRV32ZDINX-NEXT:    mv a0, a4
550; CHECKRV32ZDINX-NEXT:    bnez a1, .LBB16_2
551; CHECKRV32ZDINX-NEXT:  # %bb.1:
552; CHECKRV32ZDINX-NEXT:    mv a0, a5
553; CHECKRV32ZDINX-NEXT:  .LBB16_2:
554; CHECKRV32ZDINX-NEXT:    ret
555;
556; CHECKRV64ZDINX-LABEL: i32_select_fcmp_oeq:
557; CHECKRV64ZDINX:       # %bb.0:
558; CHECKRV64ZDINX-NEXT:    feq.d a1, a0, a1
559; CHECKRV64ZDINX-NEXT:    mv a0, a2
560; CHECKRV64ZDINX-NEXT:    bnez a1, .LBB16_2
561; CHECKRV64ZDINX-NEXT:  # %bb.1:
562; CHECKRV64ZDINX-NEXT:    mv a0, a3
563; CHECKRV64ZDINX-NEXT:  .LBB16_2:
564; CHECKRV64ZDINX-NEXT:    ret
565  %1 = fcmp oeq double %a, %b
566  %2 = select i1 %1, i32 %c, i32 %d
567  ret i32 %2
568}
569
570define i32 @select_fcmp_oeq_1_2(double %a, double %b) {
571; CHECK-LABEL: select_fcmp_oeq_1_2:
572; CHECK:       # %bb.0:
573; CHECK-NEXT:    feq.d a0, fa0, fa1
574; CHECK-NEXT:    li a1, 2
575; CHECK-NEXT:    sub a0, a1, a0
576; CHECK-NEXT:    ret
577;
578; CHECKRV32ZDINX-LABEL: select_fcmp_oeq_1_2:
579; CHECKRV32ZDINX:       # %bb.0:
580; CHECKRV32ZDINX-NEXT:    li a4, 2
581; CHECKRV32ZDINX-NEXT:    feq.d a0, a0, a2
582; CHECKRV32ZDINX-NEXT:    sub a0, a4, a0
583; CHECKRV32ZDINX-NEXT:    ret
584;
585; CHECKRV64ZDINX-LABEL: select_fcmp_oeq_1_2:
586; CHECKRV64ZDINX:       # %bb.0:
587; CHECKRV64ZDINX-NEXT:    feq.d a0, a0, a1
588; CHECKRV64ZDINX-NEXT:    li a1, 2
589; CHECKRV64ZDINX-NEXT:    sub a0, a1, a0
590; CHECKRV64ZDINX-NEXT:    ret
591  %1 = fcmp fast oeq double %a, %b
592  %2 = select i1 %1, i32 1, i32 2
593  ret i32 %2
594}
595
596define signext i32 @select_fcmp_uge_negone_zero(double %a, double %b) nounwind {
597; CHECK-LABEL: select_fcmp_uge_negone_zero:
598; CHECK:       # %bb.0:
599; CHECK-NEXT:    fle.d a0, fa0, fa1
600; CHECK-NEXT:    addi a0, a0, -1
601; CHECK-NEXT:    ret
602;
603; CHECKRV32ZDINX-LABEL: select_fcmp_uge_negone_zero:
604; CHECKRV32ZDINX:       # %bb.0:
605; CHECKRV32ZDINX-NEXT:    fle.d a0, a0, a2
606; CHECKRV32ZDINX-NEXT:    addi a0, a0, -1
607; CHECKRV32ZDINX-NEXT:    ret
608;
609; CHECKRV64ZDINX-LABEL: select_fcmp_uge_negone_zero:
610; CHECKRV64ZDINX:       # %bb.0:
611; CHECKRV64ZDINX-NEXT:    fle.d a0, a0, a1
612; CHECKRV64ZDINX-NEXT:    addi a0, a0, -1
613; CHECKRV64ZDINX-NEXT:    ret
614  %1 = fcmp ugt double %a, %b
615  %2 = select i1 %1, i32 -1, i32 0
616  ret i32 %2
617}
618
619define signext i32 @select_fcmp_uge_1_2(double %a, double %b) nounwind {
620; CHECK-LABEL: select_fcmp_uge_1_2:
621; CHECK:       # %bb.0:
622; CHECK-NEXT:    fle.d a0, fa0, fa1
623; CHECK-NEXT:    addi a0, a0, 1
624; CHECK-NEXT:    ret
625;
626; CHECKRV32ZDINX-LABEL: select_fcmp_uge_1_2:
627; CHECKRV32ZDINX:       # %bb.0:
628; CHECKRV32ZDINX-NEXT:    fle.d a0, a0, a2
629; CHECKRV32ZDINX-NEXT:    addi a0, a0, 1
630; CHECKRV32ZDINX-NEXT:    ret
631;
632; CHECKRV64ZDINX-LABEL: select_fcmp_uge_1_2:
633; CHECKRV64ZDINX:       # %bb.0:
634; CHECKRV64ZDINX-NEXT:    fle.d a0, a0, a1
635; CHECKRV64ZDINX-NEXT:    addi a0, a0, 1
636; CHECKRV64ZDINX-NEXT:    ret
637  %1 = fcmp ugt double %a, %b
638  %2 = select i1 %1, i32 1, i32 2
639  ret i32 %2
640}
641