1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 2; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs < %s | FileCheck %s -check-prefix=RV32I 3; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs < %s | FileCheck %s -check-prefix=RV64I 4; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs,+xventanacondops < %s | FileCheck %s -check-prefix=RV32XVENTANACONDOPS 5; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS 6; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV 7; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs,+zicond < %s | FileCheck %s -check-prefix=RV32ZICOND 8; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+zicond < %s | FileCheck %s -check-prefix=RV64ZICOND 9 10define i64 @zero1(i64 %rs1, i1 zeroext %rc) { 11; RV32I-LABEL: zero1: 12; RV32I: # %bb.0: 13; RV32I-NEXT: neg a2, a2 14; RV32I-NEXT: and a0, a2, a0 15; RV32I-NEXT: and a1, a2, a1 16; RV32I-NEXT: ret 17; 18; RV64I-LABEL: zero1: 19; RV64I: # %bb.0: 20; RV64I-NEXT: neg a1, a1 21; RV64I-NEXT: and a0, a1, a0 22; RV64I-NEXT: ret 23; 24; RV32XVENTANACONDOPS-LABEL: zero1: 25; RV32XVENTANACONDOPS: # %bb.0: 26; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a2 27; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2 28; RV32XVENTANACONDOPS-NEXT: ret 29; 30; RV64XVENTANACONDOPS-LABEL: zero1: 31; RV64XVENTANACONDOPS: # %bb.0: 32; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a1 33; RV64XVENTANACONDOPS-NEXT: ret 34; 35; RV64XTHEADCONDMOV-LABEL: zero1: 36; RV64XTHEADCONDMOV: # %bb.0: 37; RV64XTHEADCONDMOV-NEXT: th.mveqz a0, zero, a1 38; RV64XTHEADCONDMOV-NEXT: ret 39; 40; RV32ZICOND-LABEL: zero1: 41; RV32ZICOND: # %bb.0: 42; RV32ZICOND-NEXT: czero.eqz a0, a0, a2 43; RV32ZICOND-NEXT: czero.eqz a1, a1, a2 44; RV32ZICOND-NEXT: ret 45; 46; RV64ZICOND-LABEL: zero1: 47; RV64ZICOND: # %bb.0: 48; RV64ZICOND-NEXT: czero.eqz a0, a0, a1 49; RV64ZICOND-NEXT: ret 50 %sel = select i1 %rc, i64 %rs1, i64 0 51 ret i64 %sel 52} 53 54define i64 @zero2(i64 %rs1, i1 zeroext %rc) { 55; RV32I-LABEL: zero2: 56; RV32I: # %bb.0: 57; RV32I-NEXT: addi a2, a2, -1 58; RV32I-NEXT: and a0, a2, a0 59; RV32I-NEXT: and a1, a2, a1 60; RV32I-NEXT: ret 61; 62; RV64I-LABEL: zero2: 63; RV64I: # %bb.0: 64; RV64I-NEXT: addi a1, a1, -1 65; RV64I-NEXT: and a0, a1, a0 66; RV64I-NEXT: ret 67; 68; RV32XVENTANACONDOPS-LABEL: zero2: 69; RV32XVENTANACONDOPS: # %bb.0: 70; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2 71; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a2 72; RV32XVENTANACONDOPS-NEXT: ret 73; 74; RV64XVENTANACONDOPS-LABEL: zero2: 75; RV64XVENTANACONDOPS: # %bb.0: 76; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a1 77; RV64XVENTANACONDOPS-NEXT: ret 78; 79; RV64XTHEADCONDMOV-LABEL: zero2: 80; RV64XTHEADCONDMOV: # %bb.0: 81; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, zero, a1 82; RV64XTHEADCONDMOV-NEXT: ret 83; 84; RV32ZICOND-LABEL: zero2: 85; RV32ZICOND: # %bb.0: 86; RV32ZICOND-NEXT: czero.nez a0, a0, a2 87; RV32ZICOND-NEXT: czero.nez a1, a1, a2 88; RV32ZICOND-NEXT: ret 89; 90; RV64ZICOND-LABEL: zero2: 91; RV64ZICOND: # %bb.0: 92; RV64ZICOND-NEXT: czero.nez a0, a0, a1 93; RV64ZICOND-NEXT: ret 94 %sel = select i1 %rc, i64 0, i64 %rs1 95 ret i64 %sel 96} 97 98define i64 @zero_singlebit1(i64 %rs1, i64 %rs2) { 99; RV32I-LABEL: zero_singlebit1: 100; RV32I: # %bb.0: 101; RV32I-NEXT: bexti a2, a2, 12 102; RV32I-NEXT: addi a2, a2, -1 103; RV32I-NEXT: and a0, a2, a0 104; RV32I-NEXT: and a1, a2, a1 105; RV32I-NEXT: ret 106; 107; RV64I-LABEL: zero_singlebit1: 108; RV64I: # %bb.0: 109; RV64I-NEXT: bexti a1, a1, 12 110; RV64I-NEXT: addi a1, a1, -1 111; RV64I-NEXT: and a0, a1, a0 112; RV64I-NEXT: ret 113; 114; RV32XVENTANACONDOPS-LABEL: zero_singlebit1: 115; RV32XVENTANACONDOPS: # %bb.0: 116; RV32XVENTANACONDOPS-NEXT: bexti a2, a2, 12 117; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2 118; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a2 119; RV32XVENTANACONDOPS-NEXT: ret 120; 121; RV64XVENTANACONDOPS-LABEL: zero_singlebit1: 122; RV64XVENTANACONDOPS: # %bb.0: 123; RV64XVENTANACONDOPS-NEXT: bexti a1, a1, 12 124; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a1 125; RV64XVENTANACONDOPS-NEXT: ret 126; 127; RV64XTHEADCONDMOV-LABEL: zero_singlebit1: 128; RV64XTHEADCONDMOV: # %bb.0: 129; RV64XTHEADCONDMOV-NEXT: lui a2, 1 130; RV64XTHEADCONDMOV-NEXT: and a1, a1, a2 131; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, zero, a1 132; RV64XTHEADCONDMOV-NEXT: ret 133; 134; RV32ZICOND-LABEL: zero_singlebit1: 135; RV32ZICOND: # %bb.0: 136; RV32ZICOND-NEXT: bexti a2, a2, 12 137; RV32ZICOND-NEXT: czero.nez a0, a0, a2 138; RV32ZICOND-NEXT: czero.nez a1, a1, a2 139; RV32ZICOND-NEXT: ret 140; 141; RV64ZICOND-LABEL: zero_singlebit1: 142; RV64ZICOND: # %bb.0: 143; RV64ZICOND-NEXT: bexti a1, a1, 12 144; RV64ZICOND-NEXT: czero.nez a0, a0, a1 145; RV64ZICOND-NEXT: ret 146 %and = and i64 %rs2, 4096 147 %rc = icmp eq i64 %and, 0 148 %sel = select i1 %rc, i64 %rs1, i64 0 149 ret i64 %sel 150} 151 152define i64 @zero_singlebit2(i64 %rs1, i64 %rs2) { 153; RV32I-LABEL: zero_singlebit2: 154; RV32I: # %bb.0: 155; RV32I-NEXT: slli a2, a2, 19 156; RV32I-NEXT: srai a2, a2, 31 157; RV32I-NEXT: and a0, a2, a0 158; RV32I-NEXT: and a1, a2, a1 159; RV32I-NEXT: ret 160; 161; RV64I-LABEL: zero_singlebit2: 162; RV64I: # %bb.0: 163; RV64I-NEXT: slli a1, a1, 51 164; RV64I-NEXT: srai a1, a1, 63 165; RV64I-NEXT: and a0, a1, a0 166; RV64I-NEXT: ret 167; 168; RV32XVENTANACONDOPS-LABEL: zero_singlebit2: 169; RV32XVENTANACONDOPS: # %bb.0: 170; RV32XVENTANACONDOPS-NEXT: bexti a2, a2, 12 171; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a2 172; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2 173; RV32XVENTANACONDOPS-NEXT: ret 174; 175; RV64XVENTANACONDOPS-LABEL: zero_singlebit2: 176; RV64XVENTANACONDOPS: # %bb.0: 177; RV64XVENTANACONDOPS-NEXT: bexti a1, a1, 12 178; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a1 179; RV64XVENTANACONDOPS-NEXT: ret 180; 181; RV64XTHEADCONDMOV-LABEL: zero_singlebit2: 182; RV64XTHEADCONDMOV: # %bb.0: 183; RV64XTHEADCONDMOV-NEXT: slli a1, a1, 51 184; RV64XTHEADCONDMOV-NEXT: srai a1, a1, 63 185; RV64XTHEADCONDMOV-NEXT: and a0, a1, a0 186; RV64XTHEADCONDMOV-NEXT: ret 187; 188; RV32ZICOND-LABEL: zero_singlebit2: 189; RV32ZICOND: # %bb.0: 190; RV32ZICOND-NEXT: bexti a2, a2, 12 191; RV32ZICOND-NEXT: czero.eqz a0, a0, a2 192; RV32ZICOND-NEXT: czero.eqz a1, a1, a2 193; RV32ZICOND-NEXT: ret 194; 195; RV64ZICOND-LABEL: zero_singlebit2: 196; RV64ZICOND: # %bb.0: 197; RV64ZICOND-NEXT: bexti a1, a1, 12 198; RV64ZICOND-NEXT: czero.eqz a0, a0, a1 199; RV64ZICOND-NEXT: ret 200 %and = and i64 %rs2, 4096 201 %rc = icmp eq i64 %and, 0 202 %sel = select i1 %rc, i64 0, i64 %rs1 203 ret i64 %sel 204} 205 206define i64 @add1(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 207; RV32I-LABEL: add1: 208; RV32I: # %bb.0: 209; RV32I-NEXT: neg a0, a0 210; RV32I-NEXT: and a4, a0, a4 211; RV32I-NEXT: and a0, a0, a3 212; RV32I-NEXT: add a2, a2, a4 213; RV32I-NEXT: add a0, a1, a0 214; RV32I-NEXT: sltu a1, a0, a1 215; RV32I-NEXT: add a1, a2, a1 216; RV32I-NEXT: ret 217; 218; RV64I-LABEL: add1: 219; RV64I: # %bb.0: 220; RV64I-NEXT: neg a0, a0 221; RV64I-NEXT: and a0, a0, a2 222; RV64I-NEXT: add a0, a1, a0 223; RV64I-NEXT: ret 224; 225; RV32XVENTANACONDOPS-LABEL: add1: 226; RV32XVENTANACONDOPS: # %bb.0: 227; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a4, a0 228; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a3, a0 229; RV32XVENTANACONDOPS-NEXT: add a2, a2, a4 230; RV32XVENTANACONDOPS-NEXT: add a0, a1, a0 231; RV32XVENTANACONDOPS-NEXT: sltu a1, a0, a1 232; RV32XVENTANACONDOPS-NEXT: add a1, a2, a1 233; RV32XVENTANACONDOPS-NEXT: ret 234; 235; RV64XVENTANACONDOPS-LABEL: add1: 236; RV64XVENTANACONDOPS: # %bb.0: 237; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0 238; RV64XVENTANACONDOPS-NEXT: add a0, a1, a0 239; RV64XVENTANACONDOPS-NEXT: ret 240; 241; RV64XTHEADCONDMOV-LABEL: add1: 242; RV64XTHEADCONDMOV: # %bb.0: 243; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, zero, a0 244; RV64XTHEADCONDMOV-NEXT: add a0, a1, a2 245; RV64XTHEADCONDMOV-NEXT: ret 246; 247; RV32ZICOND-LABEL: add1: 248; RV32ZICOND: # %bb.0: 249; RV32ZICOND-NEXT: czero.eqz a4, a4, a0 250; RV32ZICOND-NEXT: czero.eqz a0, a3, a0 251; RV32ZICOND-NEXT: add a2, a2, a4 252; RV32ZICOND-NEXT: add a0, a1, a0 253; RV32ZICOND-NEXT: sltu a1, a0, a1 254; RV32ZICOND-NEXT: add a1, a2, a1 255; RV32ZICOND-NEXT: ret 256; 257; RV64ZICOND-LABEL: add1: 258; RV64ZICOND: # %bb.0: 259; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 260; RV64ZICOND-NEXT: add a0, a1, a0 261; RV64ZICOND-NEXT: ret 262 %add = add i64 %rs1, %rs2 263 %sel = select i1 %rc, i64 %add, i64 %rs1 264 ret i64 %sel 265} 266 267define i64 @add2(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 268; RV32I-LABEL: add2: 269; RV32I: # %bb.0: 270; RV32I-NEXT: neg a0, a0 271; RV32I-NEXT: and a2, a0, a2 272; RV32I-NEXT: and a0, a0, a1 273; RV32I-NEXT: add a1, a4, a2 274; RV32I-NEXT: add a0, a3, a0 275; RV32I-NEXT: sltu a2, a0, a3 276; RV32I-NEXT: add a1, a1, a2 277; RV32I-NEXT: ret 278; 279; RV64I-LABEL: add2: 280; RV64I: # %bb.0: 281; RV64I-NEXT: neg a0, a0 282; RV64I-NEXT: and a0, a0, a1 283; RV64I-NEXT: add a0, a2, a0 284; RV64I-NEXT: ret 285; 286; RV32XVENTANACONDOPS-LABEL: add2: 287; RV32XVENTANACONDOPS: # %bb.0: 288; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 289; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 290; RV32XVENTANACONDOPS-NEXT: add a1, a4, a2 291; RV32XVENTANACONDOPS-NEXT: add a0, a3, a0 292; RV32XVENTANACONDOPS-NEXT: sltu a2, a0, a3 293; RV32XVENTANACONDOPS-NEXT: add a1, a1, a2 294; RV32XVENTANACONDOPS-NEXT: ret 295; 296; RV64XVENTANACONDOPS-LABEL: add2: 297; RV64XVENTANACONDOPS: # %bb.0: 298; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 299; RV64XVENTANACONDOPS-NEXT: add a0, a2, a0 300; RV64XVENTANACONDOPS-NEXT: ret 301; 302; RV64XTHEADCONDMOV-LABEL: add2: 303; RV64XTHEADCONDMOV: # %bb.0: 304; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a0 305; RV64XTHEADCONDMOV-NEXT: add a0, a2, a1 306; RV64XTHEADCONDMOV-NEXT: ret 307; 308; RV32ZICOND-LABEL: add2: 309; RV32ZICOND: # %bb.0: 310; RV32ZICOND-NEXT: czero.eqz a2, a2, a0 311; RV32ZICOND-NEXT: czero.eqz a0, a1, a0 312; RV32ZICOND-NEXT: add a1, a4, a2 313; RV32ZICOND-NEXT: add a0, a3, a0 314; RV32ZICOND-NEXT: sltu a2, a0, a3 315; RV32ZICOND-NEXT: add a1, a1, a2 316; RV32ZICOND-NEXT: ret 317; 318; RV64ZICOND-LABEL: add2: 319; RV64ZICOND: # %bb.0: 320; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 321; RV64ZICOND-NEXT: add a0, a2, a0 322; RV64ZICOND-NEXT: ret 323 %add = add i64 %rs1, %rs2 324 %sel = select i1 %rc, i64 %add, i64 %rs2 325 ret i64 %sel 326} 327 328define i64 @add3(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 329; RV32I-LABEL: add3: 330; RV32I: # %bb.0: 331; RV32I-NEXT: addi a0, a0, -1 332; RV32I-NEXT: and a4, a0, a4 333; RV32I-NEXT: and a0, a0, a3 334; RV32I-NEXT: add a2, a2, a4 335; RV32I-NEXT: add a0, a1, a0 336; RV32I-NEXT: sltu a1, a0, a1 337; RV32I-NEXT: add a1, a2, a1 338; RV32I-NEXT: ret 339; 340; RV64I-LABEL: add3: 341; RV64I: # %bb.0: 342; RV64I-NEXT: addi a0, a0, -1 343; RV64I-NEXT: and a0, a0, a2 344; RV64I-NEXT: add a0, a1, a0 345; RV64I-NEXT: ret 346; 347; RV32XVENTANACONDOPS-LABEL: add3: 348; RV32XVENTANACONDOPS: # %bb.0: 349; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a4, a0 350; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a3, a0 351; RV32XVENTANACONDOPS-NEXT: add a2, a2, a4 352; RV32XVENTANACONDOPS-NEXT: add a0, a1, a0 353; RV32XVENTANACONDOPS-NEXT: sltu a1, a0, a1 354; RV32XVENTANACONDOPS-NEXT: add a1, a2, a1 355; RV32XVENTANACONDOPS-NEXT: ret 356; 357; RV64XVENTANACONDOPS-LABEL: add3: 358; RV64XVENTANACONDOPS: # %bb.0: 359; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 360; RV64XVENTANACONDOPS-NEXT: add a0, a1, a0 361; RV64XVENTANACONDOPS-NEXT: ret 362; 363; RV64XTHEADCONDMOV-LABEL: add3: 364; RV64XTHEADCONDMOV: # %bb.0: 365; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, zero, a0 366; RV64XTHEADCONDMOV-NEXT: add a0, a1, a2 367; RV64XTHEADCONDMOV-NEXT: ret 368; 369; RV32ZICOND-LABEL: add3: 370; RV32ZICOND: # %bb.0: 371; RV32ZICOND-NEXT: czero.nez a4, a4, a0 372; RV32ZICOND-NEXT: czero.nez a0, a3, a0 373; RV32ZICOND-NEXT: add a2, a2, a4 374; RV32ZICOND-NEXT: add a0, a1, a0 375; RV32ZICOND-NEXT: sltu a1, a0, a1 376; RV32ZICOND-NEXT: add a1, a2, a1 377; RV32ZICOND-NEXT: ret 378; 379; RV64ZICOND-LABEL: add3: 380; RV64ZICOND: # %bb.0: 381; RV64ZICOND-NEXT: czero.nez a0, a2, a0 382; RV64ZICOND-NEXT: add a0, a1, a0 383; RV64ZICOND-NEXT: ret 384 %add = add i64 %rs1, %rs2 385 %sel = select i1 %rc, i64 %rs1, i64 %add 386 ret i64 %sel 387} 388 389define i64 @add4(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 390; RV32I-LABEL: add4: 391; RV32I: # %bb.0: 392; RV32I-NEXT: addi a0, a0, -1 393; RV32I-NEXT: and a2, a0, a2 394; RV32I-NEXT: and a0, a0, a1 395; RV32I-NEXT: add a1, a4, a2 396; RV32I-NEXT: add a0, a3, a0 397; RV32I-NEXT: sltu a2, a0, a3 398; RV32I-NEXT: add a1, a1, a2 399; RV32I-NEXT: ret 400; 401; RV64I-LABEL: add4: 402; RV64I: # %bb.0: 403; RV64I-NEXT: addi a0, a0, -1 404; RV64I-NEXT: and a0, a0, a1 405; RV64I-NEXT: add a0, a2, a0 406; RV64I-NEXT: ret 407; 408; RV32XVENTANACONDOPS-LABEL: add4: 409; RV32XVENTANACONDOPS: # %bb.0: 410; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 411; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 412; RV32XVENTANACONDOPS-NEXT: add a1, a4, a2 413; RV32XVENTANACONDOPS-NEXT: add a0, a3, a0 414; RV32XVENTANACONDOPS-NEXT: sltu a2, a0, a3 415; RV32XVENTANACONDOPS-NEXT: add a1, a1, a2 416; RV32XVENTANACONDOPS-NEXT: ret 417; 418; RV64XVENTANACONDOPS-LABEL: add4: 419; RV64XVENTANACONDOPS: # %bb.0: 420; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 421; RV64XVENTANACONDOPS-NEXT: add a0, a2, a0 422; RV64XVENTANACONDOPS-NEXT: ret 423; 424; RV64XTHEADCONDMOV-LABEL: add4: 425; RV64XTHEADCONDMOV: # %bb.0: 426; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a0 427; RV64XTHEADCONDMOV-NEXT: add a0, a2, a1 428; RV64XTHEADCONDMOV-NEXT: ret 429; 430; RV32ZICOND-LABEL: add4: 431; RV32ZICOND: # %bb.0: 432; RV32ZICOND-NEXT: czero.nez a2, a2, a0 433; RV32ZICOND-NEXT: czero.nez a0, a1, a0 434; RV32ZICOND-NEXT: add a1, a4, a2 435; RV32ZICOND-NEXT: add a0, a3, a0 436; RV32ZICOND-NEXT: sltu a2, a0, a3 437; RV32ZICOND-NEXT: add a1, a1, a2 438; RV32ZICOND-NEXT: ret 439; 440; RV64ZICOND-LABEL: add4: 441; RV64ZICOND: # %bb.0: 442; RV64ZICOND-NEXT: czero.nez a0, a1, a0 443; RV64ZICOND-NEXT: add a0, a2, a0 444; RV64ZICOND-NEXT: ret 445 %add = add i64 %rs1, %rs2 446 %sel = select i1 %rc, i64 %rs2, i64 %add 447 ret i64 %sel 448} 449 450define i64 @sub1(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 451; RV32I-LABEL: sub1: 452; RV32I: # %bb.0: 453; RV32I-NEXT: neg a0, a0 454; RV32I-NEXT: and a3, a0, a3 455; RV32I-NEXT: and a0, a0, a4 456; RV32I-NEXT: sltu a4, a1, a3 457; RV32I-NEXT: sub a2, a2, a0 458; RV32I-NEXT: sub a2, a2, a4 459; RV32I-NEXT: sub a0, a1, a3 460; RV32I-NEXT: mv a1, a2 461; RV32I-NEXT: ret 462; 463; RV64I-LABEL: sub1: 464; RV64I: # %bb.0: 465; RV64I-NEXT: neg a0, a0 466; RV64I-NEXT: and a0, a0, a2 467; RV64I-NEXT: sub a0, a1, a0 468; RV64I-NEXT: ret 469; 470; RV32XVENTANACONDOPS-LABEL: sub1: 471; RV32XVENTANACONDOPS: # %bb.0: 472; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a0 473; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a4, a0 474; RV32XVENTANACONDOPS-NEXT: sltu a4, a1, a3 475; RV32XVENTANACONDOPS-NEXT: sub a2, a2, a0 476; RV32XVENTANACONDOPS-NEXT: sub a2, a2, a4 477; RV32XVENTANACONDOPS-NEXT: sub a0, a1, a3 478; RV32XVENTANACONDOPS-NEXT: mv a1, a2 479; RV32XVENTANACONDOPS-NEXT: ret 480; 481; RV64XVENTANACONDOPS-LABEL: sub1: 482; RV64XVENTANACONDOPS: # %bb.0: 483; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0 484; RV64XVENTANACONDOPS-NEXT: sub a0, a1, a0 485; RV64XVENTANACONDOPS-NEXT: ret 486; 487; RV64XTHEADCONDMOV-LABEL: sub1: 488; RV64XTHEADCONDMOV: # %bb.0: 489; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, zero, a0 490; RV64XTHEADCONDMOV-NEXT: sub a0, a1, a2 491; RV64XTHEADCONDMOV-NEXT: ret 492; 493; RV32ZICOND-LABEL: sub1: 494; RV32ZICOND: # %bb.0: 495; RV32ZICOND-NEXT: czero.eqz a3, a3, a0 496; RV32ZICOND-NEXT: czero.eqz a0, a4, a0 497; RV32ZICOND-NEXT: sltu a4, a1, a3 498; RV32ZICOND-NEXT: sub a2, a2, a0 499; RV32ZICOND-NEXT: sub a2, a2, a4 500; RV32ZICOND-NEXT: sub a0, a1, a3 501; RV32ZICOND-NEXT: mv a1, a2 502; RV32ZICOND-NEXT: ret 503; 504; RV64ZICOND-LABEL: sub1: 505; RV64ZICOND: # %bb.0: 506; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 507; RV64ZICOND-NEXT: sub a0, a1, a0 508; RV64ZICOND-NEXT: ret 509 %sub = sub i64 %rs1, %rs2 510 %sel = select i1 %rc, i64 %sub, i64 %rs1 511 ret i64 %sel 512} 513 514define i64 @sub2(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 515; RV32I-LABEL: sub2: 516; RV32I: # %bb.0: 517; RV32I-NEXT: addi a0, a0, -1 518; RV32I-NEXT: and a3, a0, a3 519; RV32I-NEXT: and a0, a0, a4 520; RV32I-NEXT: sltu a4, a1, a3 521; RV32I-NEXT: sub a2, a2, a0 522; RV32I-NEXT: sub a2, a2, a4 523; RV32I-NEXT: sub a0, a1, a3 524; RV32I-NEXT: mv a1, a2 525; RV32I-NEXT: ret 526; 527; RV64I-LABEL: sub2: 528; RV64I: # %bb.0: 529; RV64I-NEXT: addi a0, a0, -1 530; RV64I-NEXT: and a0, a0, a2 531; RV64I-NEXT: sub a0, a1, a0 532; RV64I-NEXT: ret 533; 534; RV32XVENTANACONDOPS-LABEL: sub2: 535; RV32XVENTANACONDOPS: # %bb.0: 536; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0 537; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a4, a0 538; RV32XVENTANACONDOPS-NEXT: sltu a4, a1, a3 539; RV32XVENTANACONDOPS-NEXT: sub a2, a2, a0 540; RV32XVENTANACONDOPS-NEXT: sub a2, a2, a4 541; RV32XVENTANACONDOPS-NEXT: sub a0, a1, a3 542; RV32XVENTANACONDOPS-NEXT: mv a1, a2 543; RV32XVENTANACONDOPS-NEXT: ret 544; 545; RV64XVENTANACONDOPS-LABEL: sub2: 546; RV64XVENTANACONDOPS: # %bb.0: 547; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 548; RV64XVENTANACONDOPS-NEXT: sub a0, a1, a0 549; RV64XVENTANACONDOPS-NEXT: ret 550; 551; RV64XTHEADCONDMOV-LABEL: sub2: 552; RV64XTHEADCONDMOV: # %bb.0: 553; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, zero, a0 554; RV64XTHEADCONDMOV-NEXT: sub a0, a1, a2 555; RV64XTHEADCONDMOV-NEXT: ret 556; 557; RV32ZICOND-LABEL: sub2: 558; RV32ZICOND: # %bb.0: 559; RV32ZICOND-NEXT: czero.nez a3, a3, a0 560; RV32ZICOND-NEXT: czero.nez a0, a4, a0 561; RV32ZICOND-NEXT: sltu a4, a1, a3 562; RV32ZICOND-NEXT: sub a2, a2, a0 563; RV32ZICOND-NEXT: sub a2, a2, a4 564; RV32ZICOND-NEXT: sub a0, a1, a3 565; RV32ZICOND-NEXT: mv a1, a2 566; RV32ZICOND-NEXT: ret 567; 568; RV64ZICOND-LABEL: sub2: 569; RV64ZICOND: # %bb.0: 570; RV64ZICOND-NEXT: czero.nez a0, a2, a0 571; RV64ZICOND-NEXT: sub a0, a1, a0 572; RV64ZICOND-NEXT: ret 573 %sub = sub i64 %rs1, %rs2 574 %sel = select i1 %rc, i64 %rs1, i64 %sub 575 ret i64 %sel 576} 577 578define i64 @or1(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 579; RV32I-LABEL: or1: 580; RV32I: # %bb.0: 581; RV32I-NEXT: neg a0, a0 582; RV32I-NEXT: and a3, a0, a3 583; RV32I-NEXT: and a4, a0, a4 584; RV32I-NEXT: or a0, a1, a3 585; RV32I-NEXT: or a1, a2, a4 586; RV32I-NEXT: ret 587; 588; RV64I-LABEL: or1: 589; RV64I: # %bb.0: 590; RV64I-NEXT: neg a0, a0 591; RV64I-NEXT: and a0, a0, a2 592; RV64I-NEXT: or a0, a1, a0 593; RV64I-NEXT: ret 594; 595; RV32XVENTANACONDOPS-LABEL: or1: 596; RV32XVENTANACONDOPS: # %bb.0: 597; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a0 598; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a4, a0 599; RV32XVENTANACONDOPS-NEXT: or a0, a1, a3 600; RV32XVENTANACONDOPS-NEXT: or a1, a2, a4 601; RV32XVENTANACONDOPS-NEXT: ret 602; 603; RV64XVENTANACONDOPS-LABEL: or1: 604; RV64XVENTANACONDOPS: # %bb.0: 605; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0 606; RV64XVENTANACONDOPS-NEXT: or a0, a1, a0 607; RV64XVENTANACONDOPS-NEXT: ret 608; 609; RV64XTHEADCONDMOV-LABEL: or1: 610; RV64XTHEADCONDMOV: # %bb.0: 611; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, zero, a0 612; RV64XTHEADCONDMOV-NEXT: or a0, a1, a2 613; RV64XTHEADCONDMOV-NEXT: ret 614; 615; RV32ZICOND-LABEL: or1: 616; RV32ZICOND: # %bb.0: 617; RV32ZICOND-NEXT: czero.eqz a3, a3, a0 618; RV32ZICOND-NEXT: czero.eqz a4, a4, a0 619; RV32ZICOND-NEXT: or a0, a1, a3 620; RV32ZICOND-NEXT: or a1, a2, a4 621; RV32ZICOND-NEXT: ret 622; 623; RV64ZICOND-LABEL: or1: 624; RV64ZICOND: # %bb.0: 625; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 626; RV64ZICOND-NEXT: or a0, a1, a0 627; RV64ZICOND-NEXT: ret 628 %or = or i64 %rs1, %rs2 629 %sel = select i1 %rc, i64 %or, i64 %rs1 630 ret i64 %sel 631} 632 633define i64 @or2(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 634; RV32I-LABEL: or2: 635; RV32I: # %bb.0: 636; RV32I-NEXT: neg a0, a0 637; RV32I-NEXT: and a1, a0, a1 638; RV32I-NEXT: and a2, a0, a2 639; RV32I-NEXT: or a0, a3, a1 640; RV32I-NEXT: or a1, a4, a2 641; RV32I-NEXT: ret 642; 643; RV64I-LABEL: or2: 644; RV64I: # %bb.0: 645; RV64I-NEXT: neg a0, a0 646; RV64I-NEXT: and a0, a0, a1 647; RV64I-NEXT: or a0, a2, a0 648; RV64I-NEXT: ret 649; 650; RV32XVENTANACONDOPS-LABEL: or2: 651; RV32XVENTANACONDOPS: # %bb.0: 652; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a0 653; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 654; RV32XVENTANACONDOPS-NEXT: or a0, a3, a1 655; RV32XVENTANACONDOPS-NEXT: or a1, a4, a2 656; RV32XVENTANACONDOPS-NEXT: ret 657; 658; RV64XVENTANACONDOPS-LABEL: or2: 659; RV64XVENTANACONDOPS: # %bb.0: 660; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 661; RV64XVENTANACONDOPS-NEXT: or a0, a2, a0 662; RV64XVENTANACONDOPS-NEXT: ret 663; 664; RV64XTHEADCONDMOV-LABEL: or2: 665; RV64XTHEADCONDMOV: # %bb.0: 666; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a0 667; RV64XTHEADCONDMOV-NEXT: or a0, a2, a1 668; RV64XTHEADCONDMOV-NEXT: ret 669; 670; RV32ZICOND-LABEL: or2: 671; RV32ZICOND: # %bb.0: 672; RV32ZICOND-NEXT: czero.eqz a1, a1, a0 673; RV32ZICOND-NEXT: czero.eqz a2, a2, a0 674; RV32ZICOND-NEXT: or a0, a3, a1 675; RV32ZICOND-NEXT: or a1, a4, a2 676; RV32ZICOND-NEXT: ret 677; 678; RV64ZICOND-LABEL: or2: 679; RV64ZICOND: # %bb.0: 680; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 681; RV64ZICOND-NEXT: or a0, a2, a0 682; RV64ZICOND-NEXT: ret 683 %or = or i64 %rs1, %rs2 684 %sel = select i1 %rc, i64 %or, i64 %rs2 685 ret i64 %sel 686} 687 688define i64 @or3(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 689; RV32I-LABEL: or3: 690; RV32I: # %bb.0: 691; RV32I-NEXT: addi a0, a0, -1 692; RV32I-NEXT: and a3, a0, a3 693; RV32I-NEXT: and a4, a0, a4 694; RV32I-NEXT: or a0, a1, a3 695; RV32I-NEXT: or a1, a2, a4 696; RV32I-NEXT: ret 697; 698; RV64I-LABEL: or3: 699; RV64I: # %bb.0: 700; RV64I-NEXT: addi a0, a0, -1 701; RV64I-NEXT: and a0, a0, a2 702; RV64I-NEXT: or a0, a1, a0 703; RV64I-NEXT: ret 704; 705; RV32XVENTANACONDOPS-LABEL: or3: 706; RV32XVENTANACONDOPS: # %bb.0: 707; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0 708; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a4, a0 709; RV32XVENTANACONDOPS-NEXT: or a0, a1, a3 710; RV32XVENTANACONDOPS-NEXT: or a1, a2, a4 711; RV32XVENTANACONDOPS-NEXT: ret 712; 713; RV64XVENTANACONDOPS-LABEL: or3: 714; RV64XVENTANACONDOPS: # %bb.0: 715; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 716; RV64XVENTANACONDOPS-NEXT: or a0, a1, a0 717; RV64XVENTANACONDOPS-NEXT: ret 718; 719; RV64XTHEADCONDMOV-LABEL: or3: 720; RV64XTHEADCONDMOV: # %bb.0: 721; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, zero, a0 722; RV64XTHEADCONDMOV-NEXT: or a0, a1, a2 723; RV64XTHEADCONDMOV-NEXT: ret 724; 725; RV32ZICOND-LABEL: or3: 726; RV32ZICOND: # %bb.0: 727; RV32ZICOND-NEXT: czero.nez a3, a3, a0 728; RV32ZICOND-NEXT: czero.nez a4, a4, a0 729; RV32ZICOND-NEXT: or a0, a1, a3 730; RV32ZICOND-NEXT: or a1, a2, a4 731; RV32ZICOND-NEXT: ret 732; 733; RV64ZICOND-LABEL: or3: 734; RV64ZICOND: # %bb.0: 735; RV64ZICOND-NEXT: czero.nez a0, a2, a0 736; RV64ZICOND-NEXT: or a0, a1, a0 737; RV64ZICOND-NEXT: ret 738 %or = or i64 %rs1, %rs2 739 %sel = select i1 %rc, i64 %rs1, i64 %or 740 ret i64 %sel 741} 742 743define i64 @or4(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 744; RV32I-LABEL: or4: 745; RV32I: # %bb.0: 746; RV32I-NEXT: addi a0, a0, -1 747; RV32I-NEXT: and a1, a0, a1 748; RV32I-NEXT: and a2, a0, a2 749; RV32I-NEXT: or a0, a3, a1 750; RV32I-NEXT: or a1, a4, a2 751; RV32I-NEXT: ret 752; 753; RV64I-LABEL: or4: 754; RV64I: # %bb.0: 755; RV64I-NEXT: addi a0, a0, -1 756; RV64I-NEXT: and a0, a0, a1 757; RV64I-NEXT: or a0, a2, a0 758; RV64I-NEXT: ret 759; 760; RV32XVENTANACONDOPS-LABEL: or4: 761; RV32XVENTANACONDOPS: # %bb.0: 762; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a0 763; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 764; RV32XVENTANACONDOPS-NEXT: or a0, a3, a1 765; RV32XVENTANACONDOPS-NEXT: or a1, a4, a2 766; RV32XVENTANACONDOPS-NEXT: ret 767; 768; RV64XVENTANACONDOPS-LABEL: or4: 769; RV64XVENTANACONDOPS: # %bb.0: 770; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 771; RV64XVENTANACONDOPS-NEXT: or a0, a2, a0 772; RV64XVENTANACONDOPS-NEXT: ret 773; 774; RV64XTHEADCONDMOV-LABEL: or4: 775; RV64XTHEADCONDMOV: # %bb.0: 776; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a0 777; RV64XTHEADCONDMOV-NEXT: or a0, a2, a1 778; RV64XTHEADCONDMOV-NEXT: ret 779; 780; RV32ZICOND-LABEL: or4: 781; RV32ZICOND: # %bb.0: 782; RV32ZICOND-NEXT: czero.nez a1, a1, a0 783; RV32ZICOND-NEXT: czero.nez a2, a2, a0 784; RV32ZICOND-NEXT: or a0, a3, a1 785; RV32ZICOND-NEXT: or a1, a4, a2 786; RV32ZICOND-NEXT: ret 787; 788; RV64ZICOND-LABEL: or4: 789; RV64ZICOND: # %bb.0: 790; RV64ZICOND-NEXT: czero.nez a0, a1, a0 791; RV64ZICOND-NEXT: or a0, a2, a0 792; RV64ZICOND-NEXT: ret 793 %or = or i64 %rs1, %rs2 794 %sel = select i1 %rc, i64 %rs2, i64 %or 795 ret i64 %sel 796} 797 798define i64 @xor1(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 799; RV32I-LABEL: xor1: 800; RV32I: # %bb.0: 801; RV32I-NEXT: neg a0, a0 802; RV32I-NEXT: and a3, a0, a3 803; RV32I-NEXT: and a4, a0, a4 804; RV32I-NEXT: xor a0, a1, a3 805; RV32I-NEXT: xor a1, a2, a4 806; RV32I-NEXT: ret 807; 808; RV64I-LABEL: xor1: 809; RV64I: # %bb.0: 810; RV64I-NEXT: neg a0, a0 811; RV64I-NEXT: and a0, a0, a2 812; RV64I-NEXT: xor a0, a1, a0 813; RV64I-NEXT: ret 814; 815; RV32XVENTANACONDOPS-LABEL: xor1: 816; RV32XVENTANACONDOPS: # %bb.0: 817; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a0 818; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a4, a0 819; RV32XVENTANACONDOPS-NEXT: xor a0, a1, a3 820; RV32XVENTANACONDOPS-NEXT: xor a1, a2, a4 821; RV32XVENTANACONDOPS-NEXT: ret 822; 823; RV64XVENTANACONDOPS-LABEL: xor1: 824; RV64XVENTANACONDOPS: # %bb.0: 825; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0 826; RV64XVENTANACONDOPS-NEXT: xor a0, a1, a0 827; RV64XVENTANACONDOPS-NEXT: ret 828; 829; RV64XTHEADCONDMOV-LABEL: xor1: 830; RV64XTHEADCONDMOV: # %bb.0: 831; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, zero, a0 832; RV64XTHEADCONDMOV-NEXT: xor a0, a1, a2 833; RV64XTHEADCONDMOV-NEXT: ret 834; 835; RV32ZICOND-LABEL: xor1: 836; RV32ZICOND: # %bb.0: 837; RV32ZICOND-NEXT: czero.eqz a3, a3, a0 838; RV32ZICOND-NEXT: czero.eqz a4, a4, a0 839; RV32ZICOND-NEXT: xor a0, a1, a3 840; RV32ZICOND-NEXT: xor a1, a2, a4 841; RV32ZICOND-NEXT: ret 842; 843; RV64ZICOND-LABEL: xor1: 844; RV64ZICOND: # %bb.0: 845; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 846; RV64ZICOND-NEXT: xor a0, a1, a0 847; RV64ZICOND-NEXT: ret 848 %xor = xor i64 %rs1, %rs2 849 %sel = select i1 %rc, i64 %xor, i64 %rs1 850 ret i64 %sel 851} 852 853define i64 @xor2(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 854; RV32I-LABEL: xor2: 855; RV32I: # %bb.0: 856; RV32I-NEXT: neg a0, a0 857; RV32I-NEXT: and a1, a0, a1 858; RV32I-NEXT: and a2, a0, a2 859; RV32I-NEXT: xor a0, a3, a1 860; RV32I-NEXT: xor a1, a4, a2 861; RV32I-NEXT: ret 862; 863; RV64I-LABEL: xor2: 864; RV64I: # %bb.0: 865; RV64I-NEXT: neg a0, a0 866; RV64I-NEXT: and a0, a0, a1 867; RV64I-NEXT: xor a0, a2, a0 868; RV64I-NEXT: ret 869; 870; RV32XVENTANACONDOPS-LABEL: xor2: 871; RV32XVENTANACONDOPS: # %bb.0: 872; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a0 873; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 874; RV32XVENTANACONDOPS-NEXT: xor a0, a3, a1 875; RV32XVENTANACONDOPS-NEXT: xor a1, a4, a2 876; RV32XVENTANACONDOPS-NEXT: ret 877; 878; RV64XVENTANACONDOPS-LABEL: xor2: 879; RV64XVENTANACONDOPS: # %bb.0: 880; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 881; RV64XVENTANACONDOPS-NEXT: xor a0, a2, a0 882; RV64XVENTANACONDOPS-NEXT: ret 883; 884; RV64XTHEADCONDMOV-LABEL: xor2: 885; RV64XTHEADCONDMOV: # %bb.0: 886; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a0 887; RV64XTHEADCONDMOV-NEXT: xor a0, a2, a1 888; RV64XTHEADCONDMOV-NEXT: ret 889; 890; RV32ZICOND-LABEL: xor2: 891; RV32ZICOND: # %bb.0: 892; RV32ZICOND-NEXT: czero.eqz a1, a1, a0 893; RV32ZICOND-NEXT: czero.eqz a2, a2, a0 894; RV32ZICOND-NEXT: xor a0, a3, a1 895; RV32ZICOND-NEXT: xor a1, a4, a2 896; RV32ZICOND-NEXT: ret 897; 898; RV64ZICOND-LABEL: xor2: 899; RV64ZICOND: # %bb.0: 900; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 901; RV64ZICOND-NEXT: xor a0, a2, a0 902; RV64ZICOND-NEXT: ret 903 %xor = xor i64 %rs1, %rs2 904 %sel = select i1 %rc, i64 %xor, i64 %rs2 905 ret i64 %sel 906} 907 908define i64 @xor3(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 909; RV32I-LABEL: xor3: 910; RV32I: # %bb.0: 911; RV32I-NEXT: addi a0, a0, -1 912; RV32I-NEXT: and a3, a0, a3 913; RV32I-NEXT: and a4, a0, a4 914; RV32I-NEXT: xor a0, a1, a3 915; RV32I-NEXT: xor a1, a2, a4 916; RV32I-NEXT: ret 917; 918; RV64I-LABEL: xor3: 919; RV64I: # %bb.0: 920; RV64I-NEXT: addi a0, a0, -1 921; RV64I-NEXT: and a0, a0, a2 922; RV64I-NEXT: xor a0, a1, a0 923; RV64I-NEXT: ret 924; 925; RV32XVENTANACONDOPS-LABEL: xor3: 926; RV32XVENTANACONDOPS: # %bb.0: 927; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0 928; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a4, a0 929; RV32XVENTANACONDOPS-NEXT: xor a0, a1, a3 930; RV32XVENTANACONDOPS-NEXT: xor a1, a2, a4 931; RV32XVENTANACONDOPS-NEXT: ret 932; 933; RV64XVENTANACONDOPS-LABEL: xor3: 934; RV64XVENTANACONDOPS: # %bb.0: 935; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 936; RV64XVENTANACONDOPS-NEXT: xor a0, a1, a0 937; RV64XVENTANACONDOPS-NEXT: ret 938; 939; RV64XTHEADCONDMOV-LABEL: xor3: 940; RV64XTHEADCONDMOV: # %bb.0: 941; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, zero, a0 942; RV64XTHEADCONDMOV-NEXT: xor a0, a1, a2 943; RV64XTHEADCONDMOV-NEXT: ret 944; 945; RV32ZICOND-LABEL: xor3: 946; RV32ZICOND: # %bb.0: 947; RV32ZICOND-NEXT: czero.nez a3, a3, a0 948; RV32ZICOND-NEXT: czero.nez a4, a4, a0 949; RV32ZICOND-NEXT: xor a0, a1, a3 950; RV32ZICOND-NEXT: xor a1, a2, a4 951; RV32ZICOND-NEXT: ret 952; 953; RV64ZICOND-LABEL: xor3: 954; RV64ZICOND: # %bb.0: 955; RV64ZICOND-NEXT: czero.nez a0, a2, a0 956; RV64ZICOND-NEXT: xor a0, a1, a0 957; RV64ZICOND-NEXT: ret 958 %xor = xor i64 %rs1, %rs2 959 %sel = select i1 %rc, i64 %rs1, i64 %xor 960 ret i64 %sel 961} 962 963define i64 @xor4(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 964; RV32I-LABEL: xor4: 965; RV32I: # %bb.0: 966; RV32I-NEXT: addi a0, a0, -1 967; RV32I-NEXT: and a1, a0, a1 968; RV32I-NEXT: and a2, a0, a2 969; RV32I-NEXT: xor a0, a3, a1 970; RV32I-NEXT: xor a1, a4, a2 971; RV32I-NEXT: ret 972; 973; RV64I-LABEL: xor4: 974; RV64I: # %bb.0: 975; RV64I-NEXT: addi a0, a0, -1 976; RV64I-NEXT: and a0, a0, a1 977; RV64I-NEXT: xor a0, a2, a0 978; RV64I-NEXT: ret 979; 980; RV32XVENTANACONDOPS-LABEL: xor4: 981; RV32XVENTANACONDOPS: # %bb.0: 982; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a0 983; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 984; RV32XVENTANACONDOPS-NEXT: xor a0, a3, a1 985; RV32XVENTANACONDOPS-NEXT: xor a1, a4, a2 986; RV32XVENTANACONDOPS-NEXT: ret 987; 988; RV64XVENTANACONDOPS-LABEL: xor4: 989; RV64XVENTANACONDOPS: # %bb.0: 990; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 991; RV64XVENTANACONDOPS-NEXT: xor a0, a2, a0 992; RV64XVENTANACONDOPS-NEXT: ret 993; 994; RV64XTHEADCONDMOV-LABEL: xor4: 995; RV64XTHEADCONDMOV: # %bb.0: 996; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a0 997; RV64XTHEADCONDMOV-NEXT: xor a0, a2, a1 998; RV64XTHEADCONDMOV-NEXT: ret 999; 1000; RV32ZICOND-LABEL: xor4: 1001; RV32ZICOND: # %bb.0: 1002; RV32ZICOND-NEXT: czero.nez a1, a1, a0 1003; RV32ZICOND-NEXT: czero.nez a2, a2, a0 1004; RV32ZICOND-NEXT: xor a0, a3, a1 1005; RV32ZICOND-NEXT: xor a1, a4, a2 1006; RV32ZICOND-NEXT: ret 1007; 1008; RV64ZICOND-LABEL: xor4: 1009; RV64ZICOND: # %bb.0: 1010; RV64ZICOND-NEXT: czero.nez a0, a1, a0 1011; RV64ZICOND-NEXT: xor a0, a2, a0 1012; RV64ZICOND-NEXT: ret 1013 %xor = xor i64 %rs1, %rs2 1014 %sel = select i1 %rc, i64 %rs2, i64 %xor 1015 ret i64 %sel 1016} 1017 1018define i64 @and1(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 1019; RV32I-LABEL: and1: 1020; RV32I: # %bb.0: 1021; RV32I-NEXT: beqz a0, .LBB18_2 1022; RV32I-NEXT: # %bb.1: 1023; RV32I-NEXT: and a2, a2, a4 1024; RV32I-NEXT: and a1, a1, a3 1025; RV32I-NEXT: .LBB18_2: 1026; RV32I-NEXT: mv a0, a1 1027; RV32I-NEXT: mv a1, a2 1028; RV32I-NEXT: ret 1029; 1030; RV64I-LABEL: and1: 1031; RV64I: # %bb.0: 1032; RV64I-NEXT: beqz a0, .LBB18_2 1033; RV64I-NEXT: # %bb.1: 1034; RV64I-NEXT: and a1, a1, a2 1035; RV64I-NEXT: .LBB18_2: 1036; RV64I-NEXT: mv a0, a1 1037; RV64I-NEXT: ret 1038; 1039; RV32XVENTANACONDOPS-LABEL: and1: 1040; RV32XVENTANACONDOPS: # %bb.0: 1041; RV32XVENTANACONDOPS-NEXT: and a4, a2, a4 1042; RV32XVENTANACONDOPS-NEXT: and a3, a1, a3 1043; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a0 1044; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 1045; RV32XVENTANACONDOPS-NEXT: or a0, a3, a1 1046; RV32XVENTANACONDOPS-NEXT: or a1, a4, a2 1047; RV32XVENTANACONDOPS-NEXT: ret 1048; 1049; RV64XVENTANACONDOPS-LABEL: and1: 1050; RV64XVENTANACONDOPS: # %bb.0: 1051; RV64XVENTANACONDOPS-NEXT: and a2, a1, a2 1052; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 1053; RV64XVENTANACONDOPS-NEXT: or a0, a2, a0 1054; RV64XVENTANACONDOPS-NEXT: ret 1055; 1056; RV64XTHEADCONDMOV-LABEL: and1: 1057; RV64XTHEADCONDMOV: # %bb.0: 1058; RV64XTHEADCONDMOV-NEXT: and a2, a1, a2 1059; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, a1, a0 1060; RV64XTHEADCONDMOV-NEXT: mv a0, a2 1061; RV64XTHEADCONDMOV-NEXT: ret 1062; 1063; RV32ZICOND-LABEL: and1: 1064; RV32ZICOND: # %bb.0: 1065; RV32ZICOND-NEXT: and a4, a2, a4 1066; RV32ZICOND-NEXT: and a3, a1, a3 1067; RV32ZICOND-NEXT: czero.nez a1, a1, a0 1068; RV32ZICOND-NEXT: czero.nez a2, a2, a0 1069; RV32ZICOND-NEXT: or a0, a3, a1 1070; RV32ZICOND-NEXT: or a1, a4, a2 1071; RV32ZICOND-NEXT: ret 1072; 1073; RV64ZICOND-LABEL: and1: 1074; RV64ZICOND: # %bb.0: 1075; RV64ZICOND-NEXT: and a2, a1, a2 1076; RV64ZICOND-NEXT: czero.nez a0, a1, a0 1077; RV64ZICOND-NEXT: or a0, a2, a0 1078; RV64ZICOND-NEXT: ret 1079 %and = and i64 %rs1, %rs2 1080 %sel = select i1 %rc, i64 %and, i64 %rs1 1081 ret i64 %sel 1082} 1083 1084define i64 @and2(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 1085; RV32I-LABEL: and2: 1086; RV32I: # %bb.0: 1087; RV32I-NEXT: beqz a0, .LBB19_2 1088; RV32I-NEXT: # %bb.1: 1089; RV32I-NEXT: and a4, a2, a4 1090; RV32I-NEXT: and a3, a1, a3 1091; RV32I-NEXT: .LBB19_2: 1092; RV32I-NEXT: mv a0, a3 1093; RV32I-NEXT: mv a1, a4 1094; RV32I-NEXT: ret 1095; 1096; RV64I-LABEL: and2: 1097; RV64I: # %bb.0: 1098; RV64I-NEXT: beqz a0, .LBB19_2 1099; RV64I-NEXT: # %bb.1: 1100; RV64I-NEXT: and a2, a1, a2 1101; RV64I-NEXT: .LBB19_2: 1102; RV64I-NEXT: mv a0, a2 1103; RV64I-NEXT: ret 1104; 1105; RV32XVENTANACONDOPS-LABEL: and2: 1106; RV32XVENTANACONDOPS: # %bb.0: 1107; RV32XVENTANACONDOPS-NEXT: and a2, a2, a4 1108; RV32XVENTANACONDOPS-NEXT: and a1, a1, a3 1109; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0 1110; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a4, a0 1111; RV32XVENTANACONDOPS-NEXT: or a0, a1, a3 1112; RV32XVENTANACONDOPS-NEXT: or a1, a2, a4 1113; RV32XVENTANACONDOPS-NEXT: ret 1114; 1115; RV64XVENTANACONDOPS-LABEL: and2: 1116; RV64XVENTANACONDOPS: # %bb.0: 1117; RV64XVENTANACONDOPS-NEXT: and a1, a1, a2 1118; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 1119; RV64XVENTANACONDOPS-NEXT: or a0, a1, a0 1120; RV64XVENTANACONDOPS-NEXT: ret 1121; 1122; RV64XTHEADCONDMOV-LABEL: and2: 1123; RV64XTHEADCONDMOV: # %bb.0: 1124; RV64XTHEADCONDMOV-NEXT: and a1, a1, a2 1125; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, a2, a0 1126; RV64XTHEADCONDMOV-NEXT: mv a0, a1 1127; RV64XTHEADCONDMOV-NEXT: ret 1128; 1129; RV32ZICOND-LABEL: and2: 1130; RV32ZICOND: # %bb.0: 1131; RV32ZICOND-NEXT: and a2, a2, a4 1132; RV32ZICOND-NEXT: and a1, a1, a3 1133; RV32ZICOND-NEXT: czero.nez a3, a3, a0 1134; RV32ZICOND-NEXT: czero.nez a4, a4, a0 1135; RV32ZICOND-NEXT: or a0, a1, a3 1136; RV32ZICOND-NEXT: or a1, a2, a4 1137; RV32ZICOND-NEXT: ret 1138; 1139; RV64ZICOND-LABEL: and2: 1140; RV64ZICOND: # %bb.0: 1141; RV64ZICOND-NEXT: and a1, a1, a2 1142; RV64ZICOND-NEXT: czero.nez a0, a2, a0 1143; RV64ZICOND-NEXT: or a0, a1, a0 1144; RV64ZICOND-NEXT: ret 1145 %and = and i64 %rs1, %rs2 1146 %sel = select i1 %rc, i64 %and, i64 %rs2 1147 ret i64 %sel 1148} 1149 1150define i64 @and3(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 1151; RV32I-LABEL: and3: 1152; RV32I: # %bb.0: 1153; RV32I-NEXT: bnez a0, .LBB20_2 1154; RV32I-NEXT: # %bb.1: 1155; RV32I-NEXT: and a2, a2, a4 1156; RV32I-NEXT: and a1, a1, a3 1157; RV32I-NEXT: .LBB20_2: 1158; RV32I-NEXT: mv a0, a1 1159; RV32I-NEXT: mv a1, a2 1160; RV32I-NEXT: ret 1161; 1162; RV64I-LABEL: and3: 1163; RV64I: # %bb.0: 1164; RV64I-NEXT: bnez a0, .LBB20_2 1165; RV64I-NEXT: # %bb.1: 1166; RV64I-NEXT: and a1, a1, a2 1167; RV64I-NEXT: .LBB20_2: 1168; RV64I-NEXT: mv a0, a1 1169; RV64I-NEXT: ret 1170; 1171; RV32XVENTANACONDOPS-LABEL: and3: 1172; RV32XVENTANACONDOPS: # %bb.0: 1173; RV32XVENTANACONDOPS-NEXT: and a4, a2, a4 1174; RV32XVENTANACONDOPS-NEXT: and a3, a1, a3 1175; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a0 1176; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 1177; RV32XVENTANACONDOPS-NEXT: or a0, a3, a1 1178; RV32XVENTANACONDOPS-NEXT: or a1, a4, a2 1179; RV32XVENTANACONDOPS-NEXT: ret 1180; 1181; RV64XVENTANACONDOPS-LABEL: and3: 1182; RV64XVENTANACONDOPS: # %bb.0: 1183; RV64XVENTANACONDOPS-NEXT: and a2, a1, a2 1184; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 1185; RV64XVENTANACONDOPS-NEXT: or a0, a2, a0 1186; RV64XVENTANACONDOPS-NEXT: ret 1187; 1188; RV64XTHEADCONDMOV-LABEL: and3: 1189; RV64XTHEADCONDMOV: # %bb.0: 1190; RV64XTHEADCONDMOV-NEXT: and a2, a1, a2 1191; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a1, a0 1192; RV64XTHEADCONDMOV-NEXT: mv a0, a2 1193; RV64XTHEADCONDMOV-NEXT: ret 1194; 1195; RV32ZICOND-LABEL: and3: 1196; RV32ZICOND: # %bb.0: 1197; RV32ZICOND-NEXT: and a4, a2, a4 1198; RV32ZICOND-NEXT: and a3, a1, a3 1199; RV32ZICOND-NEXT: czero.eqz a1, a1, a0 1200; RV32ZICOND-NEXT: czero.eqz a2, a2, a0 1201; RV32ZICOND-NEXT: or a0, a3, a1 1202; RV32ZICOND-NEXT: or a1, a4, a2 1203; RV32ZICOND-NEXT: ret 1204; 1205; RV64ZICOND-LABEL: and3: 1206; RV64ZICOND: # %bb.0: 1207; RV64ZICOND-NEXT: and a2, a1, a2 1208; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 1209; RV64ZICOND-NEXT: or a0, a2, a0 1210; RV64ZICOND-NEXT: ret 1211 %and = and i64 %rs1, %rs2 1212 %sel = select i1 %rc, i64 %rs1, i64 %and 1213 ret i64 %sel 1214} 1215 1216define i64 @and4(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 1217; RV32I-LABEL: and4: 1218; RV32I: # %bb.0: 1219; RV32I-NEXT: bnez a0, .LBB21_2 1220; RV32I-NEXT: # %bb.1: 1221; RV32I-NEXT: and a4, a2, a4 1222; RV32I-NEXT: and a3, a1, a3 1223; RV32I-NEXT: .LBB21_2: 1224; RV32I-NEXT: mv a0, a3 1225; RV32I-NEXT: mv a1, a4 1226; RV32I-NEXT: ret 1227; 1228; RV64I-LABEL: and4: 1229; RV64I: # %bb.0: 1230; RV64I-NEXT: bnez a0, .LBB21_2 1231; RV64I-NEXT: # %bb.1: 1232; RV64I-NEXT: and a2, a1, a2 1233; RV64I-NEXT: .LBB21_2: 1234; RV64I-NEXT: mv a0, a2 1235; RV64I-NEXT: ret 1236; 1237; RV32XVENTANACONDOPS-LABEL: and4: 1238; RV32XVENTANACONDOPS: # %bb.0: 1239; RV32XVENTANACONDOPS-NEXT: and a2, a2, a4 1240; RV32XVENTANACONDOPS-NEXT: and a1, a1, a3 1241; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a0 1242; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a4, a0 1243; RV32XVENTANACONDOPS-NEXT: or a0, a1, a3 1244; RV32XVENTANACONDOPS-NEXT: or a1, a2, a4 1245; RV32XVENTANACONDOPS-NEXT: ret 1246; 1247; RV64XVENTANACONDOPS-LABEL: and4: 1248; RV64XVENTANACONDOPS: # %bb.0: 1249; RV64XVENTANACONDOPS-NEXT: and a1, a1, a2 1250; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0 1251; RV64XVENTANACONDOPS-NEXT: or a0, a1, a0 1252; RV64XVENTANACONDOPS-NEXT: ret 1253; 1254; RV64XTHEADCONDMOV-LABEL: and4: 1255; RV64XTHEADCONDMOV: # %bb.0: 1256; RV64XTHEADCONDMOV-NEXT: and a1, a1, a2 1257; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, a2, a0 1258; RV64XTHEADCONDMOV-NEXT: mv a0, a1 1259; RV64XTHEADCONDMOV-NEXT: ret 1260; 1261; RV32ZICOND-LABEL: and4: 1262; RV32ZICOND: # %bb.0: 1263; RV32ZICOND-NEXT: and a2, a2, a4 1264; RV32ZICOND-NEXT: and a1, a1, a3 1265; RV32ZICOND-NEXT: czero.eqz a3, a3, a0 1266; RV32ZICOND-NEXT: czero.eqz a4, a4, a0 1267; RV32ZICOND-NEXT: or a0, a1, a3 1268; RV32ZICOND-NEXT: or a1, a2, a4 1269; RV32ZICOND-NEXT: ret 1270; 1271; RV64ZICOND-LABEL: and4: 1272; RV64ZICOND: # %bb.0: 1273; RV64ZICOND-NEXT: and a1, a1, a2 1274; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 1275; RV64ZICOND-NEXT: or a0, a1, a0 1276; RV64ZICOND-NEXT: ret 1277 %and = and i64 %rs1, %rs2 1278 %sel = select i1 %rc, i64 %rs2, i64 %and 1279 ret i64 %sel 1280} 1281 1282define i64 @basic(i1 zeroext %rc, i64 %rs1, i64 %rs2) { 1283; RV32I-LABEL: basic: 1284; RV32I: # %bb.0: 1285; RV32I-NEXT: bnez a0, .LBB22_2 1286; RV32I-NEXT: # %bb.1: 1287; RV32I-NEXT: mv a1, a3 1288; RV32I-NEXT: mv a2, a4 1289; RV32I-NEXT: .LBB22_2: 1290; RV32I-NEXT: mv a0, a1 1291; RV32I-NEXT: mv a1, a2 1292; RV32I-NEXT: ret 1293; 1294; RV64I-LABEL: basic: 1295; RV64I: # %bb.0: 1296; RV64I-NEXT: bnez a0, .LBB22_2 1297; RV64I-NEXT: # %bb.1: 1298; RV64I-NEXT: mv a1, a2 1299; RV64I-NEXT: .LBB22_2: 1300; RV64I-NEXT: mv a0, a1 1301; RV64I-NEXT: ret 1302; 1303; RV32XVENTANACONDOPS-LABEL: basic: 1304; RV32XVENTANACONDOPS: # %bb.0: 1305; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0 1306; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a0 1307; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a4, a0 1308; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 1309; RV32XVENTANACONDOPS-NEXT: or a0, a1, a3 1310; RV32XVENTANACONDOPS-NEXT: or a1, a2, a4 1311; RV32XVENTANACONDOPS-NEXT: ret 1312; 1313; RV64XVENTANACONDOPS-LABEL: basic: 1314; RV64XVENTANACONDOPS: # %bb.0: 1315; RV64XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 1316; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 1317; RV64XVENTANACONDOPS-NEXT: or a0, a0, a2 1318; RV64XVENTANACONDOPS-NEXT: ret 1319; 1320; RV64XTHEADCONDMOV-LABEL: basic: 1321; RV64XTHEADCONDMOV: # %bb.0: 1322; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, a2, a0 1323; RV64XTHEADCONDMOV-NEXT: mv a0, a1 1324; RV64XTHEADCONDMOV-NEXT: ret 1325; 1326; RV32ZICOND-LABEL: basic: 1327; RV32ZICOND: # %bb.0: 1328; RV32ZICOND-NEXT: czero.nez a3, a3, a0 1329; RV32ZICOND-NEXT: czero.eqz a1, a1, a0 1330; RV32ZICOND-NEXT: czero.nez a4, a4, a0 1331; RV32ZICOND-NEXT: czero.eqz a2, a2, a0 1332; RV32ZICOND-NEXT: or a0, a1, a3 1333; RV32ZICOND-NEXT: or a1, a2, a4 1334; RV32ZICOND-NEXT: ret 1335; 1336; RV64ZICOND-LABEL: basic: 1337; RV64ZICOND: # %bb.0: 1338; RV64ZICOND-NEXT: czero.nez a2, a2, a0 1339; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 1340; RV64ZICOND-NEXT: or a0, a0, a2 1341; RV64ZICOND-NEXT: ret 1342 %sel = select i1 %rc, i64 %rs1, i64 %rs2 1343 ret i64 %sel 1344} 1345 1346define i64 @seteq(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { 1347; RV32I-LABEL: seteq: 1348; RV32I: # %bb.0: 1349; RV32I-NEXT: xor a1, a1, a3 1350; RV32I-NEXT: xor a0, a0, a2 1351; RV32I-NEXT: or a1, a0, a1 1352; RV32I-NEXT: mv a0, a4 1353; RV32I-NEXT: beqz a1, .LBB23_2 1354; RV32I-NEXT: # %bb.1: 1355; RV32I-NEXT: mv a0, a6 1356; RV32I-NEXT: mv a5, a7 1357; RV32I-NEXT: .LBB23_2: 1358; RV32I-NEXT: mv a1, a5 1359; RV32I-NEXT: ret 1360; 1361; RV64I-LABEL: seteq: 1362; RV64I: # %bb.0: 1363; RV64I-NEXT: beq a0, a1, .LBB23_2 1364; RV64I-NEXT: # %bb.1: 1365; RV64I-NEXT: mv a2, a3 1366; RV64I-NEXT: .LBB23_2: 1367; RV64I-NEXT: mv a0, a2 1368; RV64I-NEXT: ret 1369; 1370; RV32XVENTANACONDOPS-LABEL: seteq: 1371; RV32XVENTANACONDOPS: # %bb.0: 1372; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a3 1373; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a2 1374; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 1375; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a0 1376; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a0 1377; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a7, a0 1378; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a0 1379; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 1380; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 1381; RV32XVENTANACONDOPS-NEXT: ret 1382; 1383; RV64XVENTANACONDOPS-LABEL: seteq: 1384; RV64XVENTANACONDOPS: # %bb.0: 1385; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a1 1386; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 1387; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 1388; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 1389; RV64XVENTANACONDOPS-NEXT: ret 1390; 1391; RV64XTHEADCONDMOV-LABEL: seteq: 1392; RV64XTHEADCONDMOV: # %bb.0: 1393; RV64XTHEADCONDMOV-NEXT: xor a0, a0, a1 1394; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a0 1395; RV64XTHEADCONDMOV-NEXT: mv a0, a2 1396; RV64XTHEADCONDMOV-NEXT: ret 1397; 1398; RV32ZICOND-LABEL: seteq: 1399; RV32ZICOND: # %bb.0: 1400; RV32ZICOND-NEXT: xor a1, a1, a3 1401; RV32ZICOND-NEXT: xor a0, a0, a2 1402; RV32ZICOND-NEXT: or a0, a0, a1 1403; RV32ZICOND-NEXT: czero.eqz a1, a6, a0 1404; RV32ZICOND-NEXT: czero.nez a2, a4, a0 1405; RV32ZICOND-NEXT: czero.eqz a3, a7, a0 1406; RV32ZICOND-NEXT: czero.nez a4, a5, a0 1407; RV32ZICOND-NEXT: or a0, a2, a1 1408; RV32ZICOND-NEXT: or a1, a4, a3 1409; RV32ZICOND-NEXT: ret 1410; 1411; RV64ZICOND-LABEL: seteq: 1412; RV64ZICOND: # %bb.0: 1413; RV64ZICOND-NEXT: xor a0, a0, a1 1414; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 1415; RV64ZICOND-NEXT: czero.nez a0, a2, a0 1416; RV64ZICOND-NEXT: or a0, a0, a1 1417; RV64ZICOND-NEXT: ret 1418 %rc = icmp eq i64 %a, %b 1419 %sel = select i1 %rc, i64 %rs1, i64 %rs2 1420 ret i64 %sel 1421} 1422 1423define i64 @setne(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { 1424; RV32I-LABEL: setne: 1425; RV32I: # %bb.0: 1426; RV32I-NEXT: xor a1, a1, a3 1427; RV32I-NEXT: xor a0, a0, a2 1428; RV32I-NEXT: or a1, a0, a1 1429; RV32I-NEXT: mv a0, a4 1430; RV32I-NEXT: bnez a1, .LBB24_2 1431; RV32I-NEXT: # %bb.1: 1432; RV32I-NEXT: mv a0, a6 1433; RV32I-NEXT: mv a5, a7 1434; RV32I-NEXT: .LBB24_2: 1435; RV32I-NEXT: mv a1, a5 1436; RV32I-NEXT: ret 1437; 1438; RV64I-LABEL: setne: 1439; RV64I: # %bb.0: 1440; RV64I-NEXT: bne a0, a1, .LBB24_2 1441; RV64I-NEXT: # %bb.1: 1442; RV64I-NEXT: mv a2, a3 1443; RV64I-NEXT: .LBB24_2: 1444; RV64I-NEXT: mv a0, a2 1445; RV64I-NEXT: ret 1446; 1447; RV32XVENTANACONDOPS-LABEL: setne: 1448; RV32XVENTANACONDOPS: # %bb.0: 1449; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a3 1450; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a2 1451; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 1452; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a0 1453; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a0 1454; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a7, a0 1455; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 1456; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 1457; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 1458; RV32XVENTANACONDOPS-NEXT: ret 1459; 1460; RV64XVENTANACONDOPS-LABEL: setne: 1461; RV64XVENTANACONDOPS: # %bb.0: 1462; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a1 1463; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a0 1464; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0 1465; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 1466; RV64XVENTANACONDOPS-NEXT: ret 1467; 1468; RV64XTHEADCONDMOV-LABEL: setne: 1469; RV64XTHEADCONDMOV: # %bb.0: 1470; RV64XTHEADCONDMOV-NEXT: xor a0, a0, a1 1471; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, a3, a0 1472; RV64XTHEADCONDMOV-NEXT: mv a0, a2 1473; RV64XTHEADCONDMOV-NEXT: ret 1474; 1475; RV32ZICOND-LABEL: setne: 1476; RV32ZICOND: # %bb.0: 1477; RV32ZICOND-NEXT: xor a1, a1, a3 1478; RV32ZICOND-NEXT: xor a0, a0, a2 1479; RV32ZICOND-NEXT: or a0, a0, a1 1480; RV32ZICOND-NEXT: czero.nez a1, a6, a0 1481; RV32ZICOND-NEXT: czero.eqz a2, a4, a0 1482; RV32ZICOND-NEXT: czero.nez a3, a7, a0 1483; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 1484; RV32ZICOND-NEXT: or a0, a2, a1 1485; RV32ZICOND-NEXT: or a1, a4, a3 1486; RV32ZICOND-NEXT: ret 1487; 1488; RV64ZICOND-LABEL: setne: 1489; RV64ZICOND: # %bb.0: 1490; RV64ZICOND-NEXT: xor a0, a0, a1 1491; RV64ZICOND-NEXT: czero.nez a1, a3, a0 1492; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 1493; RV64ZICOND-NEXT: or a0, a0, a1 1494; RV64ZICOND-NEXT: ret 1495 %rc = icmp ne i64 %a, %b 1496 %sel = select i1 %rc, i64 %rs1, i64 %rs2 1497 ret i64 %sel 1498} 1499 1500define i64 @setgt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { 1501; RV32I-LABEL: setgt: 1502; RV32I: # %bb.0: 1503; RV32I-NEXT: beq a1, a3, .LBB25_2 1504; RV32I-NEXT: # %bb.1: 1505; RV32I-NEXT: slt a0, a3, a1 1506; RV32I-NEXT: beqz a0, .LBB25_3 1507; RV32I-NEXT: j .LBB25_4 1508; RV32I-NEXT: .LBB25_2: 1509; RV32I-NEXT: sltu a0, a2, a0 1510; RV32I-NEXT: bnez a0, .LBB25_4 1511; RV32I-NEXT: .LBB25_3: 1512; RV32I-NEXT: mv a4, a6 1513; RV32I-NEXT: mv a5, a7 1514; RV32I-NEXT: .LBB25_4: 1515; RV32I-NEXT: mv a0, a4 1516; RV32I-NEXT: mv a1, a5 1517; RV32I-NEXT: ret 1518; 1519; RV64I-LABEL: setgt: 1520; RV64I: # %bb.0: 1521; RV64I-NEXT: blt a1, a0, .LBB25_2 1522; RV64I-NEXT: # %bb.1: 1523; RV64I-NEXT: mv a2, a3 1524; RV64I-NEXT: .LBB25_2: 1525; RV64I-NEXT: mv a0, a2 1526; RV64I-NEXT: ret 1527; 1528; RV32XVENTANACONDOPS-LABEL: setgt: 1529; RV32XVENTANACONDOPS: # %bb.0: 1530; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3 1531; RV32XVENTANACONDOPS-NEXT: slt a1, a3, a1 1532; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a0 1533; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0 1534; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0 1535; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 1536; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a0 1537; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a0 1538; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a7, a0 1539; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 1540; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 1541; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 1542; RV32XVENTANACONDOPS-NEXT: ret 1543; 1544; RV64XVENTANACONDOPS-LABEL: setgt: 1545; RV64XVENTANACONDOPS: # %bb.0: 1546; RV64XVENTANACONDOPS-NEXT: slt a0, a1, a0 1547; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a0 1548; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0 1549; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 1550; RV64XVENTANACONDOPS-NEXT: ret 1551; 1552; RV64XTHEADCONDMOV-LABEL: setgt: 1553; RV64XTHEADCONDMOV: # %bb.0: 1554; RV64XTHEADCONDMOV-NEXT: slt a0, a1, a0 1555; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, a3, a0 1556; RV64XTHEADCONDMOV-NEXT: mv a0, a2 1557; RV64XTHEADCONDMOV-NEXT: ret 1558; 1559; RV32ZICOND-LABEL: setgt: 1560; RV32ZICOND: # %bb.0: 1561; RV32ZICOND-NEXT: xor t0, a1, a3 1562; RV32ZICOND-NEXT: slt a1, a3, a1 1563; RV32ZICOND-NEXT: sltu a0, a2, a0 1564; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 1565; RV32ZICOND-NEXT: czero.nez a0, a0, t0 1566; RV32ZICOND-NEXT: or a0, a0, a1 1567; RV32ZICOND-NEXT: czero.nez a1, a6, a0 1568; RV32ZICOND-NEXT: czero.eqz a2, a4, a0 1569; RV32ZICOND-NEXT: czero.nez a3, a7, a0 1570; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 1571; RV32ZICOND-NEXT: or a0, a2, a1 1572; RV32ZICOND-NEXT: or a1, a4, a3 1573; RV32ZICOND-NEXT: ret 1574; 1575; RV64ZICOND-LABEL: setgt: 1576; RV64ZICOND: # %bb.0: 1577; RV64ZICOND-NEXT: slt a0, a1, a0 1578; RV64ZICOND-NEXT: czero.nez a1, a3, a0 1579; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 1580; RV64ZICOND-NEXT: or a0, a0, a1 1581; RV64ZICOND-NEXT: ret 1582 %rc = icmp sgt i64 %a, %b 1583 %sel = select i1 %rc, i64 %rs1, i64 %rs2 1584 ret i64 %sel 1585} 1586 1587define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { 1588; RV32I-LABEL: setge: 1589; RV32I: # %bb.0: 1590; RV32I-NEXT: beq a1, a3, .LBB26_2 1591; RV32I-NEXT: # %bb.1: 1592; RV32I-NEXT: slt a0, a1, a3 1593; RV32I-NEXT: bnez a0, .LBB26_3 1594; RV32I-NEXT: j .LBB26_4 1595; RV32I-NEXT: .LBB26_2: 1596; RV32I-NEXT: sltu a0, a0, a2 1597; RV32I-NEXT: beqz a0, .LBB26_4 1598; RV32I-NEXT: .LBB26_3: 1599; RV32I-NEXT: mv a4, a6 1600; RV32I-NEXT: mv a5, a7 1601; RV32I-NEXT: .LBB26_4: 1602; RV32I-NEXT: mv a0, a4 1603; RV32I-NEXT: mv a1, a5 1604; RV32I-NEXT: ret 1605; 1606; RV64I-LABEL: setge: 1607; RV64I: # %bb.0: 1608; RV64I-NEXT: bge a0, a1, .LBB26_2 1609; RV64I-NEXT: # %bb.1: 1610; RV64I-NEXT: mv a2, a3 1611; RV64I-NEXT: .LBB26_2: 1612; RV64I-NEXT: mv a0, a2 1613; RV64I-NEXT: ret 1614; 1615; RV32XVENTANACONDOPS-LABEL: setge: 1616; RV32XVENTANACONDOPS: # %bb.0: 1617; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3 1618; RV32XVENTANACONDOPS-NEXT: slt a1, a1, a3 1619; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a2 1620; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0 1621; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0 1622; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 1623; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a0 1624; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a0 1625; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a7, a0 1626; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a0 1627; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 1628; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 1629; RV32XVENTANACONDOPS-NEXT: ret 1630; 1631; RV64XVENTANACONDOPS-LABEL: setge: 1632; RV64XVENTANACONDOPS: # %bb.0: 1633; RV64XVENTANACONDOPS-NEXT: slt a0, a0, a1 1634; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 1635; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 1636; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 1637; RV64XVENTANACONDOPS-NEXT: ret 1638; 1639; RV64XTHEADCONDMOV-LABEL: setge: 1640; RV64XTHEADCONDMOV: # %bb.0: 1641; RV64XTHEADCONDMOV-NEXT: slt a0, a0, a1 1642; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a0 1643; RV64XTHEADCONDMOV-NEXT: mv a0, a2 1644; RV64XTHEADCONDMOV-NEXT: ret 1645; 1646; RV32ZICOND-LABEL: setge: 1647; RV32ZICOND: # %bb.0: 1648; RV32ZICOND-NEXT: xor t0, a1, a3 1649; RV32ZICOND-NEXT: slt a1, a1, a3 1650; RV32ZICOND-NEXT: sltu a0, a0, a2 1651; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 1652; RV32ZICOND-NEXT: czero.nez a0, a0, t0 1653; RV32ZICOND-NEXT: or a0, a0, a1 1654; RV32ZICOND-NEXT: czero.eqz a1, a6, a0 1655; RV32ZICOND-NEXT: czero.nez a2, a4, a0 1656; RV32ZICOND-NEXT: czero.eqz a3, a7, a0 1657; RV32ZICOND-NEXT: czero.nez a4, a5, a0 1658; RV32ZICOND-NEXT: or a0, a2, a1 1659; RV32ZICOND-NEXT: or a1, a4, a3 1660; RV32ZICOND-NEXT: ret 1661; 1662; RV64ZICOND-LABEL: setge: 1663; RV64ZICOND: # %bb.0: 1664; RV64ZICOND-NEXT: slt a0, a0, a1 1665; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 1666; RV64ZICOND-NEXT: czero.nez a0, a2, a0 1667; RV64ZICOND-NEXT: or a0, a0, a1 1668; RV64ZICOND-NEXT: ret 1669 %rc = icmp sge i64 %a, %b 1670 %sel = select i1 %rc, i64 %rs1, i64 %rs2 1671 ret i64 %sel 1672} 1673 1674define i64 @setlt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { 1675; RV32I-LABEL: setlt: 1676; RV32I: # %bb.0: 1677; RV32I-NEXT: beq a1, a3, .LBB27_2 1678; RV32I-NEXT: # %bb.1: 1679; RV32I-NEXT: slt a0, a1, a3 1680; RV32I-NEXT: beqz a0, .LBB27_3 1681; RV32I-NEXT: j .LBB27_4 1682; RV32I-NEXT: .LBB27_2: 1683; RV32I-NEXT: sltu a0, a0, a2 1684; RV32I-NEXT: bnez a0, .LBB27_4 1685; RV32I-NEXT: .LBB27_3: 1686; RV32I-NEXT: mv a4, a6 1687; RV32I-NEXT: mv a5, a7 1688; RV32I-NEXT: .LBB27_4: 1689; RV32I-NEXT: mv a0, a4 1690; RV32I-NEXT: mv a1, a5 1691; RV32I-NEXT: ret 1692; 1693; RV64I-LABEL: setlt: 1694; RV64I: # %bb.0: 1695; RV64I-NEXT: blt a0, a1, .LBB27_2 1696; RV64I-NEXT: # %bb.1: 1697; RV64I-NEXT: mv a2, a3 1698; RV64I-NEXT: .LBB27_2: 1699; RV64I-NEXT: mv a0, a2 1700; RV64I-NEXT: ret 1701; 1702; RV32XVENTANACONDOPS-LABEL: setlt: 1703; RV32XVENTANACONDOPS: # %bb.0: 1704; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3 1705; RV32XVENTANACONDOPS-NEXT: slt a1, a1, a3 1706; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a2 1707; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0 1708; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0 1709; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 1710; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a0 1711; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a0 1712; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a7, a0 1713; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 1714; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 1715; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 1716; RV32XVENTANACONDOPS-NEXT: ret 1717; 1718; RV64XVENTANACONDOPS-LABEL: setlt: 1719; RV64XVENTANACONDOPS: # %bb.0: 1720; RV64XVENTANACONDOPS-NEXT: slt a0, a0, a1 1721; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a0 1722; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0 1723; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 1724; RV64XVENTANACONDOPS-NEXT: ret 1725; 1726; RV64XTHEADCONDMOV-LABEL: setlt: 1727; RV64XTHEADCONDMOV: # %bb.0: 1728; RV64XTHEADCONDMOV-NEXT: slt a0, a0, a1 1729; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, a3, a0 1730; RV64XTHEADCONDMOV-NEXT: mv a0, a2 1731; RV64XTHEADCONDMOV-NEXT: ret 1732; 1733; RV32ZICOND-LABEL: setlt: 1734; RV32ZICOND: # %bb.0: 1735; RV32ZICOND-NEXT: xor t0, a1, a3 1736; RV32ZICOND-NEXT: slt a1, a1, a3 1737; RV32ZICOND-NEXT: sltu a0, a0, a2 1738; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 1739; RV32ZICOND-NEXT: czero.nez a0, a0, t0 1740; RV32ZICOND-NEXT: or a0, a0, a1 1741; RV32ZICOND-NEXT: czero.nez a1, a6, a0 1742; RV32ZICOND-NEXT: czero.eqz a2, a4, a0 1743; RV32ZICOND-NEXT: czero.nez a3, a7, a0 1744; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 1745; RV32ZICOND-NEXT: or a0, a2, a1 1746; RV32ZICOND-NEXT: or a1, a4, a3 1747; RV32ZICOND-NEXT: ret 1748; 1749; RV64ZICOND-LABEL: setlt: 1750; RV64ZICOND: # %bb.0: 1751; RV64ZICOND-NEXT: slt a0, a0, a1 1752; RV64ZICOND-NEXT: czero.nez a1, a3, a0 1753; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 1754; RV64ZICOND-NEXT: or a0, a0, a1 1755; RV64ZICOND-NEXT: ret 1756 %rc = icmp slt i64 %a, %b 1757 %sel = select i1 %rc, i64 %rs1, i64 %rs2 1758 ret i64 %sel 1759} 1760 1761define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { 1762; RV32I-LABEL: setle: 1763; RV32I: # %bb.0: 1764; RV32I-NEXT: beq a1, a3, .LBB28_2 1765; RV32I-NEXT: # %bb.1: 1766; RV32I-NEXT: slt a0, a3, a1 1767; RV32I-NEXT: bnez a0, .LBB28_3 1768; RV32I-NEXT: j .LBB28_4 1769; RV32I-NEXT: .LBB28_2: 1770; RV32I-NEXT: sltu a0, a2, a0 1771; RV32I-NEXT: beqz a0, .LBB28_4 1772; RV32I-NEXT: .LBB28_3: 1773; RV32I-NEXT: mv a4, a6 1774; RV32I-NEXT: mv a5, a7 1775; RV32I-NEXT: .LBB28_4: 1776; RV32I-NEXT: mv a0, a4 1777; RV32I-NEXT: mv a1, a5 1778; RV32I-NEXT: ret 1779; 1780; RV64I-LABEL: setle: 1781; RV64I: # %bb.0: 1782; RV64I-NEXT: bge a1, a0, .LBB28_2 1783; RV64I-NEXT: # %bb.1: 1784; RV64I-NEXT: mv a2, a3 1785; RV64I-NEXT: .LBB28_2: 1786; RV64I-NEXT: mv a0, a2 1787; RV64I-NEXT: ret 1788; 1789; RV32XVENTANACONDOPS-LABEL: setle: 1790; RV32XVENTANACONDOPS: # %bb.0: 1791; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3 1792; RV32XVENTANACONDOPS-NEXT: slt a1, a3, a1 1793; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a0 1794; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0 1795; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0 1796; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 1797; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a0 1798; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a0 1799; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a7, a0 1800; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a0 1801; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 1802; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 1803; RV32XVENTANACONDOPS-NEXT: ret 1804; 1805; RV64XVENTANACONDOPS-LABEL: setle: 1806; RV64XVENTANACONDOPS: # %bb.0: 1807; RV64XVENTANACONDOPS-NEXT: slt a0, a1, a0 1808; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 1809; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 1810; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 1811; RV64XVENTANACONDOPS-NEXT: ret 1812; 1813; RV64XTHEADCONDMOV-LABEL: setle: 1814; RV64XTHEADCONDMOV: # %bb.0: 1815; RV64XTHEADCONDMOV-NEXT: slt a0, a1, a0 1816; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a0 1817; RV64XTHEADCONDMOV-NEXT: mv a0, a2 1818; RV64XTHEADCONDMOV-NEXT: ret 1819; 1820; RV32ZICOND-LABEL: setle: 1821; RV32ZICOND: # %bb.0: 1822; RV32ZICOND-NEXT: xor t0, a1, a3 1823; RV32ZICOND-NEXT: slt a1, a3, a1 1824; RV32ZICOND-NEXT: sltu a0, a2, a0 1825; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 1826; RV32ZICOND-NEXT: czero.nez a0, a0, t0 1827; RV32ZICOND-NEXT: or a0, a0, a1 1828; RV32ZICOND-NEXT: czero.eqz a1, a6, a0 1829; RV32ZICOND-NEXT: czero.nez a2, a4, a0 1830; RV32ZICOND-NEXT: czero.eqz a3, a7, a0 1831; RV32ZICOND-NEXT: czero.nez a4, a5, a0 1832; RV32ZICOND-NEXT: or a0, a2, a1 1833; RV32ZICOND-NEXT: or a1, a4, a3 1834; RV32ZICOND-NEXT: ret 1835; 1836; RV64ZICOND-LABEL: setle: 1837; RV64ZICOND: # %bb.0: 1838; RV64ZICOND-NEXT: slt a0, a1, a0 1839; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 1840; RV64ZICOND-NEXT: czero.nez a0, a2, a0 1841; RV64ZICOND-NEXT: or a0, a0, a1 1842; RV64ZICOND-NEXT: ret 1843 %rc = icmp sle i64 %a, %b 1844 %sel = select i1 %rc, i64 %rs1, i64 %rs2 1845 ret i64 %sel 1846} 1847 1848define i64 @setugt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { 1849; RV32I-LABEL: setugt: 1850; RV32I: # %bb.0: 1851; RV32I-NEXT: beq a1, a3, .LBB29_2 1852; RV32I-NEXT: # %bb.1: 1853; RV32I-NEXT: sltu a0, a3, a1 1854; RV32I-NEXT: beqz a0, .LBB29_3 1855; RV32I-NEXT: j .LBB29_4 1856; RV32I-NEXT: .LBB29_2: 1857; RV32I-NEXT: sltu a0, a2, a0 1858; RV32I-NEXT: bnez a0, .LBB29_4 1859; RV32I-NEXT: .LBB29_3: 1860; RV32I-NEXT: mv a4, a6 1861; RV32I-NEXT: mv a5, a7 1862; RV32I-NEXT: .LBB29_4: 1863; RV32I-NEXT: mv a0, a4 1864; RV32I-NEXT: mv a1, a5 1865; RV32I-NEXT: ret 1866; 1867; RV64I-LABEL: setugt: 1868; RV64I: # %bb.0: 1869; RV64I-NEXT: bltu a1, a0, .LBB29_2 1870; RV64I-NEXT: # %bb.1: 1871; RV64I-NEXT: mv a2, a3 1872; RV64I-NEXT: .LBB29_2: 1873; RV64I-NEXT: mv a0, a2 1874; RV64I-NEXT: ret 1875; 1876; RV32XVENTANACONDOPS-LABEL: setugt: 1877; RV32XVENTANACONDOPS: # %bb.0: 1878; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3 1879; RV32XVENTANACONDOPS-NEXT: sltu a1, a3, a1 1880; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a0 1881; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0 1882; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0 1883; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 1884; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a0 1885; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a0 1886; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a7, a0 1887; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 1888; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 1889; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 1890; RV32XVENTANACONDOPS-NEXT: ret 1891; 1892; RV64XVENTANACONDOPS-LABEL: setugt: 1893; RV64XVENTANACONDOPS: # %bb.0: 1894; RV64XVENTANACONDOPS-NEXT: sltu a0, a1, a0 1895; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a0 1896; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0 1897; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 1898; RV64XVENTANACONDOPS-NEXT: ret 1899; 1900; RV64XTHEADCONDMOV-LABEL: setugt: 1901; RV64XTHEADCONDMOV: # %bb.0: 1902; RV64XTHEADCONDMOV-NEXT: sltu a0, a1, a0 1903; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, a3, a0 1904; RV64XTHEADCONDMOV-NEXT: mv a0, a2 1905; RV64XTHEADCONDMOV-NEXT: ret 1906; 1907; RV32ZICOND-LABEL: setugt: 1908; RV32ZICOND: # %bb.0: 1909; RV32ZICOND-NEXT: xor t0, a1, a3 1910; RV32ZICOND-NEXT: sltu a1, a3, a1 1911; RV32ZICOND-NEXT: sltu a0, a2, a0 1912; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 1913; RV32ZICOND-NEXT: czero.nez a0, a0, t0 1914; RV32ZICOND-NEXT: or a0, a0, a1 1915; RV32ZICOND-NEXT: czero.nez a1, a6, a0 1916; RV32ZICOND-NEXT: czero.eqz a2, a4, a0 1917; RV32ZICOND-NEXT: czero.nez a3, a7, a0 1918; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 1919; RV32ZICOND-NEXT: or a0, a2, a1 1920; RV32ZICOND-NEXT: or a1, a4, a3 1921; RV32ZICOND-NEXT: ret 1922; 1923; RV64ZICOND-LABEL: setugt: 1924; RV64ZICOND: # %bb.0: 1925; RV64ZICOND-NEXT: sltu a0, a1, a0 1926; RV64ZICOND-NEXT: czero.nez a1, a3, a0 1927; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 1928; RV64ZICOND-NEXT: or a0, a0, a1 1929; RV64ZICOND-NEXT: ret 1930 %rc = icmp ugt i64 %a, %b 1931 %sel = select i1 %rc, i64 %rs1, i64 %rs2 1932 ret i64 %sel 1933} 1934 1935define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { 1936; RV32I-LABEL: setuge: 1937; RV32I: # %bb.0: 1938; RV32I-NEXT: beq a1, a3, .LBB30_2 1939; RV32I-NEXT: # %bb.1: 1940; RV32I-NEXT: sltu a0, a1, a3 1941; RV32I-NEXT: bnez a0, .LBB30_3 1942; RV32I-NEXT: j .LBB30_4 1943; RV32I-NEXT: .LBB30_2: 1944; RV32I-NEXT: sltu a0, a0, a2 1945; RV32I-NEXT: beqz a0, .LBB30_4 1946; RV32I-NEXT: .LBB30_3: 1947; RV32I-NEXT: mv a4, a6 1948; RV32I-NEXT: mv a5, a7 1949; RV32I-NEXT: .LBB30_4: 1950; RV32I-NEXT: mv a0, a4 1951; RV32I-NEXT: mv a1, a5 1952; RV32I-NEXT: ret 1953; 1954; RV64I-LABEL: setuge: 1955; RV64I: # %bb.0: 1956; RV64I-NEXT: bgeu a0, a1, .LBB30_2 1957; RV64I-NEXT: # %bb.1: 1958; RV64I-NEXT: mv a2, a3 1959; RV64I-NEXT: .LBB30_2: 1960; RV64I-NEXT: mv a0, a2 1961; RV64I-NEXT: ret 1962; 1963; RV32XVENTANACONDOPS-LABEL: setuge: 1964; RV32XVENTANACONDOPS: # %bb.0: 1965; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3 1966; RV32XVENTANACONDOPS-NEXT: sltu a1, a1, a3 1967; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a2 1968; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0 1969; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0 1970; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 1971; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a0 1972; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a0 1973; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a7, a0 1974; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a0 1975; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 1976; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 1977; RV32XVENTANACONDOPS-NEXT: ret 1978; 1979; RV64XVENTANACONDOPS-LABEL: setuge: 1980; RV64XVENTANACONDOPS: # %bb.0: 1981; RV64XVENTANACONDOPS-NEXT: sltu a0, a0, a1 1982; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 1983; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 1984; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 1985; RV64XVENTANACONDOPS-NEXT: ret 1986; 1987; RV64XTHEADCONDMOV-LABEL: setuge: 1988; RV64XTHEADCONDMOV: # %bb.0: 1989; RV64XTHEADCONDMOV-NEXT: sltu a0, a0, a1 1990; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a0 1991; RV64XTHEADCONDMOV-NEXT: mv a0, a2 1992; RV64XTHEADCONDMOV-NEXT: ret 1993; 1994; RV32ZICOND-LABEL: setuge: 1995; RV32ZICOND: # %bb.0: 1996; RV32ZICOND-NEXT: xor t0, a1, a3 1997; RV32ZICOND-NEXT: sltu a1, a1, a3 1998; RV32ZICOND-NEXT: sltu a0, a0, a2 1999; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 2000; RV32ZICOND-NEXT: czero.nez a0, a0, t0 2001; RV32ZICOND-NEXT: or a0, a0, a1 2002; RV32ZICOND-NEXT: czero.eqz a1, a6, a0 2003; RV32ZICOND-NEXT: czero.nez a2, a4, a0 2004; RV32ZICOND-NEXT: czero.eqz a3, a7, a0 2005; RV32ZICOND-NEXT: czero.nez a4, a5, a0 2006; RV32ZICOND-NEXT: or a0, a2, a1 2007; RV32ZICOND-NEXT: or a1, a4, a3 2008; RV32ZICOND-NEXT: ret 2009; 2010; RV64ZICOND-LABEL: setuge: 2011; RV64ZICOND: # %bb.0: 2012; RV64ZICOND-NEXT: sltu a0, a0, a1 2013; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 2014; RV64ZICOND-NEXT: czero.nez a0, a2, a0 2015; RV64ZICOND-NEXT: or a0, a0, a1 2016; RV64ZICOND-NEXT: ret 2017 %rc = icmp uge i64 %a, %b 2018 %sel = select i1 %rc, i64 %rs1, i64 %rs2 2019 ret i64 %sel 2020} 2021 2022define i64 @setult(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { 2023; RV32I-LABEL: setult: 2024; RV32I: # %bb.0: 2025; RV32I-NEXT: beq a1, a3, .LBB31_2 2026; RV32I-NEXT: # %bb.1: 2027; RV32I-NEXT: sltu a0, a1, a3 2028; RV32I-NEXT: beqz a0, .LBB31_3 2029; RV32I-NEXT: j .LBB31_4 2030; RV32I-NEXT: .LBB31_2: 2031; RV32I-NEXT: sltu a0, a0, a2 2032; RV32I-NEXT: bnez a0, .LBB31_4 2033; RV32I-NEXT: .LBB31_3: 2034; RV32I-NEXT: mv a4, a6 2035; RV32I-NEXT: mv a5, a7 2036; RV32I-NEXT: .LBB31_4: 2037; RV32I-NEXT: mv a0, a4 2038; RV32I-NEXT: mv a1, a5 2039; RV32I-NEXT: ret 2040; 2041; RV64I-LABEL: setult: 2042; RV64I: # %bb.0: 2043; RV64I-NEXT: bltu a0, a1, .LBB31_2 2044; RV64I-NEXT: # %bb.1: 2045; RV64I-NEXT: mv a2, a3 2046; RV64I-NEXT: .LBB31_2: 2047; RV64I-NEXT: mv a0, a2 2048; RV64I-NEXT: ret 2049; 2050; RV32XVENTANACONDOPS-LABEL: setult: 2051; RV32XVENTANACONDOPS: # %bb.0: 2052; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3 2053; RV32XVENTANACONDOPS-NEXT: sltu a1, a1, a3 2054; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a2 2055; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0 2056; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0 2057; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 2058; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a0 2059; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a0 2060; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a7, a0 2061; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 2062; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 2063; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 2064; RV32XVENTANACONDOPS-NEXT: ret 2065; 2066; RV64XVENTANACONDOPS-LABEL: setult: 2067; RV64XVENTANACONDOPS: # %bb.0: 2068; RV64XVENTANACONDOPS-NEXT: sltu a0, a0, a1 2069; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a0 2070; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0 2071; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 2072; RV64XVENTANACONDOPS-NEXT: ret 2073; 2074; RV64XTHEADCONDMOV-LABEL: setult: 2075; RV64XTHEADCONDMOV: # %bb.0: 2076; RV64XTHEADCONDMOV-NEXT: sltu a0, a0, a1 2077; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, a3, a0 2078; RV64XTHEADCONDMOV-NEXT: mv a0, a2 2079; RV64XTHEADCONDMOV-NEXT: ret 2080; 2081; RV32ZICOND-LABEL: setult: 2082; RV32ZICOND: # %bb.0: 2083; RV32ZICOND-NEXT: xor t0, a1, a3 2084; RV32ZICOND-NEXT: sltu a1, a1, a3 2085; RV32ZICOND-NEXT: sltu a0, a0, a2 2086; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 2087; RV32ZICOND-NEXT: czero.nez a0, a0, t0 2088; RV32ZICOND-NEXT: or a0, a0, a1 2089; RV32ZICOND-NEXT: czero.nez a1, a6, a0 2090; RV32ZICOND-NEXT: czero.eqz a2, a4, a0 2091; RV32ZICOND-NEXT: czero.nez a3, a7, a0 2092; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 2093; RV32ZICOND-NEXT: or a0, a2, a1 2094; RV32ZICOND-NEXT: or a1, a4, a3 2095; RV32ZICOND-NEXT: ret 2096; 2097; RV64ZICOND-LABEL: setult: 2098; RV64ZICOND: # %bb.0: 2099; RV64ZICOND-NEXT: sltu a0, a0, a1 2100; RV64ZICOND-NEXT: czero.nez a1, a3, a0 2101; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 2102; RV64ZICOND-NEXT: or a0, a0, a1 2103; RV64ZICOND-NEXT: ret 2104 %rc = icmp ult i64 %a, %b 2105 %sel = select i1 %rc, i64 %rs1, i64 %rs2 2106 ret i64 %sel 2107} 2108 2109define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { 2110; RV32I-LABEL: setule: 2111; RV32I: # %bb.0: 2112; RV32I-NEXT: beq a1, a3, .LBB32_2 2113; RV32I-NEXT: # %bb.1: 2114; RV32I-NEXT: sltu a0, a3, a1 2115; RV32I-NEXT: bnez a0, .LBB32_3 2116; RV32I-NEXT: j .LBB32_4 2117; RV32I-NEXT: .LBB32_2: 2118; RV32I-NEXT: sltu a0, a2, a0 2119; RV32I-NEXT: beqz a0, .LBB32_4 2120; RV32I-NEXT: .LBB32_3: 2121; RV32I-NEXT: mv a4, a6 2122; RV32I-NEXT: mv a5, a7 2123; RV32I-NEXT: .LBB32_4: 2124; RV32I-NEXT: mv a0, a4 2125; RV32I-NEXT: mv a1, a5 2126; RV32I-NEXT: ret 2127; 2128; RV64I-LABEL: setule: 2129; RV64I: # %bb.0: 2130; RV64I-NEXT: bgeu a1, a0, .LBB32_2 2131; RV64I-NEXT: # %bb.1: 2132; RV64I-NEXT: mv a2, a3 2133; RV64I-NEXT: .LBB32_2: 2134; RV64I-NEXT: mv a0, a2 2135; RV64I-NEXT: ret 2136; 2137; RV32XVENTANACONDOPS-LABEL: setule: 2138; RV32XVENTANACONDOPS: # %bb.0: 2139; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3 2140; RV32XVENTANACONDOPS-NEXT: sltu a1, a3, a1 2141; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a0 2142; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0 2143; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0 2144; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 2145; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a0 2146; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a0 2147; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a7, a0 2148; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a0 2149; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 2150; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 2151; RV32XVENTANACONDOPS-NEXT: ret 2152; 2153; RV64XVENTANACONDOPS-LABEL: setule: 2154; RV64XVENTANACONDOPS: # %bb.0: 2155; RV64XVENTANACONDOPS-NEXT: sltu a0, a1, a0 2156; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 2157; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 2158; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 2159; RV64XVENTANACONDOPS-NEXT: ret 2160; 2161; RV64XTHEADCONDMOV-LABEL: setule: 2162; RV64XTHEADCONDMOV: # %bb.0: 2163; RV64XTHEADCONDMOV-NEXT: sltu a0, a1, a0 2164; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a0 2165; RV64XTHEADCONDMOV-NEXT: mv a0, a2 2166; RV64XTHEADCONDMOV-NEXT: ret 2167; 2168; RV32ZICOND-LABEL: setule: 2169; RV32ZICOND: # %bb.0: 2170; RV32ZICOND-NEXT: xor t0, a1, a3 2171; RV32ZICOND-NEXT: sltu a1, a3, a1 2172; RV32ZICOND-NEXT: sltu a0, a2, a0 2173; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 2174; RV32ZICOND-NEXT: czero.nez a0, a0, t0 2175; RV32ZICOND-NEXT: or a0, a0, a1 2176; RV32ZICOND-NEXT: czero.eqz a1, a6, a0 2177; RV32ZICOND-NEXT: czero.nez a2, a4, a0 2178; RV32ZICOND-NEXT: czero.eqz a3, a7, a0 2179; RV32ZICOND-NEXT: czero.nez a4, a5, a0 2180; RV32ZICOND-NEXT: or a0, a2, a1 2181; RV32ZICOND-NEXT: or a1, a4, a3 2182; RV32ZICOND-NEXT: ret 2183; 2184; RV64ZICOND-LABEL: setule: 2185; RV64ZICOND: # %bb.0: 2186; RV64ZICOND-NEXT: sltu a0, a1, a0 2187; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 2188; RV64ZICOND-NEXT: czero.nez a0, a2, a0 2189; RV64ZICOND-NEXT: or a0, a0, a1 2190; RV64ZICOND-NEXT: ret 2191 %rc = icmp ule i64 %a, %b 2192 %sel = select i1 %rc, i64 %rs1, i64 %rs2 2193 ret i64 %sel 2194} 2195 2196define i64 @seteq_zero(i64 %a, i64 %rs1, i64 %rs2) { 2197; RV32I-LABEL: seteq_zero: 2198; RV32I: # %bb.0: 2199; RV32I-NEXT: or a1, a0, a1 2200; RV32I-NEXT: mv a0, a2 2201; RV32I-NEXT: beqz a1, .LBB33_2 2202; RV32I-NEXT: # %bb.1: 2203; RV32I-NEXT: mv a0, a4 2204; RV32I-NEXT: mv a3, a5 2205; RV32I-NEXT: .LBB33_2: 2206; RV32I-NEXT: mv a1, a3 2207; RV32I-NEXT: ret 2208; 2209; RV64I-LABEL: seteq_zero: 2210; RV64I: # %bb.0: 2211; RV64I-NEXT: beqz a0, .LBB33_2 2212; RV64I-NEXT: # %bb.1: 2213; RV64I-NEXT: mv a1, a2 2214; RV64I-NEXT: .LBB33_2: 2215; RV64I-NEXT: mv a0, a1 2216; RV64I-NEXT: ret 2217; 2218; RV32XVENTANACONDOPS-LABEL: seteq_zero: 2219; RV32XVENTANACONDOPS: # %bb.0: 2220; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 2221; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a4, a0 2222; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 2223; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 2224; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0 2225; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 2226; RV32XVENTANACONDOPS-NEXT: or a1, a3, a4 2227; RV32XVENTANACONDOPS-NEXT: ret 2228; 2229; RV64XVENTANACONDOPS-LABEL: seteq_zero: 2230; RV64XVENTANACONDOPS: # %bb.0: 2231; RV64XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 2232; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 2233; RV64XVENTANACONDOPS-NEXT: or a0, a0, a2 2234; RV64XVENTANACONDOPS-NEXT: ret 2235; 2236; RV64XTHEADCONDMOV-LABEL: seteq_zero: 2237; RV64XTHEADCONDMOV: # %bb.0: 2238; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, a2, a0 2239; RV64XTHEADCONDMOV-NEXT: mv a0, a1 2240; RV64XTHEADCONDMOV-NEXT: ret 2241; 2242; RV32ZICOND-LABEL: seteq_zero: 2243; RV32ZICOND: # %bb.0: 2244; RV32ZICOND-NEXT: or a0, a0, a1 2245; RV32ZICOND-NEXT: czero.eqz a1, a4, a0 2246; RV32ZICOND-NEXT: czero.nez a2, a2, a0 2247; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 2248; RV32ZICOND-NEXT: czero.nez a3, a3, a0 2249; RV32ZICOND-NEXT: or a0, a2, a1 2250; RV32ZICOND-NEXT: or a1, a3, a4 2251; RV32ZICOND-NEXT: ret 2252; 2253; RV64ZICOND-LABEL: seteq_zero: 2254; RV64ZICOND: # %bb.0: 2255; RV64ZICOND-NEXT: czero.eqz a2, a2, a0 2256; RV64ZICOND-NEXT: czero.nez a0, a1, a0 2257; RV64ZICOND-NEXT: or a0, a0, a2 2258; RV64ZICOND-NEXT: ret 2259 %rc = icmp eq i64 %a, 0 2260 %sel = select i1 %rc, i64 %rs1, i64 %rs2 2261 ret i64 %sel 2262} 2263 2264define i64 @setne_zero(i64 %a, i64 %rs1, i64 %rs2) { 2265; RV32I-LABEL: setne_zero: 2266; RV32I: # %bb.0: 2267; RV32I-NEXT: or a1, a0, a1 2268; RV32I-NEXT: mv a0, a2 2269; RV32I-NEXT: bnez a1, .LBB34_2 2270; RV32I-NEXT: # %bb.1: 2271; RV32I-NEXT: mv a0, a4 2272; RV32I-NEXT: mv a3, a5 2273; RV32I-NEXT: .LBB34_2: 2274; RV32I-NEXT: mv a1, a3 2275; RV32I-NEXT: ret 2276; 2277; RV64I-LABEL: setne_zero: 2278; RV64I: # %bb.0: 2279; RV64I-NEXT: bnez a0, .LBB34_2 2280; RV64I-NEXT: # %bb.1: 2281; RV64I-NEXT: mv a1, a2 2282; RV64I-NEXT: .LBB34_2: 2283; RV64I-NEXT: mv a0, a1 2284; RV64I-NEXT: ret 2285; 2286; RV32XVENTANACONDOPS-LABEL: setne_zero: 2287; RV32XVENTANACONDOPS: # %bb.0: 2288; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 2289; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a4, a0 2290; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 2291; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a0 2292; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a0 2293; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 2294; RV32XVENTANACONDOPS-NEXT: or a1, a3, a4 2295; RV32XVENTANACONDOPS-NEXT: ret 2296; 2297; RV64XVENTANACONDOPS-LABEL: setne_zero: 2298; RV64XVENTANACONDOPS: # %bb.0: 2299; RV64XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 2300; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 2301; RV64XVENTANACONDOPS-NEXT: or a0, a0, a2 2302; RV64XVENTANACONDOPS-NEXT: ret 2303; 2304; RV64XTHEADCONDMOV-LABEL: setne_zero: 2305; RV64XTHEADCONDMOV: # %bb.0: 2306; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, a2, a0 2307; RV64XTHEADCONDMOV-NEXT: mv a0, a1 2308; RV64XTHEADCONDMOV-NEXT: ret 2309; 2310; RV32ZICOND-LABEL: setne_zero: 2311; RV32ZICOND: # %bb.0: 2312; RV32ZICOND-NEXT: or a0, a0, a1 2313; RV32ZICOND-NEXT: czero.nez a1, a4, a0 2314; RV32ZICOND-NEXT: czero.eqz a2, a2, a0 2315; RV32ZICOND-NEXT: czero.nez a4, a5, a0 2316; RV32ZICOND-NEXT: czero.eqz a3, a3, a0 2317; RV32ZICOND-NEXT: or a0, a2, a1 2318; RV32ZICOND-NEXT: or a1, a3, a4 2319; RV32ZICOND-NEXT: ret 2320; 2321; RV64ZICOND-LABEL: setne_zero: 2322; RV64ZICOND: # %bb.0: 2323; RV64ZICOND-NEXT: czero.nez a2, a2, a0 2324; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 2325; RV64ZICOND-NEXT: or a0, a0, a2 2326; RV64ZICOND-NEXT: ret 2327 %rc = icmp ne i64 %a, 0 2328 %sel = select i1 %rc, i64 %rs1, i64 %rs2 2329 ret i64 %sel 2330} 2331 2332define i64 @seteq_constant(i64 %a, i64 %rs1, i64 %rs2) { 2333; RV32I-LABEL: seteq_constant: 2334; RV32I: # %bb.0: 2335; RV32I-NEXT: xori a0, a0, 123 2336; RV32I-NEXT: or a1, a0, a1 2337; RV32I-NEXT: mv a0, a2 2338; RV32I-NEXT: beqz a1, .LBB35_2 2339; RV32I-NEXT: # %bb.1: 2340; RV32I-NEXT: mv a0, a4 2341; RV32I-NEXT: mv a3, a5 2342; RV32I-NEXT: .LBB35_2: 2343; RV32I-NEXT: mv a1, a3 2344; RV32I-NEXT: ret 2345; 2346; RV64I-LABEL: seteq_constant: 2347; RV64I: # %bb.0: 2348; RV64I-NEXT: li a3, 123 2349; RV64I-NEXT: beq a0, a3, .LBB35_2 2350; RV64I-NEXT: # %bb.1: 2351; RV64I-NEXT: mv a1, a2 2352; RV64I-NEXT: .LBB35_2: 2353; RV64I-NEXT: mv a0, a1 2354; RV64I-NEXT: ret 2355; 2356; RV32XVENTANACONDOPS-LABEL: seteq_constant: 2357; RV32XVENTANACONDOPS: # %bb.0: 2358; RV32XVENTANACONDOPS-NEXT: xori a0, a0, 123 2359; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 2360; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a4, a0 2361; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 2362; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 2363; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0 2364; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 2365; RV32XVENTANACONDOPS-NEXT: or a1, a3, a4 2366; RV32XVENTANACONDOPS-NEXT: ret 2367; 2368; RV64XVENTANACONDOPS-LABEL: seteq_constant: 2369; RV64XVENTANACONDOPS: # %bb.0: 2370; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -123 2371; RV64XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 2372; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 2373; RV64XVENTANACONDOPS-NEXT: or a0, a0, a2 2374; RV64XVENTANACONDOPS-NEXT: ret 2375; 2376; RV64XTHEADCONDMOV-LABEL: seteq_constant: 2377; RV64XTHEADCONDMOV: # %bb.0: 2378; RV64XTHEADCONDMOV-NEXT: addi a0, a0, -123 2379; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, a2, a0 2380; RV64XTHEADCONDMOV-NEXT: mv a0, a1 2381; RV64XTHEADCONDMOV-NEXT: ret 2382; 2383; RV32ZICOND-LABEL: seteq_constant: 2384; RV32ZICOND: # %bb.0: 2385; RV32ZICOND-NEXT: xori a0, a0, 123 2386; RV32ZICOND-NEXT: or a0, a0, a1 2387; RV32ZICOND-NEXT: czero.eqz a1, a4, a0 2388; RV32ZICOND-NEXT: czero.nez a2, a2, a0 2389; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 2390; RV32ZICOND-NEXT: czero.nez a3, a3, a0 2391; RV32ZICOND-NEXT: or a0, a2, a1 2392; RV32ZICOND-NEXT: or a1, a3, a4 2393; RV32ZICOND-NEXT: ret 2394; 2395; RV64ZICOND-LABEL: seteq_constant: 2396; RV64ZICOND: # %bb.0: 2397; RV64ZICOND-NEXT: addi a0, a0, -123 2398; RV64ZICOND-NEXT: czero.eqz a2, a2, a0 2399; RV64ZICOND-NEXT: czero.nez a0, a1, a0 2400; RV64ZICOND-NEXT: or a0, a0, a2 2401; RV64ZICOND-NEXT: ret 2402 %rc = icmp eq i64 %a, 123 2403 %sel = select i1 %rc, i64 %rs1, i64 %rs2 2404 ret i64 %sel 2405} 2406 2407define i64 @setne_constant(i64 %a, i64 %rs1, i64 %rs2) { 2408; RV32I-LABEL: setne_constant: 2409; RV32I: # %bb.0: 2410; RV32I-NEXT: xori a0, a0, 456 2411; RV32I-NEXT: or a1, a0, a1 2412; RV32I-NEXT: mv a0, a2 2413; RV32I-NEXT: bnez a1, .LBB36_2 2414; RV32I-NEXT: # %bb.1: 2415; RV32I-NEXT: mv a0, a4 2416; RV32I-NEXT: mv a3, a5 2417; RV32I-NEXT: .LBB36_2: 2418; RV32I-NEXT: mv a1, a3 2419; RV32I-NEXT: ret 2420; 2421; RV64I-LABEL: setne_constant: 2422; RV64I: # %bb.0: 2423; RV64I-NEXT: li a3, 456 2424; RV64I-NEXT: bne a0, a3, .LBB36_2 2425; RV64I-NEXT: # %bb.1: 2426; RV64I-NEXT: mv a1, a2 2427; RV64I-NEXT: .LBB36_2: 2428; RV64I-NEXT: mv a0, a1 2429; RV64I-NEXT: ret 2430; 2431; RV32XVENTANACONDOPS-LABEL: setne_constant: 2432; RV32XVENTANACONDOPS: # %bb.0: 2433; RV32XVENTANACONDOPS-NEXT: xori a0, a0, 456 2434; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 2435; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a4, a0 2436; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 2437; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a0 2438; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a0 2439; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 2440; RV32XVENTANACONDOPS-NEXT: or a1, a3, a4 2441; RV32XVENTANACONDOPS-NEXT: ret 2442; 2443; RV64XVENTANACONDOPS-LABEL: setne_constant: 2444; RV64XVENTANACONDOPS: # %bb.0: 2445; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -456 2446; RV64XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 2447; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 2448; RV64XVENTANACONDOPS-NEXT: or a0, a0, a2 2449; RV64XVENTANACONDOPS-NEXT: ret 2450; 2451; RV64XTHEADCONDMOV-LABEL: setne_constant: 2452; RV64XTHEADCONDMOV: # %bb.0: 2453; RV64XTHEADCONDMOV-NEXT: addi a0, a0, -456 2454; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, a2, a0 2455; RV64XTHEADCONDMOV-NEXT: mv a0, a1 2456; RV64XTHEADCONDMOV-NEXT: ret 2457; 2458; RV32ZICOND-LABEL: setne_constant: 2459; RV32ZICOND: # %bb.0: 2460; RV32ZICOND-NEXT: xori a0, a0, 456 2461; RV32ZICOND-NEXT: or a0, a0, a1 2462; RV32ZICOND-NEXT: czero.nez a1, a4, a0 2463; RV32ZICOND-NEXT: czero.eqz a2, a2, a0 2464; RV32ZICOND-NEXT: czero.nez a4, a5, a0 2465; RV32ZICOND-NEXT: czero.eqz a3, a3, a0 2466; RV32ZICOND-NEXT: or a0, a2, a1 2467; RV32ZICOND-NEXT: or a1, a3, a4 2468; RV32ZICOND-NEXT: ret 2469; 2470; RV64ZICOND-LABEL: setne_constant: 2471; RV64ZICOND: # %bb.0: 2472; RV64ZICOND-NEXT: addi a0, a0, -456 2473; RV64ZICOND-NEXT: czero.nez a2, a2, a0 2474; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 2475; RV64ZICOND-NEXT: or a0, a0, a2 2476; RV64ZICOND-NEXT: ret 2477 %rc = icmp ne i64 %a, 456 2478 %sel = select i1 %rc, i64 %rs1, i64 %rs2 2479 ret i64 %sel 2480} 2481 2482define i64 @seteq_2048(i64 %a, i64 %rs1, i64 %rs2) { 2483; RV32I-LABEL: seteq_2048: 2484; RV32I: # %bb.0: 2485; RV32I-NEXT: binvi a0, a0, 11 2486; RV32I-NEXT: or a1, a0, a1 2487; RV32I-NEXT: mv a0, a2 2488; RV32I-NEXT: beqz a1, .LBB37_2 2489; RV32I-NEXT: # %bb.1: 2490; RV32I-NEXT: mv a0, a4 2491; RV32I-NEXT: mv a3, a5 2492; RV32I-NEXT: .LBB37_2: 2493; RV32I-NEXT: mv a1, a3 2494; RV32I-NEXT: ret 2495; 2496; RV64I-LABEL: seteq_2048: 2497; RV64I: # %bb.0: 2498; RV64I-NEXT: bseti a3, zero, 11 2499; RV64I-NEXT: beq a0, a3, .LBB37_2 2500; RV64I-NEXT: # %bb.1: 2501; RV64I-NEXT: mv a1, a2 2502; RV64I-NEXT: .LBB37_2: 2503; RV64I-NEXT: mv a0, a1 2504; RV64I-NEXT: ret 2505; 2506; RV32XVENTANACONDOPS-LABEL: seteq_2048: 2507; RV32XVENTANACONDOPS: # %bb.0: 2508; RV32XVENTANACONDOPS-NEXT: binvi a0, a0, 11 2509; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 2510; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a4, a0 2511; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 2512; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 2513; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0 2514; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 2515; RV32XVENTANACONDOPS-NEXT: or a1, a3, a4 2516; RV32XVENTANACONDOPS-NEXT: ret 2517; 2518; RV64XVENTANACONDOPS-LABEL: seteq_2048: 2519; RV64XVENTANACONDOPS: # %bb.0: 2520; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -2048 2521; RV64XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 2522; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 2523; RV64XVENTANACONDOPS-NEXT: or a0, a0, a2 2524; RV64XVENTANACONDOPS-NEXT: ret 2525; 2526; RV64XTHEADCONDMOV-LABEL: seteq_2048: 2527; RV64XTHEADCONDMOV: # %bb.0: 2528; RV64XTHEADCONDMOV-NEXT: addi a0, a0, -2048 2529; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, a2, a0 2530; RV64XTHEADCONDMOV-NEXT: mv a0, a1 2531; RV64XTHEADCONDMOV-NEXT: ret 2532; 2533; RV32ZICOND-LABEL: seteq_2048: 2534; RV32ZICOND: # %bb.0: 2535; RV32ZICOND-NEXT: binvi a0, a0, 11 2536; RV32ZICOND-NEXT: or a0, a0, a1 2537; RV32ZICOND-NEXT: czero.eqz a1, a4, a0 2538; RV32ZICOND-NEXT: czero.nez a2, a2, a0 2539; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 2540; RV32ZICOND-NEXT: czero.nez a3, a3, a0 2541; RV32ZICOND-NEXT: or a0, a2, a1 2542; RV32ZICOND-NEXT: or a1, a3, a4 2543; RV32ZICOND-NEXT: ret 2544; 2545; RV64ZICOND-LABEL: seteq_2048: 2546; RV64ZICOND: # %bb.0: 2547; RV64ZICOND-NEXT: addi a0, a0, -2048 2548; RV64ZICOND-NEXT: czero.eqz a2, a2, a0 2549; RV64ZICOND-NEXT: czero.nez a0, a1, a0 2550; RV64ZICOND-NEXT: or a0, a0, a2 2551; RV64ZICOND-NEXT: ret 2552 %rc = icmp eq i64 %a, 2048 2553 %sel = select i1 %rc, i64 %rs1, i64 %rs2 2554 ret i64 %sel 2555} 2556 2557define i64 @seteq_neg2048(i64 %a, i64 %rs1, i64 %rs2) { 2558; RV32I-LABEL: seteq_neg2048: 2559; RV32I: # %bb.0: 2560; RV32I-NEXT: not a1, a1 2561; RV32I-NEXT: xori a0, a0, -2048 2562; RV32I-NEXT: or a1, a0, a1 2563; RV32I-NEXT: mv a0, a2 2564; RV32I-NEXT: beqz a1, .LBB38_2 2565; RV32I-NEXT: # %bb.1: 2566; RV32I-NEXT: mv a0, a4 2567; RV32I-NEXT: mv a3, a5 2568; RV32I-NEXT: .LBB38_2: 2569; RV32I-NEXT: mv a1, a3 2570; RV32I-NEXT: ret 2571; 2572; RV64I-LABEL: seteq_neg2048: 2573; RV64I: # %bb.0: 2574; RV64I-NEXT: li a3, -2048 2575; RV64I-NEXT: beq a0, a3, .LBB38_2 2576; RV64I-NEXT: # %bb.1: 2577; RV64I-NEXT: mv a1, a2 2578; RV64I-NEXT: .LBB38_2: 2579; RV64I-NEXT: mv a0, a1 2580; RV64I-NEXT: ret 2581; 2582; RV32XVENTANACONDOPS-LABEL: seteq_neg2048: 2583; RV32XVENTANACONDOPS: # %bb.0: 2584; RV32XVENTANACONDOPS-NEXT: not a1, a1 2585; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -2048 2586; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 2587; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a4, a0 2588; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 2589; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 2590; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0 2591; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 2592; RV32XVENTANACONDOPS-NEXT: or a1, a3, a4 2593; RV32XVENTANACONDOPS-NEXT: ret 2594; 2595; RV64XVENTANACONDOPS-LABEL: seteq_neg2048: 2596; RV64XVENTANACONDOPS: # %bb.0: 2597; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -2048 2598; RV64XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 2599; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 2600; RV64XVENTANACONDOPS-NEXT: or a0, a0, a2 2601; RV64XVENTANACONDOPS-NEXT: ret 2602; 2603; RV64XTHEADCONDMOV-LABEL: seteq_neg2048: 2604; RV64XTHEADCONDMOV: # %bb.0: 2605; RV64XTHEADCONDMOV-NEXT: xori a0, a0, -2048 2606; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, a2, a0 2607; RV64XTHEADCONDMOV-NEXT: mv a0, a1 2608; RV64XTHEADCONDMOV-NEXT: ret 2609; 2610; RV32ZICOND-LABEL: seteq_neg2048: 2611; RV32ZICOND: # %bb.0: 2612; RV32ZICOND-NEXT: not a1, a1 2613; RV32ZICOND-NEXT: xori a0, a0, -2048 2614; RV32ZICOND-NEXT: or a0, a0, a1 2615; RV32ZICOND-NEXT: czero.eqz a1, a4, a0 2616; RV32ZICOND-NEXT: czero.nez a2, a2, a0 2617; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 2618; RV32ZICOND-NEXT: czero.nez a3, a3, a0 2619; RV32ZICOND-NEXT: or a0, a2, a1 2620; RV32ZICOND-NEXT: or a1, a3, a4 2621; RV32ZICOND-NEXT: ret 2622; 2623; RV64ZICOND-LABEL: seteq_neg2048: 2624; RV64ZICOND: # %bb.0: 2625; RV64ZICOND-NEXT: xori a0, a0, -2048 2626; RV64ZICOND-NEXT: czero.eqz a2, a2, a0 2627; RV64ZICOND-NEXT: czero.nez a0, a1, a0 2628; RV64ZICOND-NEXT: or a0, a0, a2 2629; RV64ZICOND-NEXT: ret 2630 %rc = icmp eq i64 %a, -2048 2631 %sel = select i1 %rc, i64 %rs1, i64 %rs2 2632 ret i64 %sel 2633} 2634 2635define i64 @setne_neg2048(i64 %a, i64 %rs1, i64 %rs2) { 2636; RV32I-LABEL: setne_neg2048: 2637; RV32I: # %bb.0: 2638; RV32I-NEXT: not a1, a1 2639; RV32I-NEXT: xori a0, a0, -2048 2640; RV32I-NEXT: or a1, a0, a1 2641; RV32I-NEXT: mv a0, a2 2642; RV32I-NEXT: bnez a1, .LBB39_2 2643; RV32I-NEXT: # %bb.1: 2644; RV32I-NEXT: mv a0, a4 2645; RV32I-NEXT: mv a3, a5 2646; RV32I-NEXT: .LBB39_2: 2647; RV32I-NEXT: mv a1, a3 2648; RV32I-NEXT: ret 2649; 2650; RV64I-LABEL: setne_neg2048: 2651; RV64I: # %bb.0: 2652; RV64I-NEXT: li a3, -2048 2653; RV64I-NEXT: bne a0, a3, .LBB39_2 2654; RV64I-NEXT: # %bb.1: 2655; RV64I-NEXT: mv a1, a2 2656; RV64I-NEXT: .LBB39_2: 2657; RV64I-NEXT: mv a0, a1 2658; RV64I-NEXT: ret 2659; 2660; RV32XVENTANACONDOPS-LABEL: setne_neg2048: 2661; RV32XVENTANACONDOPS: # %bb.0: 2662; RV32XVENTANACONDOPS-NEXT: not a1, a1 2663; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -2048 2664; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 2665; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a4, a0 2666; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 2667; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a0 2668; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a0 2669; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 2670; RV32XVENTANACONDOPS-NEXT: or a1, a3, a4 2671; RV32XVENTANACONDOPS-NEXT: ret 2672; 2673; RV64XVENTANACONDOPS-LABEL: setne_neg2048: 2674; RV64XVENTANACONDOPS: # %bb.0: 2675; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -2048 2676; RV64XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 2677; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 2678; RV64XVENTANACONDOPS-NEXT: or a0, a0, a2 2679; RV64XVENTANACONDOPS-NEXT: ret 2680; 2681; RV64XTHEADCONDMOV-LABEL: setne_neg2048: 2682; RV64XTHEADCONDMOV: # %bb.0: 2683; RV64XTHEADCONDMOV-NEXT: xori a0, a0, -2048 2684; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, a2, a0 2685; RV64XTHEADCONDMOV-NEXT: mv a0, a1 2686; RV64XTHEADCONDMOV-NEXT: ret 2687; 2688; RV32ZICOND-LABEL: setne_neg2048: 2689; RV32ZICOND: # %bb.0: 2690; RV32ZICOND-NEXT: not a1, a1 2691; RV32ZICOND-NEXT: xori a0, a0, -2048 2692; RV32ZICOND-NEXT: or a0, a0, a1 2693; RV32ZICOND-NEXT: czero.nez a1, a4, a0 2694; RV32ZICOND-NEXT: czero.eqz a2, a2, a0 2695; RV32ZICOND-NEXT: czero.nez a4, a5, a0 2696; RV32ZICOND-NEXT: czero.eqz a3, a3, a0 2697; RV32ZICOND-NEXT: or a0, a2, a1 2698; RV32ZICOND-NEXT: or a1, a3, a4 2699; RV32ZICOND-NEXT: ret 2700; 2701; RV64ZICOND-LABEL: setne_neg2048: 2702; RV64ZICOND: # %bb.0: 2703; RV64ZICOND-NEXT: xori a0, a0, -2048 2704; RV64ZICOND-NEXT: czero.nez a2, a2, a0 2705; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 2706; RV64ZICOND-NEXT: or a0, a0, a2 2707; RV64ZICOND-NEXT: ret 2708 %rc = icmp ne i64 %a, -2048 2709 %sel = select i1 %rc, i64 %rs1, i64 %rs2 2710 ret i64 %sel 2711} 2712 2713define i64 @zero1_seteq(i64 %a, i64 %b, i64 %rs1) { 2714; RV32I-LABEL: zero1_seteq: 2715; RV32I: # %bb.0: 2716; RV32I-NEXT: xor a1, a1, a3 2717; RV32I-NEXT: xor a0, a0, a2 2718; RV32I-NEXT: or a0, a0, a1 2719; RV32I-NEXT: snez a0, a0 2720; RV32I-NEXT: addi a1, a0, -1 2721; RV32I-NEXT: and a0, a1, a4 2722; RV32I-NEXT: and a1, a1, a5 2723; RV32I-NEXT: ret 2724; 2725; RV64I-LABEL: zero1_seteq: 2726; RV64I: # %bb.0: 2727; RV64I-NEXT: xor a0, a0, a1 2728; RV64I-NEXT: snez a0, a0 2729; RV64I-NEXT: addi a0, a0, -1 2730; RV64I-NEXT: and a0, a0, a2 2731; RV64I-NEXT: ret 2732; 2733; RV32XVENTANACONDOPS-LABEL: zero1_seteq: 2734; RV32XVENTANACONDOPS: # %bb.0: 2735; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a3 2736; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a2 2737; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1 2738; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a4, a1 2739; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a5, a1 2740; RV32XVENTANACONDOPS-NEXT: ret 2741; 2742; RV64XVENTANACONDOPS-LABEL: zero1_seteq: 2743; RV64XVENTANACONDOPS: # %bb.0: 2744; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a1 2745; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 2746; RV64XVENTANACONDOPS-NEXT: ret 2747; 2748; RV64XTHEADCONDMOV-LABEL: zero1_seteq: 2749; RV64XTHEADCONDMOV: # %bb.0: 2750; RV64XTHEADCONDMOV-NEXT: xor a0, a0, a1 2751; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, zero, a0 2752; RV64XTHEADCONDMOV-NEXT: mv a0, a2 2753; RV64XTHEADCONDMOV-NEXT: ret 2754; 2755; RV32ZICOND-LABEL: zero1_seteq: 2756; RV32ZICOND: # %bb.0: 2757; RV32ZICOND-NEXT: xor a1, a1, a3 2758; RV32ZICOND-NEXT: xor a0, a0, a2 2759; RV32ZICOND-NEXT: or a1, a0, a1 2760; RV32ZICOND-NEXT: czero.nez a0, a4, a1 2761; RV32ZICOND-NEXT: czero.nez a1, a5, a1 2762; RV32ZICOND-NEXT: ret 2763; 2764; RV64ZICOND-LABEL: zero1_seteq: 2765; RV64ZICOND: # %bb.0: 2766; RV64ZICOND-NEXT: xor a0, a0, a1 2767; RV64ZICOND-NEXT: czero.nez a0, a2, a0 2768; RV64ZICOND-NEXT: ret 2769 %rc = icmp eq i64 %a, %b 2770 %sel = select i1 %rc, i64 %rs1, i64 0 2771 ret i64 %sel 2772} 2773 2774define i64 @zero2_seteq(i64 %a, i64 %b, i64 %rs1) { 2775; RV32I-LABEL: zero2_seteq: 2776; RV32I: # %bb.0: 2777; RV32I-NEXT: xor a1, a1, a3 2778; RV32I-NEXT: xor a0, a0, a2 2779; RV32I-NEXT: or a0, a0, a1 2780; RV32I-NEXT: seqz a0, a0 2781; RV32I-NEXT: addi a1, a0, -1 2782; RV32I-NEXT: and a0, a1, a4 2783; RV32I-NEXT: and a1, a1, a5 2784; RV32I-NEXT: ret 2785; 2786; RV64I-LABEL: zero2_seteq: 2787; RV64I: # %bb.0: 2788; RV64I-NEXT: xor a0, a0, a1 2789; RV64I-NEXT: seqz a0, a0 2790; RV64I-NEXT: addi a0, a0, -1 2791; RV64I-NEXT: and a0, a0, a2 2792; RV64I-NEXT: ret 2793; 2794; RV32XVENTANACONDOPS-LABEL: zero2_seteq: 2795; RV32XVENTANACONDOPS: # %bb.0: 2796; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a3 2797; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a2 2798; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1 2799; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a4, a1 2800; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a5, a1 2801; RV32XVENTANACONDOPS-NEXT: ret 2802; 2803; RV64XVENTANACONDOPS-LABEL: zero2_seteq: 2804; RV64XVENTANACONDOPS: # %bb.0: 2805; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a1 2806; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0 2807; RV64XVENTANACONDOPS-NEXT: ret 2808; 2809; RV64XTHEADCONDMOV-LABEL: zero2_seteq: 2810; RV64XTHEADCONDMOV: # %bb.0: 2811; RV64XTHEADCONDMOV-NEXT: xor a0, a0, a1 2812; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, zero, a0 2813; RV64XTHEADCONDMOV-NEXT: mv a0, a2 2814; RV64XTHEADCONDMOV-NEXT: ret 2815; 2816; RV32ZICOND-LABEL: zero2_seteq: 2817; RV32ZICOND: # %bb.0: 2818; RV32ZICOND-NEXT: xor a1, a1, a3 2819; RV32ZICOND-NEXT: xor a0, a0, a2 2820; RV32ZICOND-NEXT: or a1, a0, a1 2821; RV32ZICOND-NEXT: czero.eqz a0, a4, a1 2822; RV32ZICOND-NEXT: czero.eqz a1, a5, a1 2823; RV32ZICOND-NEXT: ret 2824; 2825; RV64ZICOND-LABEL: zero2_seteq: 2826; RV64ZICOND: # %bb.0: 2827; RV64ZICOND-NEXT: xor a0, a0, a1 2828; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 2829; RV64ZICOND-NEXT: ret 2830 %rc = icmp eq i64 %a, %b 2831 %sel = select i1 %rc, i64 0, i64 %rs1 2832 ret i64 %sel 2833} 2834 2835define i64 @zero1_setne(i64 %a, i64 %b, i64 %rs1) { 2836; RV32I-LABEL: zero1_setne: 2837; RV32I: # %bb.0: 2838; RV32I-NEXT: xor a1, a1, a3 2839; RV32I-NEXT: xor a0, a0, a2 2840; RV32I-NEXT: or a0, a0, a1 2841; RV32I-NEXT: seqz a0, a0 2842; RV32I-NEXT: addi a1, a0, -1 2843; RV32I-NEXT: and a0, a1, a4 2844; RV32I-NEXT: and a1, a1, a5 2845; RV32I-NEXT: ret 2846; 2847; RV64I-LABEL: zero1_setne: 2848; RV64I: # %bb.0: 2849; RV64I-NEXT: xor a0, a0, a1 2850; RV64I-NEXT: seqz a0, a0 2851; RV64I-NEXT: addi a0, a0, -1 2852; RV64I-NEXT: and a0, a0, a2 2853; RV64I-NEXT: ret 2854; 2855; RV32XVENTANACONDOPS-LABEL: zero1_setne: 2856; RV32XVENTANACONDOPS: # %bb.0: 2857; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a3 2858; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a2 2859; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1 2860; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a4, a1 2861; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a5, a1 2862; RV32XVENTANACONDOPS-NEXT: ret 2863; 2864; RV64XVENTANACONDOPS-LABEL: zero1_setne: 2865; RV64XVENTANACONDOPS: # %bb.0: 2866; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a1 2867; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0 2868; RV64XVENTANACONDOPS-NEXT: ret 2869; 2870; RV64XTHEADCONDMOV-LABEL: zero1_setne: 2871; RV64XTHEADCONDMOV: # %bb.0: 2872; RV64XTHEADCONDMOV-NEXT: xor a0, a0, a1 2873; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, zero, a0 2874; RV64XTHEADCONDMOV-NEXT: mv a0, a2 2875; RV64XTHEADCONDMOV-NEXT: ret 2876; 2877; RV32ZICOND-LABEL: zero1_setne: 2878; RV32ZICOND: # %bb.0: 2879; RV32ZICOND-NEXT: xor a1, a1, a3 2880; RV32ZICOND-NEXT: xor a0, a0, a2 2881; RV32ZICOND-NEXT: or a1, a0, a1 2882; RV32ZICOND-NEXT: czero.eqz a0, a4, a1 2883; RV32ZICOND-NEXT: czero.eqz a1, a5, a1 2884; RV32ZICOND-NEXT: ret 2885; 2886; RV64ZICOND-LABEL: zero1_setne: 2887; RV64ZICOND: # %bb.0: 2888; RV64ZICOND-NEXT: xor a0, a0, a1 2889; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 2890; RV64ZICOND-NEXT: ret 2891 %rc = icmp ne i64 %a, %b 2892 %sel = select i1 %rc, i64 %rs1, i64 0 2893 ret i64 %sel 2894} 2895 2896define i64 @zero2_setne(i64 %a, i64 %b, i64 %rs1) { 2897; RV32I-LABEL: zero2_setne: 2898; RV32I: # %bb.0: 2899; RV32I-NEXT: xor a1, a1, a3 2900; RV32I-NEXT: xor a0, a0, a2 2901; RV32I-NEXT: or a0, a0, a1 2902; RV32I-NEXT: snez a0, a0 2903; RV32I-NEXT: addi a1, a0, -1 2904; RV32I-NEXT: and a0, a1, a4 2905; RV32I-NEXT: and a1, a1, a5 2906; RV32I-NEXT: ret 2907; 2908; RV64I-LABEL: zero2_setne: 2909; RV64I: # %bb.0: 2910; RV64I-NEXT: xor a0, a0, a1 2911; RV64I-NEXT: snez a0, a0 2912; RV64I-NEXT: addi a0, a0, -1 2913; RV64I-NEXT: and a0, a0, a2 2914; RV64I-NEXT: ret 2915; 2916; RV32XVENTANACONDOPS-LABEL: zero2_setne: 2917; RV32XVENTANACONDOPS: # %bb.0: 2918; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a3 2919; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a2 2920; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1 2921; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a4, a1 2922; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a5, a1 2923; RV32XVENTANACONDOPS-NEXT: ret 2924; 2925; RV64XVENTANACONDOPS-LABEL: zero2_setne: 2926; RV64XVENTANACONDOPS: # %bb.0: 2927; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a1 2928; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 2929; RV64XVENTANACONDOPS-NEXT: ret 2930; 2931; RV64XTHEADCONDMOV-LABEL: zero2_setne: 2932; RV64XTHEADCONDMOV: # %bb.0: 2933; RV64XTHEADCONDMOV-NEXT: xor a0, a0, a1 2934; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, zero, a0 2935; RV64XTHEADCONDMOV-NEXT: mv a0, a2 2936; RV64XTHEADCONDMOV-NEXT: ret 2937; 2938; RV32ZICOND-LABEL: zero2_setne: 2939; RV32ZICOND: # %bb.0: 2940; RV32ZICOND-NEXT: xor a1, a1, a3 2941; RV32ZICOND-NEXT: xor a0, a0, a2 2942; RV32ZICOND-NEXT: or a1, a0, a1 2943; RV32ZICOND-NEXT: czero.nez a0, a4, a1 2944; RV32ZICOND-NEXT: czero.nez a1, a5, a1 2945; RV32ZICOND-NEXT: ret 2946; 2947; RV64ZICOND-LABEL: zero2_setne: 2948; RV64ZICOND: # %bb.0: 2949; RV64ZICOND-NEXT: xor a0, a0, a1 2950; RV64ZICOND-NEXT: czero.nez a0, a2, a0 2951; RV64ZICOND-NEXT: ret 2952 %rc = icmp ne i64 %a, %b 2953 %sel = select i1 %rc, i64 0, i64 %rs1 2954 ret i64 %sel 2955} 2956 2957define i64 @zero1_seteq_zero(i64 %a, i64 %rs1) { 2958; RV32I-LABEL: zero1_seteq_zero: 2959; RV32I: # %bb.0: 2960; RV32I-NEXT: or a0, a0, a1 2961; RV32I-NEXT: snez a0, a0 2962; RV32I-NEXT: addi a1, a0, -1 2963; RV32I-NEXT: and a0, a1, a2 2964; RV32I-NEXT: and a1, a1, a3 2965; RV32I-NEXT: ret 2966; 2967; RV64I-LABEL: zero1_seteq_zero: 2968; RV64I: # %bb.0: 2969; RV64I-NEXT: snez a0, a0 2970; RV64I-NEXT: addi a0, a0, -1 2971; RV64I-NEXT: and a0, a0, a1 2972; RV64I-NEXT: ret 2973; 2974; RV32XVENTANACONDOPS-LABEL: zero1_seteq_zero: 2975; RV32XVENTANACONDOPS: # %bb.0: 2976; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1 2977; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a1 2978; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a1 2979; RV32XVENTANACONDOPS-NEXT: ret 2980; 2981; RV64XVENTANACONDOPS-LABEL: zero1_seteq_zero: 2982; RV64XVENTANACONDOPS: # %bb.0: 2983; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 2984; RV64XVENTANACONDOPS-NEXT: ret 2985; 2986; RV64XTHEADCONDMOV-LABEL: zero1_seteq_zero: 2987; RV64XTHEADCONDMOV: # %bb.0: 2988; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a0 2989; RV64XTHEADCONDMOV-NEXT: mv a0, a1 2990; RV64XTHEADCONDMOV-NEXT: ret 2991; 2992; RV32ZICOND-LABEL: zero1_seteq_zero: 2993; RV32ZICOND: # %bb.0: 2994; RV32ZICOND-NEXT: or a1, a0, a1 2995; RV32ZICOND-NEXT: czero.nez a0, a2, a1 2996; RV32ZICOND-NEXT: czero.nez a1, a3, a1 2997; RV32ZICOND-NEXT: ret 2998; 2999; RV64ZICOND-LABEL: zero1_seteq_zero: 3000; RV64ZICOND: # %bb.0: 3001; RV64ZICOND-NEXT: czero.nez a0, a1, a0 3002; RV64ZICOND-NEXT: ret 3003 %rc = icmp eq i64 %a, 0 3004 %sel = select i1 %rc, i64 %rs1, i64 0 3005 ret i64 %sel 3006} 3007 3008define i64 @zero2_seteq_zero(i64 %a, i64 %rs1) { 3009; RV32I-LABEL: zero2_seteq_zero: 3010; RV32I: # %bb.0: 3011; RV32I-NEXT: or a0, a0, a1 3012; RV32I-NEXT: seqz a0, a0 3013; RV32I-NEXT: addi a1, a0, -1 3014; RV32I-NEXT: and a0, a1, a2 3015; RV32I-NEXT: and a1, a1, a3 3016; RV32I-NEXT: ret 3017; 3018; RV64I-LABEL: zero2_seteq_zero: 3019; RV64I: # %bb.0: 3020; RV64I-NEXT: seqz a0, a0 3021; RV64I-NEXT: addi a0, a0, -1 3022; RV64I-NEXT: and a0, a0, a1 3023; RV64I-NEXT: ret 3024; 3025; RV32XVENTANACONDOPS-LABEL: zero2_seteq_zero: 3026; RV32XVENTANACONDOPS: # %bb.0: 3027; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1 3028; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a1 3029; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a1 3030; RV32XVENTANACONDOPS-NEXT: ret 3031; 3032; RV64XVENTANACONDOPS-LABEL: zero2_seteq_zero: 3033; RV64XVENTANACONDOPS: # %bb.0: 3034; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 3035; RV64XVENTANACONDOPS-NEXT: ret 3036; 3037; RV64XTHEADCONDMOV-LABEL: zero2_seteq_zero: 3038; RV64XTHEADCONDMOV: # %bb.0: 3039; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a0 3040; RV64XTHEADCONDMOV-NEXT: mv a0, a1 3041; RV64XTHEADCONDMOV-NEXT: ret 3042; 3043; RV32ZICOND-LABEL: zero2_seteq_zero: 3044; RV32ZICOND: # %bb.0: 3045; RV32ZICOND-NEXT: or a1, a0, a1 3046; RV32ZICOND-NEXT: czero.eqz a0, a2, a1 3047; RV32ZICOND-NEXT: czero.eqz a1, a3, a1 3048; RV32ZICOND-NEXT: ret 3049; 3050; RV64ZICOND-LABEL: zero2_seteq_zero: 3051; RV64ZICOND: # %bb.0: 3052; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 3053; RV64ZICOND-NEXT: ret 3054 %rc = icmp eq i64 %a, 0 3055 %sel = select i1 %rc, i64 0, i64 %rs1 3056 ret i64 %sel 3057} 3058 3059define i64 @zero1_setne_zero(i64 %a, i64 %rs1) { 3060; RV32I-LABEL: zero1_setne_zero: 3061; RV32I: # %bb.0: 3062; RV32I-NEXT: or a0, a0, a1 3063; RV32I-NEXT: seqz a0, a0 3064; RV32I-NEXT: addi a1, a0, -1 3065; RV32I-NEXT: and a0, a1, a2 3066; RV32I-NEXT: and a1, a1, a3 3067; RV32I-NEXT: ret 3068; 3069; RV64I-LABEL: zero1_setne_zero: 3070; RV64I: # %bb.0: 3071; RV64I-NEXT: seqz a0, a0 3072; RV64I-NEXT: addi a0, a0, -1 3073; RV64I-NEXT: and a0, a0, a1 3074; RV64I-NEXT: ret 3075; 3076; RV32XVENTANACONDOPS-LABEL: zero1_setne_zero: 3077; RV32XVENTANACONDOPS: # %bb.0: 3078; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1 3079; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a1 3080; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a1 3081; RV32XVENTANACONDOPS-NEXT: ret 3082; 3083; RV64XVENTANACONDOPS-LABEL: zero1_setne_zero: 3084; RV64XVENTANACONDOPS: # %bb.0: 3085; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 3086; RV64XVENTANACONDOPS-NEXT: ret 3087; 3088; RV64XTHEADCONDMOV-LABEL: zero1_setne_zero: 3089; RV64XTHEADCONDMOV: # %bb.0: 3090; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a0 3091; RV64XTHEADCONDMOV-NEXT: mv a0, a1 3092; RV64XTHEADCONDMOV-NEXT: ret 3093; 3094; RV32ZICOND-LABEL: zero1_setne_zero: 3095; RV32ZICOND: # %bb.0: 3096; RV32ZICOND-NEXT: or a1, a0, a1 3097; RV32ZICOND-NEXT: czero.eqz a0, a2, a1 3098; RV32ZICOND-NEXT: czero.eqz a1, a3, a1 3099; RV32ZICOND-NEXT: ret 3100; 3101; RV64ZICOND-LABEL: zero1_setne_zero: 3102; RV64ZICOND: # %bb.0: 3103; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 3104; RV64ZICOND-NEXT: ret 3105 %rc = icmp ne i64 %a, 0 3106 %sel = select i1 %rc, i64 %rs1, i64 0 3107 ret i64 %sel 3108} 3109 3110define i64 @zero2_setne_zero(i64 %a, i64 %rs1) { 3111; RV32I-LABEL: zero2_setne_zero: 3112; RV32I: # %bb.0: 3113; RV32I-NEXT: or a0, a0, a1 3114; RV32I-NEXT: snez a0, a0 3115; RV32I-NEXT: addi a1, a0, -1 3116; RV32I-NEXT: and a0, a1, a2 3117; RV32I-NEXT: and a1, a1, a3 3118; RV32I-NEXT: ret 3119; 3120; RV64I-LABEL: zero2_setne_zero: 3121; RV64I: # %bb.0: 3122; RV64I-NEXT: snez a0, a0 3123; RV64I-NEXT: addi a0, a0, -1 3124; RV64I-NEXT: and a0, a0, a1 3125; RV64I-NEXT: ret 3126; 3127; RV32XVENTANACONDOPS-LABEL: zero2_setne_zero: 3128; RV32XVENTANACONDOPS: # %bb.0: 3129; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1 3130; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a1 3131; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a1 3132; RV32XVENTANACONDOPS-NEXT: ret 3133; 3134; RV64XVENTANACONDOPS-LABEL: zero2_setne_zero: 3135; RV64XVENTANACONDOPS: # %bb.0: 3136; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 3137; RV64XVENTANACONDOPS-NEXT: ret 3138; 3139; RV64XTHEADCONDMOV-LABEL: zero2_setne_zero: 3140; RV64XTHEADCONDMOV: # %bb.0: 3141; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a0 3142; RV64XTHEADCONDMOV-NEXT: mv a0, a1 3143; RV64XTHEADCONDMOV-NEXT: ret 3144; 3145; RV32ZICOND-LABEL: zero2_setne_zero: 3146; RV32ZICOND: # %bb.0: 3147; RV32ZICOND-NEXT: or a1, a0, a1 3148; RV32ZICOND-NEXT: czero.nez a0, a2, a1 3149; RV32ZICOND-NEXT: czero.nez a1, a3, a1 3150; RV32ZICOND-NEXT: ret 3151; 3152; RV64ZICOND-LABEL: zero2_setne_zero: 3153; RV64ZICOND: # %bb.0: 3154; RV64ZICOND-NEXT: czero.nez a0, a1, a0 3155; RV64ZICOND-NEXT: ret 3156 %rc = icmp ne i64 %a, 0 3157 %sel = select i1 %rc, i64 0, i64 %rs1 3158 ret i64 %sel 3159} 3160 3161define i64 @zero1_seteq_constant(i64 %a, i64 %rs1) { 3162; RV32I-LABEL: zero1_seteq_constant: 3163; RV32I: # %bb.0: 3164; RV32I-NEXT: not a1, a1 3165; RV32I-NEXT: xori a0, a0, -231 3166; RV32I-NEXT: or a0, a0, a1 3167; RV32I-NEXT: snez a0, a0 3168; RV32I-NEXT: addi a1, a0, -1 3169; RV32I-NEXT: and a0, a1, a2 3170; RV32I-NEXT: and a1, a1, a3 3171; RV32I-NEXT: ret 3172; 3173; RV64I-LABEL: zero1_seteq_constant: 3174; RV64I: # %bb.0: 3175; RV64I-NEXT: addi a0, a0, 231 3176; RV64I-NEXT: snez a0, a0 3177; RV64I-NEXT: addi a0, a0, -1 3178; RV64I-NEXT: and a0, a0, a1 3179; RV64I-NEXT: ret 3180; 3181; RV32XVENTANACONDOPS-LABEL: zero1_seteq_constant: 3182; RV32XVENTANACONDOPS: # %bb.0: 3183; RV32XVENTANACONDOPS-NEXT: not a1, a1 3184; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -231 3185; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1 3186; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a1 3187; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a1 3188; RV32XVENTANACONDOPS-NEXT: ret 3189; 3190; RV64XVENTANACONDOPS-LABEL: zero1_seteq_constant: 3191; RV64XVENTANACONDOPS: # %bb.0: 3192; RV64XVENTANACONDOPS-NEXT: addi a0, a0, 231 3193; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 3194; RV64XVENTANACONDOPS-NEXT: ret 3195; 3196; RV64XTHEADCONDMOV-LABEL: zero1_seteq_constant: 3197; RV64XTHEADCONDMOV: # %bb.0: 3198; RV64XTHEADCONDMOV-NEXT: addi a0, a0, 231 3199; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a0 3200; RV64XTHEADCONDMOV-NEXT: mv a0, a1 3201; RV64XTHEADCONDMOV-NEXT: ret 3202; 3203; RV32ZICOND-LABEL: zero1_seteq_constant: 3204; RV32ZICOND: # %bb.0: 3205; RV32ZICOND-NEXT: not a1, a1 3206; RV32ZICOND-NEXT: xori a0, a0, -231 3207; RV32ZICOND-NEXT: or a1, a0, a1 3208; RV32ZICOND-NEXT: czero.nez a0, a2, a1 3209; RV32ZICOND-NEXT: czero.nez a1, a3, a1 3210; RV32ZICOND-NEXT: ret 3211; 3212; RV64ZICOND-LABEL: zero1_seteq_constant: 3213; RV64ZICOND: # %bb.0: 3214; RV64ZICOND-NEXT: addi a0, a0, 231 3215; RV64ZICOND-NEXT: czero.nez a0, a1, a0 3216; RV64ZICOND-NEXT: ret 3217 %rc = icmp eq i64 %a, -231 3218 %sel = select i1 %rc, i64 %rs1, i64 0 3219 ret i64 %sel 3220} 3221 3222define i64 @zero2_seteq_constant(i64 %a, i64 %rs1) { 3223; RV32I-LABEL: zero2_seteq_constant: 3224; RV32I: # %bb.0: 3225; RV32I-NEXT: xori a0, a0, 546 3226; RV32I-NEXT: or a0, a0, a1 3227; RV32I-NEXT: seqz a0, a0 3228; RV32I-NEXT: addi a1, a0, -1 3229; RV32I-NEXT: and a0, a1, a2 3230; RV32I-NEXT: and a1, a1, a3 3231; RV32I-NEXT: ret 3232; 3233; RV64I-LABEL: zero2_seteq_constant: 3234; RV64I: # %bb.0: 3235; RV64I-NEXT: addi a0, a0, -546 3236; RV64I-NEXT: seqz a0, a0 3237; RV64I-NEXT: addi a0, a0, -1 3238; RV64I-NEXT: and a0, a0, a1 3239; RV64I-NEXT: ret 3240; 3241; RV32XVENTANACONDOPS-LABEL: zero2_seteq_constant: 3242; RV32XVENTANACONDOPS: # %bb.0: 3243; RV32XVENTANACONDOPS-NEXT: xori a0, a0, 546 3244; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1 3245; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a1 3246; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a1 3247; RV32XVENTANACONDOPS-NEXT: ret 3248; 3249; RV64XVENTANACONDOPS-LABEL: zero2_seteq_constant: 3250; RV64XVENTANACONDOPS: # %bb.0: 3251; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -546 3252; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 3253; RV64XVENTANACONDOPS-NEXT: ret 3254; 3255; RV64XTHEADCONDMOV-LABEL: zero2_seteq_constant: 3256; RV64XTHEADCONDMOV: # %bb.0: 3257; RV64XTHEADCONDMOV-NEXT: addi a0, a0, -546 3258; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a0 3259; RV64XTHEADCONDMOV-NEXT: mv a0, a1 3260; RV64XTHEADCONDMOV-NEXT: ret 3261; 3262; RV32ZICOND-LABEL: zero2_seteq_constant: 3263; RV32ZICOND: # %bb.0: 3264; RV32ZICOND-NEXT: xori a0, a0, 546 3265; RV32ZICOND-NEXT: or a1, a0, a1 3266; RV32ZICOND-NEXT: czero.eqz a0, a2, a1 3267; RV32ZICOND-NEXT: czero.eqz a1, a3, a1 3268; RV32ZICOND-NEXT: ret 3269; 3270; RV64ZICOND-LABEL: zero2_seteq_constant: 3271; RV64ZICOND: # %bb.0: 3272; RV64ZICOND-NEXT: addi a0, a0, -546 3273; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 3274; RV64ZICOND-NEXT: ret 3275 %rc = icmp eq i64 %a, 546 3276 %sel = select i1 %rc, i64 0, i64 %rs1 3277 ret i64 %sel 3278} 3279 3280define i64 @zero1_setne_constant(i64 %a, i64 %rs1) { 3281; RV32I-LABEL: zero1_setne_constant: 3282; RV32I: # %bb.0: 3283; RV32I-NEXT: xori a0, a0, 321 3284; RV32I-NEXT: or a0, a0, a1 3285; RV32I-NEXT: seqz a0, a0 3286; RV32I-NEXT: addi a1, a0, -1 3287; RV32I-NEXT: and a0, a1, a2 3288; RV32I-NEXT: and a1, a1, a3 3289; RV32I-NEXT: ret 3290; 3291; RV64I-LABEL: zero1_setne_constant: 3292; RV64I: # %bb.0: 3293; RV64I-NEXT: addi a0, a0, -321 3294; RV64I-NEXT: seqz a0, a0 3295; RV64I-NEXT: addi a0, a0, -1 3296; RV64I-NEXT: and a0, a0, a1 3297; RV64I-NEXT: ret 3298; 3299; RV32XVENTANACONDOPS-LABEL: zero1_setne_constant: 3300; RV32XVENTANACONDOPS: # %bb.0: 3301; RV32XVENTANACONDOPS-NEXT: xori a0, a0, 321 3302; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1 3303; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a1 3304; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a1 3305; RV32XVENTANACONDOPS-NEXT: ret 3306; 3307; RV64XVENTANACONDOPS-LABEL: zero1_setne_constant: 3308; RV64XVENTANACONDOPS: # %bb.0: 3309; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -321 3310; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 3311; RV64XVENTANACONDOPS-NEXT: ret 3312; 3313; RV64XTHEADCONDMOV-LABEL: zero1_setne_constant: 3314; RV64XTHEADCONDMOV: # %bb.0: 3315; RV64XTHEADCONDMOV-NEXT: addi a0, a0, -321 3316; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a0 3317; RV64XTHEADCONDMOV-NEXT: mv a0, a1 3318; RV64XTHEADCONDMOV-NEXT: ret 3319; 3320; RV32ZICOND-LABEL: zero1_setne_constant: 3321; RV32ZICOND: # %bb.0: 3322; RV32ZICOND-NEXT: xori a0, a0, 321 3323; RV32ZICOND-NEXT: or a1, a0, a1 3324; RV32ZICOND-NEXT: czero.eqz a0, a2, a1 3325; RV32ZICOND-NEXT: czero.eqz a1, a3, a1 3326; RV32ZICOND-NEXT: ret 3327; 3328; RV64ZICOND-LABEL: zero1_setne_constant: 3329; RV64ZICOND: # %bb.0: 3330; RV64ZICOND-NEXT: addi a0, a0, -321 3331; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 3332; RV64ZICOND-NEXT: ret 3333 %rc = icmp ne i64 %a, 321 3334 %sel = select i1 %rc, i64 %rs1, i64 0 3335 ret i64 %sel 3336} 3337 3338define i64 @zero2_setne_constant(i64 %a, i64 %rs1) { 3339; RV32I-LABEL: zero2_setne_constant: 3340; RV32I: # %bb.0: 3341; RV32I-NEXT: not a1, a1 3342; RV32I-NEXT: xori a0, a0, -654 3343; RV32I-NEXT: or a0, a0, a1 3344; RV32I-NEXT: snez a0, a0 3345; RV32I-NEXT: addi a1, a0, -1 3346; RV32I-NEXT: and a0, a1, a2 3347; RV32I-NEXT: and a1, a1, a3 3348; RV32I-NEXT: ret 3349; 3350; RV64I-LABEL: zero2_setne_constant: 3351; RV64I: # %bb.0: 3352; RV64I-NEXT: addi a0, a0, 654 3353; RV64I-NEXT: snez a0, a0 3354; RV64I-NEXT: addi a0, a0, -1 3355; RV64I-NEXT: and a0, a0, a1 3356; RV64I-NEXT: ret 3357; 3358; RV32XVENTANACONDOPS-LABEL: zero2_setne_constant: 3359; RV32XVENTANACONDOPS: # %bb.0: 3360; RV32XVENTANACONDOPS-NEXT: not a1, a1 3361; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -654 3362; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1 3363; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a1 3364; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a1 3365; RV32XVENTANACONDOPS-NEXT: ret 3366; 3367; RV64XVENTANACONDOPS-LABEL: zero2_setne_constant: 3368; RV64XVENTANACONDOPS: # %bb.0: 3369; RV64XVENTANACONDOPS-NEXT: addi a0, a0, 654 3370; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 3371; RV64XVENTANACONDOPS-NEXT: ret 3372; 3373; RV64XTHEADCONDMOV-LABEL: zero2_setne_constant: 3374; RV64XTHEADCONDMOV: # %bb.0: 3375; RV64XTHEADCONDMOV-NEXT: addi a0, a0, 654 3376; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a0 3377; RV64XTHEADCONDMOV-NEXT: mv a0, a1 3378; RV64XTHEADCONDMOV-NEXT: ret 3379; 3380; RV32ZICOND-LABEL: zero2_setne_constant: 3381; RV32ZICOND: # %bb.0: 3382; RV32ZICOND-NEXT: not a1, a1 3383; RV32ZICOND-NEXT: xori a0, a0, -654 3384; RV32ZICOND-NEXT: or a1, a0, a1 3385; RV32ZICOND-NEXT: czero.nez a0, a2, a1 3386; RV32ZICOND-NEXT: czero.nez a1, a3, a1 3387; RV32ZICOND-NEXT: ret 3388; 3389; RV64ZICOND-LABEL: zero2_setne_constant: 3390; RV64ZICOND: # %bb.0: 3391; RV64ZICOND-NEXT: addi a0, a0, 654 3392; RV64ZICOND-NEXT: czero.nez a0, a1, a0 3393; RV64ZICOND-NEXT: ret 3394 %rc = icmp ne i64 %a, -654 3395 %sel = select i1 %rc, i64 0, i64 %rs1 3396 ret i64 %sel 3397} 3398 3399define i64 @zero1_seteq_neg2048(i64 %a, i64 %rs1) { 3400; RV32I-LABEL: zero1_seteq_neg2048: 3401; RV32I: # %bb.0: 3402; RV32I-NEXT: not a1, a1 3403; RV32I-NEXT: xori a0, a0, -2048 3404; RV32I-NEXT: or a0, a0, a1 3405; RV32I-NEXT: snez a0, a0 3406; RV32I-NEXT: addi a1, a0, -1 3407; RV32I-NEXT: and a0, a1, a2 3408; RV32I-NEXT: and a1, a1, a3 3409; RV32I-NEXT: ret 3410; 3411; RV64I-LABEL: zero1_seteq_neg2048: 3412; RV64I: # %bb.0: 3413; RV64I-NEXT: xori a0, a0, -2048 3414; RV64I-NEXT: snez a0, a0 3415; RV64I-NEXT: addi a0, a0, -1 3416; RV64I-NEXT: and a0, a0, a1 3417; RV64I-NEXT: ret 3418; 3419; RV32XVENTANACONDOPS-LABEL: zero1_seteq_neg2048: 3420; RV32XVENTANACONDOPS: # %bb.0: 3421; RV32XVENTANACONDOPS-NEXT: not a1, a1 3422; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -2048 3423; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1 3424; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a1 3425; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a1 3426; RV32XVENTANACONDOPS-NEXT: ret 3427; 3428; RV64XVENTANACONDOPS-LABEL: zero1_seteq_neg2048: 3429; RV64XVENTANACONDOPS: # %bb.0: 3430; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -2048 3431; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 3432; RV64XVENTANACONDOPS-NEXT: ret 3433; 3434; RV64XTHEADCONDMOV-LABEL: zero1_seteq_neg2048: 3435; RV64XTHEADCONDMOV: # %bb.0: 3436; RV64XTHEADCONDMOV-NEXT: xori a0, a0, -2048 3437; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a0 3438; RV64XTHEADCONDMOV-NEXT: mv a0, a1 3439; RV64XTHEADCONDMOV-NEXT: ret 3440; 3441; RV32ZICOND-LABEL: zero1_seteq_neg2048: 3442; RV32ZICOND: # %bb.0: 3443; RV32ZICOND-NEXT: not a1, a1 3444; RV32ZICOND-NEXT: xori a0, a0, -2048 3445; RV32ZICOND-NEXT: or a1, a0, a1 3446; RV32ZICOND-NEXT: czero.nez a0, a2, a1 3447; RV32ZICOND-NEXT: czero.nez a1, a3, a1 3448; RV32ZICOND-NEXT: ret 3449; 3450; RV64ZICOND-LABEL: zero1_seteq_neg2048: 3451; RV64ZICOND: # %bb.0: 3452; RV64ZICOND-NEXT: xori a0, a0, -2048 3453; RV64ZICOND-NEXT: czero.nez a0, a1, a0 3454; RV64ZICOND-NEXT: ret 3455 %rc = icmp eq i64 %a, -2048 3456 %sel = select i1 %rc, i64 %rs1, i64 0 3457 ret i64 %sel 3458} 3459 3460define i64 @zero2_seteq_neg2048(i64 %a, i64 %rs1) { 3461; RV32I-LABEL: zero2_seteq_neg2048: 3462; RV32I: # %bb.0: 3463; RV32I-NEXT: not a1, a1 3464; RV32I-NEXT: xori a0, a0, -2048 3465; RV32I-NEXT: or a0, a0, a1 3466; RV32I-NEXT: seqz a0, a0 3467; RV32I-NEXT: addi a1, a0, -1 3468; RV32I-NEXT: and a0, a1, a2 3469; RV32I-NEXT: and a1, a1, a3 3470; RV32I-NEXT: ret 3471; 3472; RV64I-LABEL: zero2_seteq_neg2048: 3473; RV64I: # %bb.0: 3474; RV64I-NEXT: xori a0, a0, -2048 3475; RV64I-NEXT: seqz a0, a0 3476; RV64I-NEXT: addi a0, a0, -1 3477; RV64I-NEXT: and a0, a0, a1 3478; RV64I-NEXT: ret 3479; 3480; RV32XVENTANACONDOPS-LABEL: zero2_seteq_neg2048: 3481; RV32XVENTANACONDOPS: # %bb.0: 3482; RV32XVENTANACONDOPS-NEXT: not a1, a1 3483; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -2048 3484; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1 3485; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a1 3486; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a1 3487; RV32XVENTANACONDOPS-NEXT: ret 3488; 3489; RV64XVENTANACONDOPS-LABEL: zero2_seteq_neg2048: 3490; RV64XVENTANACONDOPS: # %bb.0: 3491; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -2048 3492; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 3493; RV64XVENTANACONDOPS-NEXT: ret 3494; 3495; RV64XTHEADCONDMOV-LABEL: zero2_seteq_neg2048: 3496; RV64XTHEADCONDMOV: # %bb.0: 3497; RV64XTHEADCONDMOV-NEXT: xori a0, a0, -2048 3498; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a0 3499; RV64XTHEADCONDMOV-NEXT: mv a0, a1 3500; RV64XTHEADCONDMOV-NEXT: ret 3501; 3502; RV32ZICOND-LABEL: zero2_seteq_neg2048: 3503; RV32ZICOND: # %bb.0: 3504; RV32ZICOND-NEXT: not a1, a1 3505; RV32ZICOND-NEXT: xori a0, a0, -2048 3506; RV32ZICOND-NEXT: or a1, a0, a1 3507; RV32ZICOND-NEXT: czero.eqz a0, a2, a1 3508; RV32ZICOND-NEXT: czero.eqz a1, a3, a1 3509; RV32ZICOND-NEXT: ret 3510; 3511; RV64ZICOND-LABEL: zero2_seteq_neg2048: 3512; RV64ZICOND: # %bb.0: 3513; RV64ZICOND-NEXT: xori a0, a0, -2048 3514; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 3515; RV64ZICOND-NEXT: ret 3516 %rc = icmp eq i64 %a, -2048 3517 %sel = select i1 %rc, i64 0, i64 %rs1 3518 ret i64 %sel 3519} 3520 3521define i64 @zero1_setne_neg2048(i64 %a, i64 %rs1) { 3522; RV32I-LABEL: zero1_setne_neg2048: 3523; RV32I: # %bb.0: 3524; RV32I-NEXT: not a1, a1 3525; RV32I-NEXT: xori a0, a0, -2048 3526; RV32I-NEXT: or a0, a0, a1 3527; RV32I-NEXT: seqz a0, a0 3528; RV32I-NEXT: addi a1, a0, -1 3529; RV32I-NEXT: and a0, a1, a2 3530; RV32I-NEXT: and a1, a1, a3 3531; RV32I-NEXT: ret 3532; 3533; RV64I-LABEL: zero1_setne_neg2048: 3534; RV64I: # %bb.0: 3535; RV64I-NEXT: xori a0, a0, -2048 3536; RV64I-NEXT: seqz a0, a0 3537; RV64I-NEXT: addi a0, a0, -1 3538; RV64I-NEXT: and a0, a0, a1 3539; RV64I-NEXT: ret 3540; 3541; RV32XVENTANACONDOPS-LABEL: zero1_setne_neg2048: 3542; RV32XVENTANACONDOPS: # %bb.0: 3543; RV32XVENTANACONDOPS-NEXT: not a1, a1 3544; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -2048 3545; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1 3546; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a1 3547; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a1 3548; RV32XVENTANACONDOPS-NEXT: ret 3549; 3550; RV64XVENTANACONDOPS-LABEL: zero1_setne_neg2048: 3551; RV64XVENTANACONDOPS: # %bb.0: 3552; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -2048 3553; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 3554; RV64XVENTANACONDOPS-NEXT: ret 3555; 3556; RV64XTHEADCONDMOV-LABEL: zero1_setne_neg2048: 3557; RV64XTHEADCONDMOV: # %bb.0: 3558; RV64XTHEADCONDMOV-NEXT: xori a0, a0, -2048 3559; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a0 3560; RV64XTHEADCONDMOV-NEXT: mv a0, a1 3561; RV64XTHEADCONDMOV-NEXT: ret 3562; 3563; RV32ZICOND-LABEL: zero1_setne_neg2048: 3564; RV32ZICOND: # %bb.0: 3565; RV32ZICOND-NEXT: not a1, a1 3566; RV32ZICOND-NEXT: xori a0, a0, -2048 3567; RV32ZICOND-NEXT: or a1, a0, a1 3568; RV32ZICOND-NEXT: czero.eqz a0, a2, a1 3569; RV32ZICOND-NEXT: czero.eqz a1, a3, a1 3570; RV32ZICOND-NEXT: ret 3571; 3572; RV64ZICOND-LABEL: zero1_setne_neg2048: 3573; RV64ZICOND: # %bb.0: 3574; RV64ZICOND-NEXT: xori a0, a0, -2048 3575; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 3576; RV64ZICOND-NEXT: ret 3577 %rc = icmp ne i64 %a, -2048 3578 %sel = select i1 %rc, i64 %rs1, i64 0 3579 ret i64 %sel 3580} 3581 3582define i64 @zero2_setne_neg2048(i64 %a, i64 %rs1) { 3583; RV32I-LABEL: zero2_setne_neg2048: 3584; RV32I: # %bb.0: 3585; RV32I-NEXT: not a1, a1 3586; RV32I-NEXT: xori a0, a0, -2048 3587; RV32I-NEXT: or a0, a0, a1 3588; RV32I-NEXT: snez a0, a0 3589; RV32I-NEXT: addi a1, a0, -1 3590; RV32I-NEXT: and a0, a1, a2 3591; RV32I-NEXT: and a1, a1, a3 3592; RV32I-NEXT: ret 3593; 3594; RV64I-LABEL: zero2_setne_neg2048: 3595; RV64I: # %bb.0: 3596; RV64I-NEXT: xori a0, a0, -2048 3597; RV64I-NEXT: snez a0, a0 3598; RV64I-NEXT: addi a0, a0, -1 3599; RV64I-NEXT: and a0, a0, a1 3600; RV64I-NEXT: ret 3601; 3602; RV32XVENTANACONDOPS-LABEL: zero2_setne_neg2048: 3603; RV32XVENTANACONDOPS: # %bb.0: 3604; RV32XVENTANACONDOPS-NEXT: not a1, a1 3605; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -2048 3606; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1 3607; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a1 3608; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a1 3609; RV32XVENTANACONDOPS-NEXT: ret 3610; 3611; RV64XVENTANACONDOPS-LABEL: zero2_setne_neg2048: 3612; RV64XVENTANACONDOPS: # %bb.0: 3613; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -2048 3614; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 3615; RV64XVENTANACONDOPS-NEXT: ret 3616; 3617; RV64XTHEADCONDMOV-LABEL: zero2_setne_neg2048: 3618; RV64XTHEADCONDMOV: # %bb.0: 3619; RV64XTHEADCONDMOV-NEXT: xori a0, a0, -2048 3620; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a0 3621; RV64XTHEADCONDMOV-NEXT: mv a0, a1 3622; RV64XTHEADCONDMOV-NEXT: ret 3623; 3624; RV32ZICOND-LABEL: zero2_setne_neg2048: 3625; RV32ZICOND: # %bb.0: 3626; RV32ZICOND-NEXT: not a1, a1 3627; RV32ZICOND-NEXT: xori a0, a0, -2048 3628; RV32ZICOND-NEXT: or a1, a0, a1 3629; RV32ZICOND-NEXT: czero.nez a0, a2, a1 3630; RV32ZICOND-NEXT: czero.nez a1, a3, a1 3631; RV32ZICOND-NEXT: ret 3632; 3633; RV64ZICOND-LABEL: zero2_setne_neg2048: 3634; RV64ZICOND: # %bb.0: 3635; RV64ZICOND-NEXT: xori a0, a0, -2048 3636; RV64ZICOND-NEXT: czero.nez a0, a1, a0 3637; RV64ZICOND-NEXT: ret 3638 %rc = icmp ne i64 %a, -2048 3639 %sel = select i1 %rc, i64 0, i64 %rs1 3640 ret i64 %sel 3641} 3642 3643define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nounwind { 3644; RV32I-LABEL: sextw_removal_maskc: 3645; RV32I: # %bb.0: # %bb 3646; RV32I-NEXT: addi sp, sp, -16 3647; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 3648; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 3649; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 3650; RV32I-NEXT: mv s0, a2 3651; RV32I-NEXT: slli a0, a0, 31 3652; RV32I-NEXT: srai a0, a0, 31 3653; RV32I-NEXT: and s1, a0, a1 3654; RV32I-NEXT: .LBB56_1: # %bb2 3655; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 3656; RV32I-NEXT: mv a0, s1 3657; RV32I-NEXT: call bar 3658; RV32I-NEXT: sll s1, s1, s0 3659; RV32I-NEXT: bnez a0, .LBB56_1 3660; RV32I-NEXT: # %bb.2: # %bb7 3661; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 3662; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 3663; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 3664; RV32I-NEXT: addi sp, sp, 16 3665; RV32I-NEXT: ret 3666; 3667; RV64I-LABEL: sextw_removal_maskc: 3668; RV64I: # %bb.0: # %bb 3669; RV64I-NEXT: addi sp, sp, -32 3670; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 3671; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 3672; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 3673; RV64I-NEXT: mv s0, a2 3674; RV64I-NEXT: slli a0, a0, 63 3675; RV64I-NEXT: srai a0, a0, 63 3676; RV64I-NEXT: and s1, a0, a1 3677; RV64I-NEXT: .LBB56_1: # %bb2 3678; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 3679; RV64I-NEXT: mv a0, s1 3680; RV64I-NEXT: call bar 3681; RV64I-NEXT: sllw s1, s1, s0 3682; RV64I-NEXT: bnez a0, .LBB56_1 3683; RV64I-NEXT: # %bb.2: # %bb7 3684; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 3685; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 3686; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 3687; RV64I-NEXT: addi sp, sp, 32 3688; RV64I-NEXT: ret 3689; 3690; RV32XVENTANACONDOPS-LABEL: sextw_removal_maskc: 3691; RV32XVENTANACONDOPS: # %bb.0: # %bb 3692; RV32XVENTANACONDOPS-NEXT: addi sp, sp, -16 3693; RV32XVENTANACONDOPS-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 3694; RV32XVENTANACONDOPS-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 3695; RV32XVENTANACONDOPS-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 3696; RV32XVENTANACONDOPS-NEXT: mv s0, a2 3697; RV32XVENTANACONDOPS-NEXT: andi a0, a0, 1 3698; RV32XVENTANACONDOPS-NEXT: vt.maskc s1, a1, a0 3699; RV32XVENTANACONDOPS-NEXT: .LBB56_1: # %bb2 3700; RV32XVENTANACONDOPS-NEXT: # =>This Inner Loop Header: Depth=1 3701; RV32XVENTANACONDOPS-NEXT: mv a0, s1 3702; RV32XVENTANACONDOPS-NEXT: call bar 3703; RV32XVENTANACONDOPS-NEXT: sll s1, s1, s0 3704; RV32XVENTANACONDOPS-NEXT: bnez a0, .LBB56_1 3705; RV32XVENTANACONDOPS-NEXT: # %bb.2: # %bb7 3706; RV32XVENTANACONDOPS-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 3707; RV32XVENTANACONDOPS-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 3708; RV32XVENTANACONDOPS-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 3709; RV32XVENTANACONDOPS-NEXT: addi sp, sp, 16 3710; RV32XVENTANACONDOPS-NEXT: ret 3711; 3712; RV64XVENTANACONDOPS-LABEL: sextw_removal_maskc: 3713; RV64XVENTANACONDOPS: # %bb.0: # %bb 3714; RV64XVENTANACONDOPS-NEXT: addi sp, sp, -32 3715; RV64XVENTANACONDOPS-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 3716; RV64XVENTANACONDOPS-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 3717; RV64XVENTANACONDOPS-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 3718; RV64XVENTANACONDOPS-NEXT: mv s0, a2 3719; RV64XVENTANACONDOPS-NEXT: andi a0, a0, 1 3720; RV64XVENTANACONDOPS-NEXT: vt.maskc s1, a1, a0 3721; RV64XVENTANACONDOPS-NEXT: .LBB56_1: # %bb2 3722; RV64XVENTANACONDOPS-NEXT: # =>This Inner Loop Header: Depth=1 3723; RV64XVENTANACONDOPS-NEXT: mv a0, s1 3724; RV64XVENTANACONDOPS-NEXT: call bar 3725; RV64XVENTANACONDOPS-NEXT: sllw s1, s1, s0 3726; RV64XVENTANACONDOPS-NEXT: bnez a0, .LBB56_1 3727; RV64XVENTANACONDOPS-NEXT: # %bb.2: # %bb7 3728; RV64XVENTANACONDOPS-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 3729; RV64XVENTANACONDOPS-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 3730; RV64XVENTANACONDOPS-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 3731; RV64XVENTANACONDOPS-NEXT: addi sp, sp, 32 3732; RV64XVENTANACONDOPS-NEXT: ret 3733; 3734; RV64XTHEADCONDMOV-LABEL: sextw_removal_maskc: 3735; RV64XTHEADCONDMOV: # %bb.0: # %bb 3736; RV64XTHEADCONDMOV-NEXT: addi sp, sp, -32 3737; RV64XTHEADCONDMOV-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 3738; RV64XTHEADCONDMOV-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 3739; RV64XTHEADCONDMOV-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 3740; RV64XTHEADCONDMOV-NEXT: mv s0, a2 3741; RV64XTHEADCONDMOV-NEXT: mv s1, a1 3742; RV64XTHEADCONDMOV-NEXT: andi a0, a0, 1 3743; RV64XTHEADCONDMOV-NEXT: th.mveqz s1, zero, a0 3744; RV64XTHEADCONDMOV-NEXT: .LBB56_1: # %bb2 3745; RV64XTHEADCONDMOV-NEXT: # =>This Inner Loop Header: Depth=1 3746; RV64XTHEADCONDMOV-NEXT: sext.w a0, s1 3747; RV64XTHEADCONDMOV-NEXT: call bar 3748; RV64XTHEADCONDMOV-NEXT: sllw s1, s1, s0 3749; RV64XTHEADCONDMOV-NEXT: bnez a0, .LBB56_1 3750; RV64XTHEADCONDMOV-NEXT: # %bb.2: # %bb7 3751; RV64XTHEADCONDMOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 3752; RV64XTHEADCONDMOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 3753; RV64XTHEADCONDMOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 3754; RV64XTHEADCONDMOV-NEXT: addi sp, sp, 32 3755; RV64XTHEADCONDMOV-NEXT: ret 3756; 3757; RV32ZICOND-LABEL: sextw_removal_maskc: 3758; RV32ZICOND: # %bb.0: # %bb 3759; RV32ZICOND-NEXT: addi sp, sp, -16 3760; RV32ZICOND-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 3761; RV32ZICOND-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 3762; RV32ZICOND-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 3763; RV32ZICOND-NEXT: mv s0, a2 3764; RV32ZICOND-NEXT: andi a0, a0, 1 3765; RV32ZICOND-NEXT: czero.eqz s1, a1, a0 3766; RV32ZICOND-NEXT: .LBB56_1: # %bb2 3767; RV32ZICOND-NEXT: # =>This Inner Loop Header: Depth=1 3768; RV32ZICOND-NEXT: mv a0, s1 3769; RV32ZICOND-NEXT: call bar 3770; RV32ZICOND-NEXT: sll s1, s1, s0 3771; RV32ZICOND-NEXT: bnez a0, .LBB56_1 3772; RV32ZICOND-NEXT: # %bb.2: # %bb7 3773; RV32ZICOND-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 3774; RV32ZICOND-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 3775; RV32ZICOND-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 3776; RV32ZICOND-NEXT: addi sp, sp, 16 3777; RV32ZICOND-NEXT: ret 3778; 3779; RV64ZICOND-LABEL: sextw_removal_maskc: 3780; RV64ZICOND: # %bb.0: # %bb 3781; RV64ZICOND-NEXT: addi sp, sp, -32 3782; RV64ZICOND-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 3783; RV64ZICOND-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 3784; RV64ZICOND-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 3785; RV64ZICOND-NEXT: mv s0, a2 3786; RV64ZICOND-NEXT: andi a0, a0, 1 3787; RV64ZICOND-NEXT: czero.eqz s1, a1, a0 3788; RV64ZICOND-NEXT: .LBB56_1: # %bb2 3789; RV64ZICOND-NEXT: # =>This Inner Loop Header: Depth=1 3790; RV64ZICOND-NEXT: mv a0, s1 3791; RV64ZICOND-NEXT: call bar 3792; RV64ZICOND-NEXT: sllw s1, s1, s0 3793; RV64ZICOND-NEXT: bnez a0, .LBB56_1 3794; RV64ZICOND-NEXT: # %bb.2: # %bb7 3795; RV64ZICOND-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 3796; RV64ZICOND-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 3797; RV64ZICOND-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 3798; RV64ZICOND-NEXT: addi sp, sp, 32 3799; RV64ZICOND-NEXT: ret 3800bb: 3801 %i = select i1 %c, i32 %arg, i32 0 3802 br label %bb2 3803 3804bb2: ; preds = %bb2, %bb 3805 %i3 = phi i32 [ %i, %bb ], [ %i5, %bb2 ] 3806 %i4 = tail call signext i32 @bar(i32 signext %i3) 3807 %i5 = shl i32 %i3, %arg1 3808 %i6 = icmp eq i32 %i4, 0 3809 br i1 %i6, label %bb7, label %bb2 3810 3811bb7: ; preds = %bb2 3812 ret void 3813} 3814declare signext i32 @bar(i32 signext) 3815 3816define void @sextw_removal_maskcn(i1 %c, i32 signext %arg, i32 signext %arg1) nounwind { 3817; RV32I-LABEL: sextw_removal_maskcn: 3818; RV32I: # %bb.0: # %bb 3819; RV32I-NEXT: addi sp, sp, -16 3820; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 3821; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 3822; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 3823; RV32I-NEXT: mv s0, a2 3824; RV32I-NEXT: andi a0, a0, 1 3825; RV32I-NEXT: addi a0, a0, -1 3826; RV32I-NEXT: and s1, a0, a1 3827; RV32I-NEXT: .LBB57_1: # %bb2 3828; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 3829; RV32I-NEXT: mv a0, s1 3830; RV32I-NEXT: call bar 3831; RV32I-NEXT: sll s1, s1, s0 3832; RV32I-NEXT: bnez a0, .LBB57_1 3833; RV32I-NEXT: # %bb.2: # %bb7 3834; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 3835; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 3836; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 3837; RV32I-NEXT: addi sp, sp, 16 3838; RV32I-NEXT: ret 3839; 3840; RV64I-LABEL: sextw_removal_maskcn: 3841; RV64I: # %bb.0: # %bb 3842; RV64I-NEXT: addi sp, sp, -32 3843; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 3844; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 3845; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 3846; RV64I-NEXT: mv s0, a2 3847; RV64I-NEXT: andi a0, a0, 1 3848; RV64I-NEXT: addiw a0, a0, -1 3849; RV64I-NEXT: and s1, a0, a1 3850; RV64I-NEXT: .LBB57_1: # %bb2 3851; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 3852; RV64I-NEXT: mv a0, s1 3853; RV64I-NEXT: call bar 3854; RV64I-NEXT: sllw s1, s1, s0 3855; RV64I-NEXT: bnez a0, .LBB57_1 3856; RV64I-NEXT: # %bb.2: # %bb7 3857; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 3858; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 3859; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 3860; RV64I-NEXT: addi sp, sp, 32 3861; RV64I-NEXT: ret 3862; 3863; RV32XVENTANACONDOPS-LABEL: sextw_removal_maskcn: 3864; RV32XVENTANACONDOPS: # %bb.0: # %bb 3865; RV32XVENTANACONDOPS-NEXT: addi sp, sp, -16 3866; RV32XVENTANACONDOPS-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 3867; RV32XVENTANACONDOPS-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 3868; RV32XVENTANACONDOPS-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 3869; RV32XVENTANACONDOPS-NEXT: mv s0, a2 3870; RV32XVENTANACONDOPS-NEXT: andi a0, a0, 1 3871; RV32XVENTANACONDOPS-NEXT: vt.maskcn s1, a1, a0 3872; RV32XVENTANACONDOPS-NEXT: .LBB57_1: # %bb2 3873; RV32XVENTANACONDOPS-NEXT: # =>This Inner Loop Header: Depth=1 3874; RV32XVENTANACONDOPS-NEXT: mv a0, s1 3875; RV32XVENTANACONDOPS-NEXT: call bar 3876; RV32XVENTANACONDOPS-NEXT: sll s1, s1, s0 3877; RV32XVENTANACONDOPS-NEXT: bnez a0, .LBB57_1 3878; RV32XVENTANACONDOPS-NEXT: # %bb.2: # %bb7 3879; RV32XVENTANACONDOPS-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 3880; RV32XVENTANACONDOPS-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 3881; RV32XVENTANACONDOPS-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 3882; RV32XVENTANACONDOPS-NEXT: addi sp, sp, 16 3883; RV32XVENTANACONDOPS-NEXT: ret 3884; 3885; RV64XVENTANACONDOPS-LABEL: sextw_removal_maskcn: 3886; RV64XVENTANACONDOPS: # %bb.0: # %bb 3887; RV64XVENTANACONDOPS-NEXT: addi sp, sp, -32 3888; RV64XVENTANACONDOPS-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 3889; RV64XVENTANACONDOPS-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 3890; RV64XVENTANACONDOPS-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 3891; RV64XVENTANACONDOPS-NEXT: mv s0, a2 3892; RV64XVENTANACONDOPS-NEXT: andi a0, a0, 1 3893; RV64XVENTANACONDOPS-NEXT: vt.maskcn s1, a1, a0 3894; RV64XVENTANACONDOPS-NEXT: .LBB57_1: # %bb2 3895; RV64XVENTANACONDOPS-NEXT: # =>This Inner Loop Header: Depth=1 3896; RV64XVENTANACONDOPS-NEXT: mv a0, s1 3897; RV64XVENTANACONDOPS-NEXT: call bar 3898; RV64XVENTANACONDOPS-NEXT: sllw s1, s1, s0 3899; RV64XVENTANACONDOPS-NEXT: bnez a0, .LBB57_1 3900; RV64XVENTANACONDOPS-NEXT: # %bb.2: # %bb7 3901; RV64XVENTANACONDOPS-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 3902; RV64XVENTANACONDOPS-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 3903; RV64XVENTANACONDOPS-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 3904; RV64XVENTANACONDOPS-NEXT: addi sp, sp, 32 3905; RV64XVENTANACONDOPS-NEXT: ret 3906; 3907; RV64XTHEADCONDMOV-LABEL: sextw_removal_maskcn: 3908; RV64XTHEADCONDMOV: # %bb.0: # %bb 3909; RV64XTHEADCONDMOV-NEXT: addi sp, sp, -32 3910; RV64XTHEADCONDMOV-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 3911; RV64XTHEADCONDMOV-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 3912; RV64XTHEADCONDMOV-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 3913; RV64XTHEADCONDMOV-NEXT: mv s0, a2 3914; RV64XTHEADCONDMOV-NEXT: mv s1, a1 3915; RV64XTHEADCONDMOV-NEXT: andi a0, a0, 1 3916; RV64XTHEADCONDMOV-NEXT: th.mvnez s1, zero, a0 3917; RV64XTHEADCONDMOV-NEXT: .LBB57_1: # %bb2 3918; RV64XTHEADCONDMOV-NEXT: # =>This Inner Loop Header: Depth=1 3919; RV64XTHEADCONDMOV-NEXT: sext.w a0, s1 3920; RV64XTHEADCONDMOV-NEXT: call bar 3921; RV64XTHEADCONDMOV-NEXT: sllw s1, s1, s0 3922; RV64XTHEADCONDMOV-NEXT: bnez a0, .LBB57_1 3923; RV64XTHEADCONDMOV-NEXT: # %bb.2: # %bb7 3924; RV64XTHEADCONDMOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 3925; RV64XTHEADCONDMOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 3926; RV64XTHEADCONDMOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 3927; RV64XTHEADCONDMOV-NEXT: addi sp, sp, 32 3928; RV64XTHEADCONDMOV-NEXT: ret 3929; 3930; RV32ZICOND-LABEL: sextw_removal_maskcn: 3931; RV32ZICOND: # %bb.0: # %bb 3932; RV32ZICOND-NEXT: addi sp, sp, -16 3933; RV32ZICOND-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 3934; RV32ZICOND-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 3935; RV32ZICOND-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 3936; RV32ZICOND-NEXT: mv s0, a2 3937; RV32ZICOND-NEXT: andi a0, a0, 1 3938; RV32ZICOND-NEXT: czero.nez s1, a1, a0 3939; RV32ZICOND-NEXT: .LBB57_1: # %bb2 3940; RV32ZICOND-NEXT: # =>This Inner Loop Header: Depth=1 3941; RV32ZICOND-NEXT: mv a0, s1 3942; RV32ZICOND-NEXT: call bar 3943; RV32ZICOND-NEXT: sll s1, s1, s0 3944; RV32ZICOND-NEXT: bnez a0, .LBB57_1 3945; RV32ZICOND-NEXT: # %bb.2: # %bb7 3946; RV32ZICOND-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 3947; RV32ZICOND-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 3948; RV32ZICOND-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 3949; RV32ZICOND-NEXT: addi sp, sp, 16 3950; RV32ZICOND-NEXT: ret 3951; 3952; RV64ZICOND-LABEL: sextw_removal_maskcn: 3953; RV64ZICOND: # %bb.0: # %bb 3954; RV64ZICOND-NEXT: addi sp, sp, -32 3955; RV64ZICOND-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 3956; RV64ZICOND-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 3957; RV64ZICOND-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 3958; RV64ZICOND-NEXT: mv s0, a2 3959; RV64ZICOND-NEXT: andi a0, a0, 1 3960; RV64ZICOND-NEXT: czero.nez s1, a1, a0 3961; RV64ZICOND-NEXT: .LBB57_1: # %bb2 3962; RV64ZICOND-NEXT: # =>This Inner Loop Header: Depth=1 3963; RV64ZICOND-NEXT: mv a0, s1 3964; RV64ZICOND-NEXT: call bar 3965; RV64ZICOND-NEXT: sllw s1, s1, s0 3966; RV64ZICOND-NEXT: bnez a0, .LBB57_1 3967; RV64ZICOND-NEXT: # %bb.2: # %bb7 3968; RV64ZICOND-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 3969; RV64ZICOND-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 3970; RV64ZICOND-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 3971; RV64ZICOND-NEXT: addi sp, sp, 32 3972; RV64ZICOND-NEXT: ret 3973bb: 3974 %i = select i1 %c, i32 0, i32 %arg 3975 br label %bb2 3976 3977bb2: ; preds = %bb2, %bb 3978 %i3 = phi i32 [ %i, %bb ], [ %i5, %bb2 ] 3979 %i4 = tail call signext i32 @bar(i32 signext %i3) 3980 %i5 = shl i32 %i3, %arg1 3981 %i6 = icmp eq i32 %i4, 0 3982 br i1 %i6, label %bb7, label %bb2 3983 3984bb7: ; preds = %bb2 3985 ret void 3986} 3987 3988define i32 @setune_32(float %a, float %b, i32 %rs1, i32 %rs2) { 3989; RV32I-LABEL: setune_32: 3990; RV32I: # %bb.0: 3991; RV32I-NEXT: feq.s a2, fa0, fa1 3992; RV32I-NEXT: beqz a2, .LBB58_2 3993; RV32I-NEXT: # %bb.1: 3994; RV32I-NEXT: mv a0, a1 3995; RV32I-NEXT: .LBB58_2: 3996; RV32I-NEXT: ret 3997; 3998; RV64I-LABEL: setune_32: 3999; RV64I: # %bb.0: 4000; RV64I-NEXT: feq.s a2, fa0, fa1 4001; RV64I-NEXT: beqz a2, .LBB58_2 4002; RV64I-NEXT: # %bb.1: 4003; RV64I-NEXT: mv a0, a1 4004; RV64I-NEXT: .LBB58_2: 4005; RV64I-NEXT: ret 4006; 4007; RV32XVENTANACONDOPS-LABEL: setune_32: 4008; RV32XVENTANACONDOPS: # %bb.0: 4009; RV32XVENTANACONDOPS-NEXT: feq.s a2, fa0, fa1 4010; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2 4011; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2 4012; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 4013; RV32XVENTANACONDOPS-NEXT: ret 4014; 4015; RV64XVENTANACONDOPS-LABEL: setune_32: 4016; RV64XVENTANACONDOPS: # %bb.0: 4017; RV64XVENTANACONDOPS-NEXT: feq.s a2, fa0, fa1 4018; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2 4019; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2 4020; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 4021; RV64XVENTANACONDOPS-NEXT: ret 4022; 4023; RV64XTHEADCONDMOV-LABEL: setune_32: 4024; RV64XTHEADCONDMOV: # %bb.0: 4025; RV64XTHEADCONDMOV-NEXT: feq.s a2, fa0, fa1 4026; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, a1, a2 4027; RV64XTHEADCONDMOV-NEXT: ret 4028; 4029; RV32ZICOND-LABEL: setune_32: 4030; RV32ZICOND: # %bb.0: 4031; RV32ZICOND-NEXT: feq.s a2, fa0, fa1 4032; RV32ZICOND-NEXT: czero.eqz a1, a1, a2 4033; RV32ZICOND-NEXT: czero.nez a0, a0, a2 4034; RV32ZICOND-NEXT: or a0, a0, a1 4035; RV32ZICOND-NEXT: ret 4036; 4037; RV64ZICOND-LABEL: setune_32: 4038; RV64ZICOND: # %bb.0: 4039; RV64ZICOND-NEXT: feq.s a2, fa0, fa1 4040; RV64ZICOND-NEXT: czero.eqz a1, a1, a2 4041; RV64ZICOND-NEXT: czero.nez a0, a0, a2 4042; RV64ZICOND-NEXT: or a0, a0, a1 4043; RV64ZICOND-NEXT: ret 4044 %rc = fcmp une float %a, %b 4045 %sel = select i1 %rc, i32 %rs1, i32 %rs2 4046 ret i32 %sel 4047} 4048 4049define i64 @setune_64(float %a, float %b, i64 %rs1, i64 %rs2) { 4050; RV32I-LABEL: setune_64: 4051; RV32I: # %bb.0: 4052; RV32I-NEXT: feq.s a4, fa0, fa1 4053; RV32I-NEXT: beqz a4, .LBB59_2 4054; RV32I-NEXT: # %bb.1: 4055; RV32I-NEXT: mv a0, a2 4056; RV32I-NEXT: mv a1, a3 4057; RV32I-NEXT: .LBB59_2: 4058; RV32I-NEXT: ret 4059; 4060; RV64I-LABEL: setune_64: 4061; RV64I: # %bb.0: 4062; RV64I-NEXT: feq.s a2, fa0, fa1 4063; RV64I-NEXT: beqz a2, .LBB59_2 4064; RV64I-NEXT: # %bb.1: 4065; RV64I-NEXT: mv a0, a1 4066; RV64I-NEXT: .LBB59_2: 4067; RV64I-NEXT: ret 4068; 4069; RV32XVENTANACONDOPS-LABEL: setune_64: 4070; RV32XVENTANACONDOPS: # %bb.0: 4071; RV32XVENTANACONDOPS-NEXT: feq.s a4, fa0, fa1 4072; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a4 4073; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a4 4074; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a4 4075; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a4 4076; RV32XVENTANACONDOPS-NEXT: or a0, a0, a2 4077; RV32XVENTANACONDOPS-NEXT: or a1, a1, a3 4078; RV32XVENTANACONDOPS-NEXT: ret 4079; 4080; RV64XVENTANACONDOPS-LABEL: setune_64: 4081; RV64XVENTANACONDOPS: # %bb.0: 4082; RV64XVENTANACONDOPS-NEXT: feq.s a2, fa0, fa1 4083; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2 4084; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2 4085; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 4086; RV64XVENTANACONDOPS-NEXT: ret 4087; 4088; RV64XTHEADCONDMOV-LABEL: setune_64: 4089; RV64XTHEADCONDMOV: # %bb.0: 4090; RV64XTHEADCONDMOV-NEXT: feq.s a2, fa0, fa1 4091; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, a1, a2 4092; RV64XTHEADCONDMOV-NEXT: ret 4093; 4094; RV32ZICOND-LABEL: setune_64: 4095; RV32ZICOND: # %bb.0: 4096; RV32ZICOND-NEXT: feq.s a4, fa0, fa1 4097; RV32ZICOND-NEXT: czero.eqz a2, a2, a4 4098; RV32ZICOND-NEXT: czero.nez a0, a0, a4 4099; RV32ZICOND-NEXT: czero.eqz a3, a3, a4 4100; RV32ZICOND-NEXT: czero.nez a1, a1, a4 4101; RV32ZICOND-NEXT: or a0, a0, a2 4102; RV32ZICOND-NEXT: or a1, a1, a3 4103; RV32ZICOND-NEXT: ret 4104; 4105; RV64ZICOND-LABEL: setune_64: 4106; RV64ZICOND: # %bb.0: 4107; RV64ZICOND-NEXT: feq.s a2, fa0, fa1 4108; RV64ZICOND-NEXT: czero.eqz a1, a1, a2 4109; RV64ZICOND-NEXT: czero.nez a0, a0, a2 4110; RV64ZICOND-NEXT: or a0, a0, a1 4111; RV64ZICOND-NEXT: ret 4112 %rc = fcmp une float %a, %b 4113 %sel = select i1 %rc, i64 %rs1, i64 %rs2 4114 ret i64 %sel 4115} 4116 4117; Test that we can ComputeNumSignBits across basic blocks when the live out is 4118; RISCVISD::SELECT_CC. There should be no slli+srai or sext.h in the output. 4119define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2, i16 signext %3) nounwind { 4120; RV32I-LABEL: numsignbits: 4121; RV32I: # %bb.0: 4122; RV32I-NEXT: addi sp, sp, -16 4123; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 4124; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 4125; RV32I-NEXT: mv s0, a3 4126; RV32I-NEXT: beqz a0, .LBB60_2 4127; RV32I-NEXT: # %bb.1: 4128; RV32I-NEXT: mv s0, a2 4129; RV32I-NEXT: .LBB60_2: 4130; RV32I-NEXT: beqz a1, .LBB60_4 4131; RV32I-NEXT: # %bb.3: 4132; RV32I-NEXT: mv a0, s0 4133; RV32I-NEXT: call bat 4134; RV32I-NEXT: .LBB60_4: 4135; RV32I-NEXT: mv a0, s0 4136; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 4137; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 4138; RV32I-NEXT: addi sp, sp, 16 4139; RV32I-NEXT: ret 4140; 4141; RV64I-LABEL: numsignbits: 4142; RV64I: # %bb.0: 4143; RV64I-NEXT: addi sp, sp, -16 4144; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 4145; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill 4146; RV64I-NEXT: mv s0, a3 4147; RV64I-NEXT: beqz a0, .LBB60_2 4148; RV64I-NEXT: # %bb.1: 4149; RV64I-NEXT: mv s0, a2 4150; RV64I-NEXT: .LBB60_2: 4151; RV64I-NEXT: beqz a1, .LBB60_4 4152; RV64I-NEXT: # %bb.3: 4153; RV64I-NEXT: mv a0, s0 4154; RV64I-NEXT: call bat 4155; RV64I-NEXT: .LBB60_4: 4156; RV64I-NEXT: mv a0, s0 4157; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 4158; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload 4159; RV64I-NEXT: addi sp, sp, 16 4160; RV64I-NEXT: ret 4161; 4162; RV32XVENTANACONDOPS-LABEL: numsignbits: 4163; RV32XVENTANACONDOPS: # %bb.0: 4164; RV32XVENTANACONDOPS-NEXT: addi sp, sp, -16 4165; RV32XVENTANACONDOPS-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 4166; RV32XVENTANACONDOPS-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 4167; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 4168; RV32XVENTANACONDOPS-NEXT: vt.maskcn s0, a3, a0 4169; RV32XVENTANACONDOPS-NEXT: or s0, s0, a2 4170; RV32XVENTANACONDOPS-NEXT: beqz a1, .LBB60_2 4171; RV32XVENTANACONDOPS-NEXT: # %bb.1: 4172; RV32XVENTANACONDOPS-NEXT: mv a0, s0 4173; RV32XVENTANACONDOPS-NEXT: call bat 4174; RV32XVENTANACONDOPS-NEXT: .LBB60_2: 4175; RV32XVENTANACONDOPS-NEXT: mv a0, s0 4176; RV32XVENTANACONDOPS-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 4177; RV32XVENTANACONDOPS-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 4178; RV32XVENTANACONDOPS-NEXT: addi sp, sp, 16 4179; RV32XVENTANACONDOPS-NEXT: ret 4180; 4181; RV64XVENTANACONDOPS-LABEL: numsignbits: 4182; RV64XVENTANACONDOPS: # %bb.0: 4183; RV64XVENTANACONDOPS-NEXT: addi sp, sp, -16 4184; RV64XVENTANACONDOPS-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 4185; RV64XVENTANACONDOPS-NEXT: sd s0, 0(sp) # 8-byte Folded Spill 4186; RV64XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 4187; RV64XVENTANACONDOPS-NEXT: vt.maskcn s0, a3, a0 4188; RV64XVENTANACONDOPS-NEXT: or s0, s0, a2 4189; RV64XVENTANACONDOPS-NEXT: beqz a1, .LBB60_2 4190; RV64XVENTANACONDOPS-NEXT: # %bb.1: 4191; RV64XVENTANACONDOPS-NEXT: mv a0, s0 4192; RV64XVENTANACONDOPS-NEXT: call bat 4193; RV64XVENTANACONDOPS-NEXT: .LBB60_2: 4194; RV64XVENTANACONDOPS-NEXT: mv a0, s0 4195; RV64XVENTANACONDOPS-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 4196; RV64XVENTANACONDOPS-NEXT: ld s0, 0(sp) # 8-byte Folded Reload 4197; RV64XVENTANACONDOPS-NEXT: addi sp, sp, 16 4198; RV64XVENTANACONDOPS-NEXT: ret 4199; 4200; RV64XTHEADCONDMOV-LABEL: numsignbits: 4201; RV64XTHEADCONDMOV: # %bb.0: 4202; RV64XTHEADCONDMOV-NEXT: addi sp, sp, -16 4203; RV64XTHEADCONDMOV-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 4204; RV64XTHEADCONDMOV-NEXT: sd s0, 0(sp) # 8-byte Folded Spill 4205; RV64XTHEADCONDMOV-NEXT: mv s0, a2 4206; RV64XTHEADCONDMOV-NEXT: th.mveqz s0, a3, a0 4207; RV64XTHEADCONDMOV-NEXT: beqz a1, .LBB60_2 4208; RV64XTHEADCONDMOV-NEXT: # %bb.1: 4209; RV64XTHEADCONDMOV-NEXT: mv a0, s0 4210; RV64XTHEADCONDMOV-NEXT: call bat 4211; RV64XTHEADCONDMOV-NEXT: .LBB60_2: 4212; RV64XTHEADCONDMOV-NEXT: mv a0, s0 4213; RV64XTHEADCONDMOV-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 4214; RV64XTHEADCONDMOV-NEXT: ld s0, 0(sp) # 8-byte Folded Reload 4215; RV64XTHEADCONDMOV-NEXT: addi sp, sp, 16 4216; RV64XTHEADCONDMOV-NEXT: ret 4217; 4218; RV32ZICOND-LABEL: numsignbits: 4219; RV32ZICOND: # %bb.0: 4220; RV32ZICOND-NEXT: addi sp, sp, -16 4221; RV32ZICOND-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 4222; RV32ZICOND-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 4223; RV32ZICOND-NEXT: czero.eqz a2, a2, a0 4224; RV32ZICOND-NEXT: czero.nez s0, a3, a0 4225; RV32ZICOND-NEXT: or s0, s0, a2 4226; RV32ZICOND-NEXT: beqz a1, .LBB60_2 4227; RV32ZICOND-NEXT: # %bb.1: 4228; RV32ZICOND-NEXT: mv a0, s0 4229; RV32ZICOND-NEXT: call bat 4230; RV32ZICOND-NEXT: .LBB60_2: 4231; RV32ZICOND-NEXT: mv a0, s0 4232; RV32ZICOND-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 4233; RV32ZICOND-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 4234; RV32ZICOND-NEXT: addi sp, sp, 16 4235; RV32ZICOND-NEXT: ret 4236; 4237; RV64ZICOND-LABEL: numsignbits: 4238; RV64ZICOND: # %bb.0: 4239; RV64ZICOND-NEXT: addi sp, sp, -16 4240; RV64ZICOND-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 4241; RV64ZICOND-NEXT: sd s0, 0(sp) # 8-byte Folded Spill 4242; RV64ZICOND-NEXT: czero.eqz a2, a2, a0 4243; RV64ZICOND-NEXT: czero.nez s0, a3, a0 4244; RV64ZICOND-NEXT: or s0, s0, a2 4245; RV64ZICOND-NEXT: beqz a1, .LBB60_2 4246; RV64ZICOND-NEXT: # %bb.1: 4247; RV64ZICOND-NEXT: mv a0, s0 4248; RV64ZICOND-NEXT: call bat 4249; RV64ZICOND-NEXT: .LBB60_2: 4250; RV64ZICOND-NEXT: mv a0, s0 4251; RV64ZICOND-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 4252; RV64ZICOND-NEXT: ld s0, 0(sp) # 8-byte Folded Reload 4253; RV64ZICOND-NEXT: addi sp, sp, 16 4254; RV64ZICOND-NEXT: ret 4255 %5 = icmp eq i16 %0, 0 4256 %6 = select i1 %5, i16 %3, i16 %2 4257 %7 = icmp eq i16 %1, 0 4258 br i1 %7, label %9, label %8 4259 42608: ; preds = %4 4261 tail call void @bat(i16 signext %6) 4262 br label %9 4263 42649: ; preds = %8, %4 4265 ret i16 %6 4266} 4267 4268declare void @bat(i16 signext) 4269 4270define i64 @single_bit(i64 %x) { 4271; RV32I-LABEL: single_bit: 4272; RV32I: # %bb.0: # %entry 4273; RV32I-NEXT: slli a2, a0, 21 4274; RV32I-NEXT: srai a2, a2, 31 4275; RV32I-NEXT: and a0, a2, a0 4276; RV32I-NEXT: and a1, a2, a1 4277; RV32I-NEXT: ret 4278; 4279; RV64I-LABEL: single_bit: 4280; RV64I: # %bb.0: # %entry 4281; RV64I-NEXT: slli a1, a0, 53 4282; RV64I-NEXT: srai a1, a1, 63 4283; RV64I-NEXT: and a0, a1, a0 4284; RV64I-NEXT: ret 4285; 4286; RV32XVENTANACONDOPS-LABEL: single_bit: 4287; RV32XVENTANACONDOPS: # %bb.0: # %entry 4288; RV32XVENTANACONDOPS-NEXT: andi a2, a0, 1024 4289; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a2 4290; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2 4291; RV32XVENTANACONDOPS-NEXT: ret 4292; 4293; RV64XVENTANACONDOPS-LABEL: single_bit: 4294; RV64XVENTANACONDOPS: # %bb.0: # %entry 4295; RV64XVENTANACONDOPS-NEXT: andi a1, a0, 1024 4296; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a1 4297; RV64XVENTANACONDOPS-NEXT: ret 4298; 4299; RV64XTHEADCONDMOV-LABEL: single_bit: 4300; RV64XTHEADCONDMOV: # %bb.0: # %entry 4301; RV64XTHEADCONDMOV-NEXT: slli a1, a0, 53 4302; RV64XTHEADCONDMOV-NEXT: srai a1, a1, 63 4303; RV64XTHEADCONDMOV-NEXT: and a0, a1, a0 4304; RV64XTHEADCONDMOV-NEXT: ret 4305; 4306; RV32ZICOND-LABEL: single_bit: 4307; RV32ZICOND: # %bb.0: # %entry 4308; RV32ZICOND-NEXT: andi a2, a0, 1024 4309; RV32ZICOND-NEXT: czero.eqz a0, a0, a2 4310; RV32ZICOND-NEXT: czero.eqz a1, a1, a2 4311; RV32ZICOND-NEXT: ret 4312; 4313; RV64ZICOND-LABEL: single_bit: 4314; RV64ZICOND: # %bb.0: # %entry 4315; RV64ZICOND-NEXT: andi a1, a0, 1024 4316; RV64ZICOND-NEXT: czero.eqz a0, a0, a1 4317; RV64ZICOND-NEXT: ret 4318entry: 4319 %and = and i64 %x, 1024 4320 %tobool.not = icmp eq i64 %and, 0 4321 %cond = select i1 %tobool.not, i64 0, i64 %x 4322 ret i64 %cond 4323} 4324 4325; Test to fold select with single bit check to (and (sra (shl x))). 4326define i64 @single_bit2(i64 %x) { 4327; RV32I-LABEL: single_bit2: 4328; RV32I: # %bb.0: # %entry 4329; RV32I-NEXT: slli a2, a0, 20 4330; RV32I-NEXT: srai a2, a2, 31 4331; RV32I-NEXT: and a0, a2, a0 4332; RV32I-NEXT: and a1, a2, a1 4333; RV32I-NEXT: ret 4334; 4335; RV64I-LABEL: single_bit2: 4336; RV64I: # %bb.0: # %entry 4337; RV64I-NEXT: slli a1, a0, 52 4338; RV64I-NEXT: srai a1, a1, 63 4339; RV64I-NEXT: and a0, a1, a0 4340; RV64I-NEXT: ret 4341; 4342; RV32XVENTANACONDOPS-LABEL: single_bit2: 4343; RV32XVENTANACONDOPS: # %bb.0: # %entry 4344; RV32XVENTANACONDOPS-NEXT: bexti a2, a0, 11 4345; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a2 4346; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2 4347; RV32XVENTANACONDOPS-NEXT: ret 4348; 4349; RV64XVENTANACONDOPS-LABEL: single_bit2: 4350; RV64XVENTANACONDOPS: # %bb.0: # %entry 4351; RV64XVENTANACONDOPS-NEXT: bexti a1, a0, 11 4352; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a1 4353; RV64XVENTANACONDOPS-NEXT: ret 4354; 4355; RV64XTHEADCONDMOV-LABEL: single_bit2: 4356; RV64XTHEADCONDMOV: # %bb.0: # %entry 4357; RV64XTHEADCONDMOV-NEXT: slli a1, a0, 52 4358; RV64XTHEADCONDMOV-NEXT: srai a1, a1, 63 4359; RV64XTHEADCONDMOV-NEXT: and a0, a1, a0 4360; RV64XTHEADCONDMOV-NEXT: ret 4361; 4362; RV32ZICOND-LABEL: single_bit2: 4363; RV32ZICOND: # %bb.0: # %entry 4364; RV32ZICOND-NEXT: bexti a2, a0, 11 4365; RV32ZICOND-NEXT: czero.eqz a0, a0, a2 4366; RV32ZICOND-NEXT: czero.eqz a1, a1, a2 4367; RV32ZICOND-NEXT: ret 4368; 4369; RV64ZICOND-LABEL: single_bit2: 4370; RV64ZICOND: # %bb.0: # %entry 4371; RV64ZICOND-NEXT: bexti a1, a0, 11 4372; RV64ZICOND-NEXT: czero.eqz a0, a0, a1 4373; RV64ZICOND-NEXT: ret 4374entry: 4375 %and = and i64 %x, 2048 4376 %tobool.not = icmp eq i64 %and, 0 4377 %cond = select i1 %tobool.not, i64 0, i64 %x 4378 ret i64 %cond 4379} 4380 4381; Test that we don't crash on types larger than 64 bits. 4382define i64 @single_bit3(i80 %x, i64 %y) { 4383; RV32I-LABEL: single_bit3: 4384; RV32I: # %bb.0: # %entry 4385; RV32I-NEXT: lw a0, 8(a0) 4386; RV32I-NEXT: slli a0, a0, 31 4387; RV32I-NEXT: srai a3, a0, 31 4388; RV32I-NEXT: and a0, a3, a1 4389; RV32I-NEXT: and a1, a3, a2 4390; RV32I-NEXT: ret 4391; 4392; RV64I-LABEL: single_bit3: 4393; RV64I: # %bb.0: # %entry 4394; RV64I-NEXT: slli a1, a1, 63 4395; RV64I-NEXT: srai a0, a1, 63 4396; RV64I-NEXT: and a0, a0, a2 4397; RV64I-NEXT: ret 4398; 4399; RV32XVENTANACONDOPS-LABEL: single_bit3: 4400; RV32XVENTANACONDOPS: # %bb.0: # %entry 4401; RV32XVENTANACONDOPS-NEXT: lw a0, 8(a0) 4402; RV32XVENTANACONDOPS-NEXT: andi a3, a0, 1 4403; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a3 4404; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a2, a3 4405; RV32XVENTANACONDOPS-NEXT: ret 4406; 4407; RV64XVENTANACONDOPS-LABEL: single_bit3: 4408; RV64XVENTANACONDOPS: # %bb.0: # %entry 4409; RV64XVENTANACONDOPS-NEXT: andi a1, a1, 1 4410; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a1 4411; RV64XVENTANACONDOPS-NEXT: ret 4412; 4413; RV64XTHEADCONDMOV-LABEL: single_bit3: 4414; RV64XTHEADCONDMOV: # %bb.0: # %entry 4415; RV64XTHEADCONDMOV-NEXT: slli a1, a1, 63 4416; RV64XTHEADCONDMOV-NEXT: srai a0, a1, 63 4417; RV64XTHEADCONDMOV-NEXT: and a0, a0, a2 4418; RV64XTHEADCONDMOV-NEXT: ret 4419; 4420; RV32ZICOND-LABEL: single_bit3: 4421; RV32ZICOND: # %bb.0: # %entry 4422; RV32ZICOND-NEXT: lw a0, 8(a0) 4423; RV32ZICOND-NEXT: andi a3, a0, 1 4424; RV32ZICOND-NEXT: czero.eqz a0, a1, a3 4425; RV32ZICOND-NEXT: czero.eqz a1, a2, a3 4426; RV32ZICOND-NEXT: ret 4427; 4428; RV64ZICOND-LABEL: single_bit3: 4429; RV64ZICOND: # %bb.0: # %entry 4430; RV64ZICOND-NEXT: andi a1, a1, 1 4431; RV64ZICOND-NEXT: czero.eqz a0, a2, a1 4432; RV64ZICOND-NEXT: ret 4433entry: 4434 %and = and i80 %x, 18446744073709551616 ; 1 << 64 4435 %tobool.not = icmp eq i80 %and, 0 4436 %cond = select i1 %tobool.not, i64 0, i64 %y 4437 ret i64 %cond 4438} 4439