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/llvm-project/llvm/test/CodeGen/AArch64/
H A Dcomplex-deinterleaving-add-mull-fixed-contract.ll7 define <4 x double> @mull_add(<4 x double> %a, <4 x double> %b, <4 x double> %c) {
10 ; CHECK-NEXT: zip2 v4.2d, v2.2d, v3.2d
11 ; CHECK-NEXT: zip2 v5.2d, v0.2d, v1.2d
12 ; CHECK-NEXT: zip1 v0.2d, v0.2d, v1.2d
13 ; CHECK-NEXT: zip1 v2.2d, v2.2d, v3.2d
14 ; CHECK-NEXT: fmul v1.2d, v5.2d, v4.2d
15 ; CHECK-NEXT: fmul v3.2d, v0.2d, v4.2d
16 ; CHECK-NEXT: fneg v1.2d, v1.2d
17 ; CHECK-NEXT: fmla v3.2d, v2.2d, v5.2d
18 ; CHECK-NEXT: fmla v1.2d, v2.2d, v0.2d
[all …]
H A Dcomplex-deinterleaving-add-mull-fixed-fast.ll7 define <4 x double> @mull_add(<4 x double> %a, <4 x double> %b, <4 x double> %c) {
10 ; CHECK-NEXT: fcmla v4.2d, v0.2d, v2.2d, #0
11 ; CHECK-NEXT: fcmla v5.2d, v1.2d, v3.2d, #0
12 ; CHECK-NEXT: fcmla v4.2d, v0.2d, v2.2d, #90
13 ; CHECK-NEXT: fcmla v5.2d, v1.2d, v3.2d, #90
18 %strided.vec = shufflevector <4 x double> %a, <4 x double> poison, <2 x i32> <i32 0, i32 2>
19 %strided.vec28 = shufflevector <4 x double> %a, <4 x double> poison, <2 x i32> <i32 1, i32 3>
20 %strided.vec30 = shufflevector <4 x double> %b, <4 x double> poison, <2 x i32> <i32 0, i32 2>
21 %strided.vec31 = shufflevector <4 x double> %b, <4 x double> poison, <2 x i32> <i32 1, i32 3>
26 %strided.vec33 = shufflevector <4 x double> %c, <4 x double> poison, <2 x i32> <i32 0, i32 2>
[all …]
H A Dsqrt-fastmath.ll7 declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #0
11 declare <4 x double> @llvm.sqrt.v4f64(<4 x double>) #0
82 define <4 x float> @f4sqrt(<4 x float> %a) #0 {
85 ; FAULT-NEXT: fsqrt v0.4s, v0.4s
90 ; CHECK-NEXT: frsqrte v1.4s, v0.4s
91 ; CHECK-NEXT: fmul v2.4s, v1.4s, v1.4s
92 ; CHECK-NEXT: frsqrts v2.4s, v0.4s, v2.4s
93 ; CHECK-NEXT: fmul v1.4s, v1.4s, v2.4s
94 ; CHECK-NEXT: fmul v2.4s, v1.4s, v1.4s
95 ; CHECK-NEXT: fmul v1.4s, v0.4s, v1.4s
[all …]
H A Dsme2-intrinsics-max.ll1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
9 ; CHECK-NEXT: mov z5.d, z2.d
10 ; CHECK-NEXT: mov z4.d, z1.d
12 ; CHECK-NEXT: mov z0.d, z4.d
13 ; CHECK-NEXT: mov z1.d, z5.d
22 ; CHECK-NEXT: mov z5.d, z
[all...]
H A Dsme2-intrinsics-min.ll1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
9 ; CHECK-NEXT: mov z5.d, z2.d
10 ; CHECK-NEXT: mov z4.d, z1.d
12 ; CHECK-NEXT: mov z0.d, z4.d
13 ; CHECK-NEXT: mov z1.d, z5.d
22 ; CHECK-NEXT: mov z5.d, z
[all...]
H A Dsme2-intrinsics-rshl.ll1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
9 ; CHECK-NEXT: mov z5.d, z2.d
10 ; CHECK-NEXT: mov z4.d, z1.d
12 ; CHECK-NEXT: mov z0.d, z4.d
13 ; CHECK-NEXT: mov z1.d, z5.d
22 ; CHECK-NEXT: mov z5.d, z2.d
23 ; CHECK-NEXT: mov z4.d, z1.d
25 ; CHECK-NEXT: mov z0.d, z4.d
26 ; CHECK-NEXT: mov z1.d, z5.d
32 …4 x i32>, <vscale x 4 x i32> } @multi_vec_rounding_shl_single_x2_s32(<vscale x 4 x i32> %dummy, <v…
[all …]
H A Dcomplex-deinterleaving-i64-mul-scalable.ll10 ; CHECK-NEXT: mov z2.d, #0 // =0x0
11 ; CHECK-NEXT: cmla z2.d, z1.d, z0.d, #0
12 ; CHECK-NEXT: cmla z2.d, z1.d, z0.d, #90
13 ; CHECK-NEXT: mov z0.d, z2.d
26 %4 = mul <vscale x 1 x i64> %a.imag, %b.imag
27 %5 = sub <vscale x 1 x i64> %3, %4
33 define <vscale x 4 x i64> @complex_mul_v4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {
36 ; CHECK-NEXT: mov z4.d, #0 // =0x0
37 ; CHECK-NEXT: mov z5.d, z4.d
38 ; CHECK-NEXT: cmla z4.d, z3.d, z1.d, #0
[all …]
H A Dfp16-v16-instructions.ll8 ; CHECK-NEXT: scvtf v0.4s, v0.4s
9 ; CHECK-NEXT: scvtf v2.4s, v2.4s
10 ; CHECK-NEXT: scvtf v4.4s, v1.4s
11 ; CHECK-NEXT: fcvtn v0.4h, v0.4s
12 ; CHECK-NEXT: fcvtn v1.4h, v2.4s
13 ; CHECK-NEXT: scvtf v2.4s, v3.4s
14 ; CHECK-NEXT: fcvtn2 v0.8h, v4.4s
15 ; CHECK-NEXT: fcvtn2 v1.8h, v2.4s
26 ; CHECK-NEXT: scvtf v0.2d, v0.2d
27 ; CHECK-NEXT: scvtf v4.2d, v4.2d
[all …]
H A Dsve2-fcopysign.ll13 ; CHECK-NEXT: bsl z0.d, z0.d, z1.d, z2.d
22 ; CHECK-NEXT: ptrue p0.d
24 ; CHECK-NEXT: fcvt z1.s, p0/m, z1.d
25 ; CHECK-NEXT: bsl z0.d, z0.d, z1.d, z2.d
36 define <vscale x 4 x float> @test_copysign_v4f32_v4f32(<vscale x 4 x float> %a, <vscale x 4 x float…
40 ; CHECK-NEXT: bsl z0.d, z0.d, z1.d, z2.d
42 …%r = call <vscale x 4 x float> @llvm.copysign.v4f32(<vscale x 4 x float> %a, <vscale x 4 x float> …
43 ret <vscale x 4 x float> %r
47 define <vscale x 4 x float> @test_copysign_v4f32_v4f64(<vscale x 4 x float> %a, <vscale x 4 x doubl…
50 ; CHECK_NO_EXTEND_ROUND-NEXT: ptrue p0.d
[all …]
H A Dsme2-intrinsics-sqdmulh.ll1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
9 ; CHECK-NEXT: mov z5.d, z2.d
10 ; CHECK-NEXT: mov z4.d, z1.d
12 ; CHECK-NEXT: mov z0.d, z4.d
13 ; CHECK-NEXT: mov z1.d, z5.d
22 ; CHECK-NEXT: mov z5.d, z2.d
23 ; CHECK-NEXT: mov z4.d, z1.d
25 ; CHECK-NEXT: mov z0.d, z4.d
26 ; CHECK-NEXT: mov z1.d, z5.d
32 …4 x i32>, <vscale x 4 x i32> } @multi_vec_sat_double_mulh_single_x2_s32(<vscale x 4 x i32> %unused…
[all …]
H A Dfdiv-combine.ll5 ; a / D; b / D; c / D;
7 ; recip = 1.0 / D; a * recip; b * recip; c * recip;
8 define void @three_fdiv_float(float %D, float %a, float %b, float %c) #0 {
17 %div = fdiv float %a, %D
18 %div1 = fdiv float %b, %D
19 %div2 = fdiv float %c, %D
24 define void @three_fdiv_double(double %D, double %a, double %b, double %c) #0 {
33 %div = fdiv double %a, %D
34 %div1 = fdiv double %b, %D
35 %div2 = fdiv double %c, %D
[all …]
H A Dvector-fcvt.ll6 define <4 x float> @sitofp_v4i8_float(<4 x i8> %a) {
9 ; CHECK-NEXT: shl v0.4h, v0.4h, #8
10 ; CHECK-NEXT: sshr v0.4h, v0.4h, #8
11 ; CHECK-NEXT: sshll v0.4s, v0.4h, #0
12 ; CHECK-NEXT: scvtf v0.4s, v0.4s
14 %1 = sitofp <4 x i8> %a to <4 x float>
15 ret <4 x float> %1
23 ; CHECK-NEXT: shl v1.4h, v1.4h, #8
24 ; CHECK-NEXT: shl v0.4h, v0.4h, #8
25 ; CHECK-NEXT: sshr v1.4h, v1.4h, #8
[all …]
H A Dsme2-intrinsics-qrshr.ll8 … @multi_vector_sat_shift_narrow_x2_s16(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscal…
11 ; CHECK-NEXT: mov z3.d, z2.d
12 ; CHECK-NEXT: mov z2.d, z1.d
15 …scale x 8 x i16> @llvm.aarch64.sve.sqrshr.x2.nxv8i16(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %…
19 … @multi_vector_sat_shift_narrow_x2_u16(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscal…
22 ; CHECK-NEXT: mov z3.d, z2.d
23 ; CHECK-NEXT: mov z2.d, z1.d
26 …scale x 8 x i16> @llvm.aarch64.sve.uqrshr.x2.nxv8i16(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %…
34 …_narrow_x4_s8(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscal…
37 ; CHECK-NEXT: mov z7.d, z4.d
[all …]
H A Dcomplex-deinterleaving-add-mull-scalable-contract.ll7 define <vscale x 4 x double> @mull_add(<vscale x 4 x double> %a, <vscale x 4 x double> %b, <vscale …
10 ; CHECK-NEXT: uzp2 z6.d, z0.d, z1.d
11 ; CHECK-NEXT: uzp1 z0.d, z0.d, z1.d
12 ; CHECK-NEXT: uzp2 z1.d, z2.d, z3.d
13 ; CHECK-NEXT: uzp1 z2.d, z2.d, z3.d
14 ; CHECK-NEXT: ptrue p0.d
15 ; CHECK-NEXT: fmul z7.d, z0.d, z1.d
16 ; CHECK-NEXT: fmul z1.d, z6.d, z1.d
18 ; CHECK-NEXT: fmla z3.d, p0/m, z6.d, z2.d
19 ; CHECK-NEXT: fnmsb z0.d, p0/m, z2.d, z1.d
[all …]
H A Dsve2-eor3.ll8 ; SVE-NEXT: eor z0.d, z0.d, z1.d
9 ; SVE-NEXT: eor z0.d, z0.d, z2.d
14 ; SVE2-NEXT: eor3 z0.d, z0.d, z1.d, z2.d
16 %4 = xor <vscale x 16 x i8> %0, %1
17 %5 = xor <vscale x 16 x i8> %4, %2
24 ; SVE-NEXT: eor z0.d, z0.d, z1.d
25 ; SVE-NEXT: eor z0.d, z2.d, z0.d
30 ; SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z1.d
31 ; SVE2-NEXT: mov z0.d, z2.d
33 %4 = xor <vscale x 16 x i8> %0, %1
[all …]
H A Dsve2-bcax.ll1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
8 ; SVE-NEXT: bic z1.d, z2.d, z1.d
9 ; SVE-NEXT: eor z0.d, z1.d, z0.d
14 ; SVE2-NEXT: bcax z0.d, z0.d, z2.d, z1.d
16 %4 = xor <vscale x 2 x i64> %1, splat (i64 -1)
17 %5 = and <vscale x 2 x i64> %4, %2
25 ; SVE-NEXT: bic z0.d, z0.d, z1.d
26 ; SVE-NEXT: eor z0.d, z0.d, z2.d
31 ; SVE2-NEXT: bcax z2.d, z2.d, z0.d, z1.d
32 ; SVE2-NEXT: mov z0.d, z2.d
[all …]
H A Ditofp.ll999 ; CHECK-SD-NEXT: mov x0, v0.d[1]
1016 ; CHECK-GI-NEXT: mov d8, v0.d[1]
1044 ; CHECK-SD-NEXT: mov x0, v0.d[1]
1061 ; CHECK-GI-NEXT: mov d8, v0.d[1]
1217 ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
1242 ; CHECK-GI-NEXT: mov v1.d[1], v0.d[0]
1275 ; CHECK-SD-NEXT: mov v0.d[1], v1.d[
[all...]
H A Dcomplex-deinterleaving-add-mull-scalable-fast.ll7 define <vscale x 4 x double> @mull_add(<vscale x 4 x double> %a, <vscale x 4 x double> %b, <vscale …
10 ; CHECK-NEXT: ptrue p0.d
11 ; CHECK-NEXT: fcmla z4.d, p0/m, z0.d, z2.d, #0
12 ; CHECK-NEXT: fcmla z5.d, p0/m, z1.d, z3.d, #0
13 ; CHECK-NEXT: fcmla z4.d, p0/m, z0.d, z2.d, #90
14 ; CHECK-NEXT: fcmla z5.d, p0/m, z1.d, z3.d, #90
15 ; CHECK-NEXT: mov z0.d, z4.d
16 ; CHECK-NEXT: mov z1.d, z5.d
19 …x 2 x double>, <vscale x 2 x double> } @llvm.vector.deinterleave2.nxv4f64(<vscale x 4 x double> %a)
22 …x 2 x double>, <vscale x 2 x double> } @llvm.vector.deinterleave2.nxv4f64(<vscale x 4 x double> %b)
[all …]
H A Dsve2-xar.ll1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
8 ; SVE-NEXT: eor z0.d, z0.d, z1.d
9 ; SVE-NEXT: lsr z1.d, z0.d, #4
10 ; SVE-NEXT: lsl z0.d, z0.d, #60
11 ; SVE-NEXT: orr z0.d, z0.d, z1.d
16 ; SVE2-NEXT: xar z0.d, z0.d, z1.d, #4
26 ; SVE-NEXT: eor z0.d, z0.d, z1.d
27 ; SVE-NEXT: lsl z1.d, z0.d, #60
28 ; SVE-NEXT: lsr z0.d, z0.d, #4
29 ; SVE-NEXT: orr z0.d, z0.d, z1.d
[all …]
H A Dsve-hadd.ll8 ; SVE-NEXT: eor z2.d, z0.d, z1.d
9 ; SVE-NEXT: and z0.d, z0.d, z1.d
10 ; SVE-NEXT: asr z1.d, z2.d, #1
11 ; SVE-NEXT: add z0.d, z0.d, z
[all...]
/llvm-project/llvm/test/tools/llvm-nm/X86/
H A Dradix.s3 // RUN: llvm-nm --radix=d %t.o | FileCheck %s
13 .align 4
16 .size i0, 4
21 .align 4
24 .size i1, 4
28 .align 4
31 .size i2, 4
35 .align 4
38 .size i3, 4
42 .align 4
[all …]
/llvm-project/llvm/test/tools/llvm-mca/AArch64/Neoverse/
H A DV2-forwarding.s28 mul v0.4s, v0.4s, v0.4s
29 saba v0.4s, v1.4s, v2.4s
30 saba v0.4s, v1.4s, v2.4s
31 saba v0.4s, v0.4s, v1.4s
35 mul v0.4s, v0.4s, v0.4s
36 sdot v0.4s, v1.16b, v2.16b
37 sdot v0.4s, v1.16b, v2.16b
38 sdot v0.4s, v0.16b, v1.16b
42 mul v0.4s, v0.4s, v0.4s
43 smmla v0.4s, v1.16b, v2.16b
[all …]
H A DN1-neon-instructions.s6 abs v0.2d, v0.2d
8 abs v0.4h, v0.4h
9 abs v0.4s, v0.4s
14 addhn v0.2s, v0.2d, v0.2d
15 addhn v0.4h, v0.4s, v0.4s
18 addhn2 v0.4s, v0.2d, v0.2d
19 addhn2 v0.8h, v0.4s, v0.4s
20 addp v0.2d, v0.2d, v0.2d
23 bic v0.4h, #15, lsl #8
30 cls v0.4h, v0.4h
[all …]
/llvm-project/llvm/test/tools/llvm-mca/AArch64/A64FX/
H A DA64FX-neon-instructions.s6 abs v0.2d, v0.2d
8 abs v0.4h, v0.4h
9 abs v0.4s, v0.4s
14 addhn v0.2s, v0.2d, v0.2d
15 addhn v0.4h, v0.4s, v0.4s
18 addhn2 v0.4s, v0.2d, v0.2d
19 addhn2 v0.8h, v0.4s, v0.4s
20 addp v0.2d, v0.2d, v0.2d
23 bic v0.4h, #15, lsl #8
30 cls v0.4h, v0.4h
[all …]
/llvm-project/llvm/test/tools/llvm-mca/AArch64/Exynos/
H A Dasimd-st1.s12 st1 {v0.d}[0], [sp]
13 st1 {v0.2d}, [sp]
14 st1 {v0.2d, v1.2d}, [sp]
15 st1 {v0.2d, v1.2d, v2.2d}, [sp]
16 st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp]
18 st1 {v0.s}[0], [sp], #4
24 st1 {v0.d}[0], [sp], #8
25 st1 {v0.2d}, [sp], #16
26 st1 {v0.2d, v1.2d}, [sp], #32
27 st1 {v0.2d, v1.2d, v2.2d}, [sp], #48
[all …]

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