Lines Matching +full:4 +full:d
8 … @multi_vector_sat_shift_narrow_x2_s16(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscal…
11 ; CHECK-NEXT: mov z3.d, z2.d
12 ; CHECK-NEXT: mov z2.d, z1.d
15 …scale x 8 x i16> @llvm.aarch64.sve.sqrshr.x2.nxv8i16(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %…
19 … @multi_vector_sat_shift_narrow_x2_u16(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscal…
22 ; CHECK-NEXT: mov z3.d, z2.d
23 ; CHECK-NEXT: mov z2.d, z1.d
26 …scale x 8 x i16> @llvm.aarch64.sve.uqrshr.x2.nxv8i16(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %…
34 …_narrow_x4_s8(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscal…
37 ; CHECK-NEXT: mov z7.d, z4.d
38 ; CHECK-NEXT: mov z6.d, z3.d
39 ; CHECK-NEXT: mov z5.d, z2.d
40 ; CHECK-NEXT: mov z4.d, z1.d
43 …rch64.sve.sqrshr.x4.nxv16i8(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %…
50 ; CHECK-NEXT: mov z7.d, z4.d
51 ; CHECK-NEXT: mov z6.d, z3.d
52 ; CHECK-NEXT: mov z5.d, z2.d
53 ; CHECK-NEXT: mov z4.d, z1.d
54 ; CHECK-NEXT: sqrshr z0.h, { z4.d - z7.d }, #64
60 …_narrow_x4_u8(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscal…
63 ; CHECK-NEXT: mov z7.d, z4.d
64 ; CHECK-NEXT: mov z6.d, z3.d
65 ; CHECK-NEXT: mov z5.d, z2.d
66 ; CHECK-NEXT: mov z4.d, z1.d
69 …rch64.sve.uqrshr.x4.nxv16i8(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %…
76 ; CHECK-NEXT: mov z7.d, z4.d
77 ; CHECK-NEXT: mov z6.d, z3.d
78 ; CHECK-NEXT: mov z5.d, z2.d
79 ; CHECK-NEXT: mov z4.d, z1.d
80 ; CHECK-NEXT: uqrshr z0.h, { z4.d - z7.d }, #64
88 …erleave_x4_s8(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscal…
91 ; CHECK-NEXT: mov z7.d, z4.d
92 ; CHECK-NEXT: mov z6.d, z3.d
93 ; CHECK-NEXT: mov z5.d, z2.d
94 ; CHECK-NEXT: mov z4.d, z1.d
97 …ch64.sve.sqrshrn.x4.nxv16i8(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %…
104 ; CHECK-NEXT: mov z7.d, z4.d
105 ; CHECK-NEXT: mov z6.d, z3.d
106 ; CHECK-NEXT: mov z5.d, z2.d
107 ; CHECK-NEXT: mov z4.d, z1.d
108 ; CHECK-NEXT: sqrshrn z0.h, { z4.d - z7.d }, #64
114 …<vscale x 2 x i64> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %…
117 ; CHECK-NEXT: mov z7.d, z4.d
118 ; CHECK-NEXT: mov z6.d, z3.d
119 ; CHECK-NEXT: mov z5.d, z2.d
120 ; CHECK-NEXT: mov z4.d, z1.d
123 …ch64.sve.uqrshrn.x4.nxv16i8(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %…
130 ; CHECK-NEXT: mov z7.d, z4.d
131 ; CHECK-NEXT: mov z6.d, z3.d
132 ; CHECK-NEXT: mov z5.d, z2.d
133 ; CHECK-NEXT: mov z4.d, z1.d
134 ; CHECK-NEXT: uqrshrn z0.h, { z4.d - z7.d }, #64
142 …ector_sat_shift_unsigned_narrow_x2_u16(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscal…
145 ; CHECK-NEXT: mov z3.d, z2.d
146 ; CHECK-NEXT: mov z2.d, z1.d
149 …cale x 8 x i16> @llvm.aarch64.sve.sqrshru.x2.nxv8i16(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %…
155 …_narrow_x4_u8(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscal…
158 ; CHECK-NEXT: mov z7.d, z4.d
159 ; CHECK-NEXT: mov z6.d, z3.d
160 ; CHECK-NEXT: mov z5.d, z2.d
161 ; CHECK-NEXT: mov z4.d, z1.d
164 …ch64.sve.sqrshru.x4.nxv16i8(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %…
171 ; CHECK-NEXT: mov z7.d, z4.d
172 ; CHECK-NEXT: mov z6.d, z3.d
173 ; CHECK-NEXT: mov z5.d, z2.d
174 ; CHECK-NEXT: mov z4.d, z1.d
175 ; CHECK-NEXT: sqrshru z0.h, { z4.d - z7.d }, #64
183 …erleave_x4_u8(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscal…
186 ; CHECK-NEXT: mov z7.d, z4.d
187 ; CHECK-NEXT: mov z6.d, z3.d
188 ; CHECK-NEXT: mov z5.d, z2.d
189 ; CHECK-NEXT: mov z4.d, z1.d
192 …h64.sve.sqrshrun.x4.nxv16i8(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %…
199 ; CHECK-NEXT: mov z7.d, z4.d
200 ; CHECK-NEXT: mov z6.d, z3.d
201 ; CHECK-NEXT: mov z5.d, z2.d
202 ; CHECK-NEXT: mov z4.d, z1.d
203 ; CHECK-NEXT: sqrshrun z0.h, { z4.d - z7.d }, #64
209 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshr.x2.nxv8i16(<vscale x 4 x i32>, <vscale x 4 x i3…
211 …@llvm.aarch64.sve.sqrshr.x4.nxv16i8(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <v…
214 declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x2.nxv8i16(<vscale x 4 x i32>, <vscale x 4 x i3…
216 …@llvm.aarch64.sve.uqrshr.x4.nxv16i8(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <v…
219 …llvm.aarch64.sve.sqrshrn.x4.nxv16i8(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <v…
222 …llvm.aarch64.sve.uqrshrn.x4.nxv16i8(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <v…
225 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshru.x2.nxv8i16(<vscale x 4 x i32>, <vscale x 4 x i…
227 …llvm.aarch64.sve.sqrshru.x4.nxv16i8(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <v…
230 …lvm.aarch64.sve.sqrshrun.x4.nxv16i8(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <v…