Lines Matching +full:4 +full:d
13 ; CHECK-NEXT: bsl z0.d, z0.d, z1.d, z2.d
22 ; CHECK-NEXT: ptrue p0.d
24 ; CHECK-NEXT: fcvt z1.s, p0/m, z1.d
25 ; CHECK-NEXT: bsl z0.d, z0.d, z1.d, z2.d
36 define <vscale x 4 x float> @test_copysign_v4f32_v4f32(<vscale x 4 x float> %a, <vscale x 4 x float…
40 ; CHECK-NEXT: bsl z0.d, z0.d, z1.d, z2.d
42 …%r = call <vscale x 4 x float> @llvm.copysign.v4f32(<vscale x 4 x float> %a, <vscale x 4 x float> …
43 ret <vscale x 4 x float> %r
47 define <vscale x 4 x float> @test_copysign_v4f32_v4f64(<vscale x 4 x float> %a, <vscale x 4 x doubl…
50 ; CHECK_NO_EXTEND_ROUND-NEXT: ptrue p0.d
52 ; CHECK_NO_EXTEND_ROUND-NEXT: fcvt z2.s, p0/m, z2.d
53 ; CHECK_NO_EXTEND_ROUND-NEXT: fcvt z1.s, p0/m, z1.d
55 ; CHECK_NO_EXTEND_ROUND-NEXT: bsl z0.d, z0.d, z1.d, z3.d
60 ; CHECK_EXTEND_ROUND-NEXT: ptrue p0.d
61 ; CHECK_EXTEND_ROUND-NEXT: uunpkhi z3.d, z0.s
63 ; CHECK_EXTEND_ROUND-NEXT: uunpklo z0.d, z0.s
64 ; CHECK_EXTEND_ROUND-NEXT: fcvt z2.s, p0/m, z2.d
65 ; CHECK_EXTEND_ROUND-NEXT: fcvt z1.s, p0/m, z1.d
66 ; CHECK_EXTEND_ROUND-NEXT: bsl z3.d, z3.d, z2.d, z4.d
67 ; CHECK_EXTEND_ROUND-NEXT: bsl z0.d, z0.d, z1.d, z4.d
70 %tmp0 = fptrunc <vscale x 4 x double> %b to <vscale x 4 x float>
71 …%r = call <vscale x 4 x float> @llvm.copysign.v4f32(<vscale x 4 x float> %a, <vscale x 4 x float> …
72 ret <vscale x 4 x float> %r
75 declare <vscale x 4 x float> @llvm.copysign.v4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b)…
82 ; CHECK-NEXT: ptrue p0.d
83 ; CHECK-NEXT: mov z2.d, #0x7fffffffffffffff
84 ; CHECK-NEXT: fcvt z1.d, p0/m, z1.s
85 ; CHECK-NEXT: bsl z0.d, z0.d, z1.d, z2.d
95 ; CHECK-NEXT: mov z2.d, #0x7fffffffffffffff
96 ; CHECK-NEXT: bsl z0.d, z0.d, z1.d, z2.d
107 define <vscale x 4 x double> @test_copysign_v4f64_v4f32(<vscale x 4 x double> %a, <vscale x 4 x flo…
110 ; CHECK_NO_EXTEND_ROUND-NEXT: uunpkhi z3.d, z2.s
111 ; CHECK_NO_EXTEND_ROUND-NEXT: uunpklo z2.d, z2.s
112 ; CHECK_NO_EXTEND_ROUND-NEXT: ptrue p0.d
113 ; CHECK_NO_EXTEND_ROUND-NEXT: mov z4.d, #0x7fffffffffffffff
114 ; CHECK_NO_EXTEND_ROUND-NEXT: fcvt z3.d, p0/m, z3.s
115 ; CHECK_NO_EXTEND_ROUND-NEXT: fcvt z2.d, p0/m, z2.s
116 ; CHECK_NO_EXTEND_ROUND-NEXT: bsl z0.d, z0.d, z2.d, z4.d
117 ; CHECK_NO_EXTEND_ROUND-NEXT: bsl z1.d, z1.d, z3.d, z4.d
122 ; CHECK_EXTEND_ROUND-NEXT: uunpkhi z3.d, z2.s
123 ; CHECK_EXTEND_ROUND-NEXT: uunpklo z2.d, z2.s
124 ; CHECK_EXTEND_ROUND-NEXT: ptrue p0.d
125 ; CHECK_EXTEND_ROUND-NEXT: mov z4.d, #0x7fffffffffffffff
126 ; CHECK_EXTEND_ROUND-NEXT: fcvt z2.d, p0/m, z2.s
127 ; CHECK_EXTEND_ROUND-NEXT: fcvt z3.d, p0/m, z3.s
128 ; CHECK_EXTEND_ROUND-NEXT: bsl z0.d, z0.d, z2.d, z4.d
129 ; CHECK_EXTEND_ROUND-NEXT: bsl z1.d, z1.d, z3.d, z4.d
131 %tmp0 = fpext <vscale x 4 x float> %b to <vscale x 4 x double>
132 …%r = call <vscale x 4 x double> @llvm.copysign.v4f64(<vscale x 4 x double> %a, <vscale x 4 x doubl…
133 ret <vscale x 4 x double> %r
137 define <vscale x 4 x double> @test_copysign_v4f64_v4f64(<vscale x 4 x double> %a, <vscale x 4 x dou…
140 ; CHECK-NEXT: mov z4.d, #0x7fffffffffffffff
141 ; CHECK-NEXT: bsl z0.d, z0.d, z2.d, z4.d
142 ; CHECK-NEXT: bsl z1.d, z1.d, z3.d, z4.d
144 …%r = call <vscale x 4 x double> @llvm.copysign.v4f64(<vscale x 4 x double> %a, <vscale x 4 x doubl…
145 ret <vscale x 4 x double> %r
148 declare <vscale x 4 x double> @llvm.copysign.v4f64(<vscale x 4 x double> %a, <vscale x 4 x double> …
152 define <vscale x 4 x half> @test_copysign_v4f16_v4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %…
156 ; CHECK-NEXT: bsl z0.d, z0.d, z1.d, z2.d
158 %r = call <vscale x 4 x half> @llvm.copysign.v4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b)
159 ret <vscale x 4 x half> %r
162 define <vscale x 4 x half> @test_copysign_v4f16_v4f32(<vscale x 4 x half> %a, <vscale x 4 x float> …
168 ; CHECK-NEXT: bsl z0.d, z0.d, z1.d, z2.d
170 %tmp0 = fptrunc <vscale x 4 x float> %b to <vscale x 4 x half>
171 …%r = call <vscale x 4 x half> @llvm.copysign.v4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %tm…
172 ret <vscale x 4 x half> %r
175 define <vscale x 4 x half> @test_copysign_v4f16_v4f64(<vscale x 4 x half> %a, <vscale x 4 x double>…
178 ; CHECK_NO_EXTEND_ROUND-NEXT: ptrue p0.d
180 ; CHECK_NO_EXTEND_ROUND-NEXT: fcvt z2.h, p0/m, z2.d
181 ; CHECK_NO_EXTEND_ROUND-NEXT: fcvt z1.h, p0/m, z1.d
183 ; CHECK_NO_EXTEND_ROUND-NEXT: bsl z0.d, z0.d, z1.d, z3.d
188 ; CHECK_EXTEND_ROUND-NEXT: ptrue p0.d
189 ; CHECK_EXTEND_ROUND-NEXT: uunpkhi z3.d, z0.s
191 ; CHECK_EXTEND_ROUND-NEXT: uunpklo z0.d, z0.s
192 ; CHECK_EXTEND_ROUND-NEXT: fcvt z2.h, p0/m, z2.d
193 ; CHECK_EXTEND_ROUND-NEXT: fcvt z1.h, p0/m, z1.d
194 ; CHECK_EXTEND_ROUND-NEXT: bsl z3.d, z3.d, z2.d, z4.d
195 ; CHECK_EXTEND_ROUND-NEXT: bsl z0.d, z0.d, z1.d, z4.d
198 %tmp0 = fptrunc <vscale x 4 x double> %b to <vscale x 4 x half>
199 …%r = call <vscale x 4 x half> @llvm.copysign.v4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %tm…
200 ret <vscale x 4 x half> %r
203 declare <vscale x 4 x half> @llvm.copysign.v4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0
211 ; CHECK-NEXT: bsl z0.d, z0.d, z1.d, z2.d
225 ; CHECK_NO_EXTEND_ROUND-NEXT: bsl z0.d, z0.d, z1.d, z3.d
236 ; CHECK_EXTEND_ROUND-NEXT: bsl z3.d, z3.d, z2.d, z4.d
237 ; CHECK_EXTEND_ROUND-NEXT: bsl z0.d, z0.d, z1.d, z4.d