Home
last modified time | relevance | path

Searched full:4 (Results 1 – 25 of 15562) sorted by relevance

12345678910>>...623

/llvm-project/llvm/test/CodeGen/AArch64/
H A Dminmax-of-minmax.ll4 ; There are 4 commuted variants (abbc/abcb/bcab/bcba) *
5 ; 4 predicate variants ([*][lg][te]) *
6 ; 4 min/max flavors (smin/smax/umin/umax) *
10 define <4 x i32> @smin_ab_bc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
13 ; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
14 ; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
15 ; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
17 %cmp_ab = icmp slt <4 x i32> %a, %b
18 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
19 %cmp_bc = icmp slt <4 x i32> %b, %c
[all …]
H A Ditofp-bf16.ll356 ; CHECK-NEXT: movi v2.4s, #127, msl #8
359 ; CHECK-NEXT: fcvtn2 v0.4s, v1.2d
360 ; CHECK-NEXT: movi v1.4s, #1
361 ; CHECK-NEXT: ushr v3.4s, v0.4s, #16
362 ; CHECK-NEXT: add v2.4s, v0.4s, v2.4s
364 ; CHECK-NEXT: fcmeq v3.4s, v0.4
[all...]
H A Dneon-sm4-sm3.ll4 define <4 x i32> @test_vsm3partw1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
7 ; CHECK-NEXT: sm3partw1 v0.4s, v1.4s, v2.4s
10 …%vsm3partw1.i = tail call <4 x i32> @llvm.aarch64.crypto.sm3partw1(<4 x i32> %a, <4 x i32> %b, <4 …
11 ret <4 x i32> %vsm3partw1.i
14 define <4 x i32> @test_vsm3partw2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
17 ; CHECK-NEXT: sm3partw2 v0.4s, v1.4s, v2.4s
20 …%vsm3partw2.i = tail call <4 x i32> @llvm.aarch64.crypto.sm3partw2(<4 x i32> %a, <4 x i32> %b, <4 …
21 ret <4 x i32> %vsm3partw2.i
24 define <4 x i32> @test_vsm3ss1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
27 ; CHECK-NEXT: sm3ss1 v0.4s, v0.4s, v1.4s, v2.4s
[all …]
/llvm-project/mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sm80-lt/
H A Dsparse-matmul-2-4-prune.mlir22 j floordiv 4 : dense,
23 j mod 4 : structured[2, 4]
84 // CHECK: ( 4, 1, 4, 1, 4, 1, 4, 1, 4, 1, 4, 1, 4,
[all...]
/llvm-project/llvm/test/CodeGen/X86/
H A D2008-07-19-movups-spills.ll7 @0 = external dso_local global <4 x float>, align 1 ; <ptr>:0 [#uses=2]
8 @1 = external dso_local global <4 x float>, align 1 ; <ptr>:1 [#uses=1]
9 @2 = external dso_local global <4 x float>, align 1 ; <ptr>:2 [#uses=1]
10 @3 = external dso_local global <4 x float>, align 1 ; <ptr>:3 [#uses=1]
11 @4 = external dso_local global <4 x float>, align 1 ; <ptr>:4 [#uses=1]
12 @5 = external dso_local global <4 x float>, align 1 ; <ptr>:5 [#uses=1]
13 @6 = external dso_local global <4 x float>, align 1 ; <ptr>:6 [#uses=1]
14 @7 = external dso_local global <4 x float>, align 1 ; <ptr>:7 [#uses=1]
15 @8 = external dso_local global <4 x float>, align 1 ; <ptr>:8 [#uses=1]
16 @9 = external dso_local global <4 x float>, align 1 ; <ptr>:9 [#uses=1]
[all …]
H A Dpr55648.ll7 ; CHECK-NEXT: .p2align 4
12 %tmp = load <4 x i16>, ptr poison, align 16
13 %tmp1 = icmp ne <4 x i16> %tmp, <i16 1, i16 1, i16 1, i16 1>
14 %tmp2 = load <4 x i16>, ptr poison, align 8
15 %tmp3 = icmp ne <4 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1>
16 %tmp4 = load <4 x i16>, ptr poison, align 16
17 %tmp5 = icmp ne <4 x i16> %tmp4, <i16 1, i16 1, i16 1, i16 1>
18 %tmp6 = load <4 x i16>, ptr poison, align 8
19 %tmp7 = icmp ne <4 x i16> %tmp6, <i16 1, i16 1, i16 1, i16 1>
20 %tmp8 = load <4
[all...]
H A D2007-04-24-VectorCrash.ll5 declare <4 x float> @llvm.x86.sse.add.ss(<4 x float>, <4 x float>)
9 …%and = and <4 x i32> bitcast (<4 x float> shufflevector (<4 x float> undef, <4 x float> undef, <4 …
10 or <4 x i32> zeroinitializer, %and
11 bitcast <4 x i32> %0 to <4 x float> ; <<4 x float>>:1 [#uses=1]
12 fsub <4 x float> %1, zeroinitializer ; <<4 x float>>:2 [#uses=1]
13 …fsub <4 x float> shufflevector (<4 x float> undef, <4 x float> undef, <4 x i32> zeroinitializer), …
14 …shufflevector <4 x float> zeroinitializer, <4 x float> %3, <4 x i32> < i32 0, i32 5, i32 6, i32 7 …
15 …shufflevector <4 x float> zeroinitializer, <4 x float> %4, <4 x i32> < i32 0, i32 5, i32 6, i32 7 …
16 …shufflevector <4 x float> zeroinitializer, <4 x float> %5, <4 x i32> < i32 0, i32 1, i32 2, i32 7 …
17 …shufflevector <4 x float> %6, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 …
[all …]
/llvm-project/compiler-rt/lib/xray/
H A Dxray_trampoline_powerpc64_asm.S4 .p2align 4
13 std 4, 40(1)
20 addi 4, 1, 96
21 stxsdx 1, 0, 4
22 addi 4, 1, 104
23 stxsdx 2, 0, 4
24 addi 4, 1, 112
25 stxsdx 3, 0, 4
26 addi 4, 1, 120
27 stxsdx 4, 0, 4
[all …]
/llvm-project/llvm/test/CodeGen/PowerPC/
H A Daix-insert-extract.ll6 define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
11 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
12 ret <4 x float> %vecins
15 define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
20 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3>
21 ret <4 x float> %vecins
24 define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
29 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3>
30 ret <4 x float> %vecins
33 define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
[all …]
H A D2007-03-30-SpillerCrash.ll5 %.sub7896 = getelementptr [4 x <4 x i32>], ptr null, i32 0, i32 0 ; <ptr> [#uses=24]
6 getelementptr [193 x [4 x <4 x float>]], ptr null, i32 0, i32 175, i32 3 ; <ptr>:2 [#uses=0]
7 getelementptr [193 x [4 x <4 x float>]], ptr null, i32 0, i32 174, i32 2 ; <ptr>:3 [#uses=0]
8 getelementptr [193 x [4 x <4 x float>]], ptr null, i32 0, i32 174, i32 3 ; <ptr>:4 [#uses=0]
9 getelementptr [193 x [4 x <4 x float>]], ptr null, i32 0, i32 173, i32 1 ; <ptr>:5 [#uses=0]
10 getelementptr [193 x [4 x <4 x float>]], ptr null, i32 0, i32 173, i32 2 ; <ptr>:6 [#uses=0]
11 getelementptr [193 x [4 x <4 x float>]], ptr null, i32 0, i32 173, i32 3 ; <ptr>:7 [#uses=0]
12 getelementptr [193 x [4 x <4 x float>]], ptr null, i32 0, i32 172, i32 1 ; <ptr>:8 [#uses=0]
13 getelementptr [193 x [4 x <4 x float>]], ptr null, i32 0, i32 172, i32 2 ; <ptr>:9 [#uses=0]
14 getelementptr [193 x [4 x <4 x float>]], ptr null, i32 0, i32 172, i32 3 ; <ptr>:10 [#uses=0]
[all …]
H A Dp9-xxinsertw-xxextractuw.ll6 define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
14 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
15 ret <4 x float> %vecins
18 define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
26 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3>
27 ret <4 x float> %vecins
30 define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
38 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3>
39 ret <4 x float> %vecins
42 define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
[all …]
H A Dconst-nonsplat-array-init.ll18 ; P8-BE-NEXT: ld 4, L..C0(2) # %const.0
19 ; P8-BE-NEXT: lxvw4x 0, 0, 4
20 ; P8-BE-NEXT: lis 4, 1029
21 ; P8-BE-NEXT: ori 4, 4, 1543
22 ; P8-BE-NEXT: stw 4, 16(3)
23 ; P8-BE-NEXT: li 4, 2057
25 ; P8-BE-NEXT: sth 4, 20(3)
30 ; P9-BE-NEXT: ld 4, L..C0(2) # %const.0
31 ; P9-BE-NEXT: lxv 0, 0(4)
[all...]
/llvm-project/llvm/test/CodeGen/Thumb2/
H A Dmve-vpt-blocks.ll4 declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)
6 define arm_aapcs_vfpcc <4 x i32> @vpt_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
13 %0 = icmp sge <4 x i32> %a, %c
14 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
15 ret <4 x i32> %1
18 define arm_aapcs_vfpcc <4 x i32> @vptt_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
27 %0 = icmp sge <4 x i32> %a, %c
28 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
29 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %1, <4 x i32> %c, <4 x …
30 ret <4 x i32> %2
[all …]
H A Dmve-gather-ind32-unscaled.ll4 define arm_aapcs_vfpcc <4 x i32> @zext_unscaled_i8_i32(ptr %base, ptr %offptr) {
11 %offs = load <4 x i32>, ptr %offptr, align 4
12 %ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs
13 …%gather = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> <i1 true, i…
14 %gather.zext = zext <4 x i8> %gather to <4 x i32>
15 ret <4 x i32> %gather.zext
18 define arm_aapcs_vfpcc <4 x i32> @sext_unscaled_i8_i32(ptr %base, ptr %offptr) {
25 %offs = load <4 x i32>, ptr %offptr, align 4
26 %ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs
27 …%gather = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> <i1 true, i…
[all …]
/llvm-project/llvm/test/Verifier/
H A Dintrinsic-arg-overloading-struct-ret.ll7 define { <4 x i64>, <4 x i32> } @test_ld2_ret(ptr %ptr) {
8 %res = call { <4 x i64>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32(ptr %ptr)
9 ret{ <4 x i64>, <4 x i32> } %res
11 declare { <4 x i64>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32(ptr %ptr)
15 define { <4 x i64>, <4 x i32> } @test_ld2lane_ret(ptr %ptr, <4 x i64> %a, <4 x i64> %b) {
16 …%res = call { <4 x i64>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i64(<4 x i64> %a, <4 x i64> %b, …
17 ret{ <4 x i64>, <4 x i32> } %res
19 declare { <4 x i64>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i64(<4 x i64>, <4 x i64>, i64, ptr)
23 define { <4 x i32>, <4 x i32> } @test_ld2lane_arg(ptr %ptr, <4 x i64> %a, <4 x i32> %b) {
24 …%res = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32(<4 x i64> %a, <4 x i32> %b, …
[all …]
/llvm-project/llvm/test/Transforms/InstCombine/
H A Dvec-binop-select.ll6 define <4 x i32> @and(<4 x i32> %x, <4 x i32> %y) {
8 ; CHECK-NEXT: [[R:%.*]] = and <4 x i32> [[X:%.*]], [[Y:%.*]]
9 ; CHECK-NEXT: ret <4 x i32> [[R]]
11 %sel1 = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
12 %sel2 = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 4, i32 1, i32 2, i32 7>
13 %r = and <4 x i32> %sel1, %sel2
14 ret <4 x i32> %r
17 define <vscale x 4 x i32> @vscaleand(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
19 ; CHECK-NEXT: [[TMP1:%.*]] = and <vscale x 4 x i32> [[X:%.*]], [[Y:%.*]]
20 …CK-NEXT: [[R:%.*]] = shufflevector <vscale x 4 x i32> [[TMP1]], <vscale x 4 x i32> poison, <vsc…
[all …]
H A Dvec-binop-select-inseltpoison.ll6 define <4 x i32> @and(<4 x i32> %x, <4 x i32> %y) {
8 ; CHECK-NEXT: [[R:%.*]] = and <4 x i32> [[X:%.*]], [[Y:%.*]]
9 ; CHECK-NEXT: ret <4 x i32> [[R]]
11 %sel1 = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
12 %sel2 = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 4, i32 1, i32 2, i32 7>
13 %r = and <4 x i32> %sel1, %sel2
14 ret <4 x i32> %r
17 define <vscale x 4 x i32> @vscaleand(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
19 ; CHECK-NEXT: [[TMP1:%.*]] = and <vscale x 4 x i32> [[X:%.*]], [[Y:%.*]]
20 …CK-NEXT: [[R:%.*]] = shufflevector <vscale x 4 x i32> [[TMP1]], <vscale x 4 x i32> poison, <vsc…
[all …]
H A Dvector-reverse.ll8 define <vscale x 4 x i32> @binop_reverse(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
10 ; CHECK-NEXT: [[ADD1:%.*]] = add nsw <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
11 ; CHECK-NEXT: [[ADD:%.*]] = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> [[ADD1]])
12 ; CHECK-NEXT: ret <vscale x 4 x i32> [[ADD]]
14 %a.rev = tail call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %a)
15 %b.rev = tail call <vscale x 4
[all...]
H A Dshuffle_select.ll7 define <4 x i32> @add(<4 x i32> %v) {
9 ; CHECK-NEXT: [[S:%.*]] = add <4 x i32> [[V:%.*]], <i32 11, i32 0, i32 13, i32 0>
10 ; CHECK-NEXT: ret <4 x i32> [[S]]
12 %b = add <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
13 %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
14 ret <4 x i32> %s
19 define <4
[all...]
H A Dshuffle_select-inseltpoison.ll7 define <4 x i32> @add(<4 x i32> %v) {
9 ; CHECK-NEXT: [[S:%.*]] = add <4 x i32> [[V:%.*]], <i32 11, i32 0, i32 13, i32 0>
10 ; CHECK-NEXT: ret <4 x i32> [[S]]
12 %b = add <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
13 %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
14 ret <4 x i32> %s
19 define <4
[all...]
H A Dshuffle-binop.ll4 define <4 x i8> @splat_binop_non_splat_x(<4 x i8> %x, <4 x i8> %y) {
6 ; CHECK-NEXT: [[XSPLAT:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> poison, <4 x i32> <i32 0, i32 2, i32 poison, i32 poison>
7 ; CHECK-NEXT: call void @use(<4 x i8> [[XSPLAT]])
8 ; CHECK-NEXT: [[B:%.*]] = add <4 x i8> [[XSPLAT]], [[Y:%.*]]
9 ; CHECK-NEXT: [[BSPLAT:%.*]] = shufflevector <4 x i8> [[B]], <4
[all...]
/llvm-project/llvm/test/CodeGen/RISCV/rvv/
H A Dundef-vp-ops.ll9 declare <4 x i32> @llvm.vp.load.v4i32.p0(ptr, <4 x i1>, i32)
11 define <4 x i32> @vload_v4i32_zero_evl(ptr %ptr, <4 x i1> %m) {
15 %v = call <4 x i32> @llvm.vp.load.v4i32.p0(ptr %ptr, <4 x i1> %m, i32 0)
16 ret <4 x i32> %v
19 define <4 x i32> @vload_v4i32_false_mask(ptr %ptr, i32 %evl) {
23 %v = call <4 x i32> @llvm.vp.load.v4i32.p0(ptr %ptr, <4
[all...]
/llvm-project/llvm/test/CodeGen/Hexagon/
H A Dstore-vector-pred.ll21 %v7 = lshr <128 x i8> %v6, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i
[all...]
/llvm-project/llvm/test/Transforms/InstSimplify/
H A Dshufflevector.ll4 define <4 x i32> @const_folding(<4 x i32> %x) {
6 ; CHECK-NEXT: ret <4 x i32> zeroinitializer
8 %shuf = shufflevector <4 x i32> %x, <4 x i32> zeroinitializer, <4 x i32> <i32 5, i32 4, i32 5, i32 4>
9 ret <4 x i32> %shuf
12 define <4
[all...]
/llvm-project/llvm/test/Analysis/BasicAA/
H A Dvscale.ll6 ; CHECK-DAG: MustAlias: <vscale x 4 x i32>* %alloc, <vscale x 4 x i32>* %gep1
7 ; CHECK-DAG: MayAlias: <vscale x 4 x i32>* %alloc, <vscale x 4 x i32>* %gep2
8 ; CHECK-DAG: MayAlias: <vscale x 4 x i32>* %gep1, <vscale x 4 x i32>* %gep2
10 %alloc = alloca <vscale x 4 x i32>
11 %gep1 = getelementptr <vscale x 4 x i32>, ptr %alloc, i64 0
12 %gep2 = getelementptr <vscale x 4 x i32>, ptr %alloc, i64 1
13 load <vscale x 4 x i32>, ptr %alloc
14 load <vscale x 4 x i32>, ptr %gep1
15 load <vscale x 4 x i32>, ptr %gep2
20 ; CHECK-DAG: MayAlias: <vscale x 4 x i32>* %alloc, <vscale x 4 x i32>* %gep1
[all …]

12345678910>>...623