1; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi \ 2; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-64 3; RUN: llc -mcpu=pwr9 -mtriple=powerpc-ibm-aix-xcoff -vec-extabi \ 4; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-32 5 6define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 7entry: 8; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_ 9; CHECK: xxsldwi 0, 35, 35, 3 10; CHECK: xxinsertw 34, 0, 0 11 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3> 12 ret <4 x float> %vecins 13} 14 15define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 16entry: 17; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_ 18; CHECK-NOT: xxsldwi 19; CHECK: xxinsertw 34, 35, 0 20 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3> 21 ret <4 x float> %vecins 22} 23 24define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 25entry: 26; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_ 27; CHECK: xxsldwi 0, 35, 35, 1 28; CHECK: xxinsertw 34, 0, 0 29 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3> 30 ret <4 x float> %vecins 31} 32 33define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 34entry: 35; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_ 36; CHECK: xxswapd 0, 35 37; CHECK: xxinsertw 34, 0, 0 38 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3> 39 ret <4 x float> %vecins 40} 41 42define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 43entry: 44; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_ 45; CHECK: xxsldwi 0, 35, 35, 3 46; CHECK: xxinsertw 34, 0, 4 47 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3> 48 ret <4 x float> %vecins 49} 50 51define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 52entry: 53; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_ 54; CHECK-NOT: xxsldwi 55; CHECK: xxinsertw 34, 35, 4 56 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3> 57 ret <4 x float> %vecins 58} 59 60define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 61entry: 62; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_ 63; CHECK: xxsldwi 0, 35, 35, 1 64; CHECK: xxinsertw 34, 0, 4 65 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3> 66 ret <4 x float> %vecins 67} 68 69define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 70entry: 71; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_ 72; CHECK: xxswapd 0, 35 73; CHECK: xxinsertw 34, 0, 4 74 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3> 75 ret <4 x float> %vecins 76} 77 78define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 79entry: 80; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_ 81; CHECK: xxsldwi 0, 35, 35, 3 82; CHECK: xxinsertw 34, 0, 8 83 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3> 84 ret <4 x float> %vecins 85} 86 87define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 88entry: 89; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_ 90; CHECK-NOT: xxsldwi 91; CHECK: xxinsertw 34, 35, 8 92 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3> 93 ret <4 x float> %vecins 94} 95 96define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 97entry: 98; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_ 99; CHECK: xxsldwi 0, 35, 35, 1 100; CHECK: xxinsertw 34, 0, 8 101 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3> 102 ret <4 x float> %vecins 103} 104 105define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 106entry: 107; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_ 108; CHECK: xxswapd 0, 35 109; CHECK: xxinsertw 34, 0, 8 110 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3> 111 ret <4 x float> %vecins 112} 113 114define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 115entry: 116; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_ 117; CHECK: xxsldwi 0, 35, 35, 3 118; CHECK: xxinsertw 34, 0, 12 119 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4> 120 ret <4 x float> %vecins 121} 122 123define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 124entry: 125; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_ 126; CHECK-NOT: xxsldwi 127; CHECK: xxinsertw 34, 35, 12 128 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5> 129 ret <4 x float> %vecins 130} 131 132define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 133entry: 134; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_ 135; CHECK: xxsldwi 0, 35, 35, 1 136; CHECK: xxinsertw 34, 0, 12 137 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6> 138 ret <4 x float> %vecins 139} 140 141define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 142entry: 143; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_ 144; CHECK: xxswapd 0, 35 145; CHECK: xxinsertw 34, 0, 12 146 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7> 147 ret <4 x float> %vecins 148} 149 150define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 151entry: 152; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_ 153; CHECK: xxsldwi 0, 35, 35, 3 154; CHECK: xxinsertw 34, 0, 0 155 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3> 156 ret <4 x i32> %vecins 157} 158 159define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 160entry: 161; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_ 162; CHECK-NOT: xxsldwi 163; CHECK: xxinsertw 34, 35, 0 164 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3> 165 ret <4 x i32> %vecins 166} 167 168define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 169entry: 170; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_ 171; CHECK: xxsldwi 0, 35, 35, 1 172; CHECK: xxinsertw 34, 0, 0 173 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3> 174 ret <4 x i32> %vecins 175} 176 177define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 178entry: 179; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_ 180; CHECK: xxswapd 0, 35 181; CHECK: xxinsertw 34, 0, 0 182 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3> 183 ret <4 x i32> %vecins 184} 185 186define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 187entry: 188; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_ 189; CHECK: xxsldwi 0, 35, 35, 3 190; CHECK: xxinsertw 34, 0, 4 191 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3> 192 ret <4 x i32> %vecins 193} 194 195define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 196entry: 197; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_ 198; CHECK-NOT: xxsldwi 199; CHECK: xxinsertw 34, 35, 4 200 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3> 201 ret <4 x i32> %vecins 202} 203 204define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 205entry: 206; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_ 207; CHECK: xxsldwi 0, 35, 35, 1 208; CHECK: xxinsertw 34, 0, 4 209 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3> 210 ret <4 x i32> %vecins 211} 212 213define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 214entry: 215; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_ 216; CHECK: xxswapd 0, 35 217; CHECK: xxinsertw 34, 0, 4 218 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3> 219 ret <4 x i32> %vecins 220} 221 222define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 223entry: 224; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_ 225; CHECK: xxsldwi 0, 35, 35, 3 226; CHECK: xxinsertw 34, 0, 8 227 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3> 228 ret <4 x i32> %vecins 229} 230 231define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 232entry: 233; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_ 234; CHECK-NOT: xxsldwi 235; CHECK: xxinsertw 34, 35, 8 236 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3> 237 ret <4 x i32> %vecins 238} 239 240define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 241entry: 242; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_ 243; CHECK: xxsldwi 0, 35, 35, 1 244; CHECK: xxinsertw 34, 0, 8 245 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3> 246 ret <4 x i32> %vecins 247} 248 249define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 250entry: 251; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_ 252; CHECK: xxswapd 0, 35 253; CHECK: xxinsertw 34, 0, 8 254 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3> 255 ret <4 x i32> %vecins 256} 257 258define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 259entry: 260; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_ 261; CHECK: xxsldwi 0, 35, 35, 3 262; CHECK: xxinsertw 34, 0, 12 263 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4> 264 ret <4 x i32> %vecins 265} 266 267define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 268entry: 269; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_ 270; CHECK-NOT: xxsldwi 271; CHECK: xxinsertw 34, 35, 12 272 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5> 273 ret <4 x i32> %vecins 274} 275 276define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 277entry: 278; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_ 279; CHECK: xxsldwi 0, 35, 35, 1 280; CHECK: xxinsertw 34, 0, 12 281 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6> 282 ret <4 x i32> %vecins 283} 284 285define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 286entry: 287; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_ 288; CHECK: xxswapd 0, 35 289; CHECK: xxinsertw 34, 0, 12 290 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7> 291 ret <4 x i32> %vecins 292} 293 294define float @_Z13testUiToFpExtILj0EEfDv4_j(<4 x i32> %a) { 295entry: 296; CHECK-64-LABEL: _Z13testUiToFpExtILj0EEfDv4_j 297; CHECK-64: xxextractuw 0, 34, 0 298; CHECK-64: xscvuxdsp 1, 0 299; CHECK-32-LABEL: _Z13testUiToFpExtILj0EEfDv4_j 300; CHECK-32: lfiwzx 0, 0, 3 301; CHECK-32: xscvuxdsp 1, 0 302 %vecext = extractelement <4 x i32> %a, i32 0 303 %conv = uitofp i32 %vecext to float 304 ret float %conv 305} 306 307define float @_Z13testUiToFpExtILj1EEfDv4_j(<4 x i32> %a) { 308entry: 309; CHECK-64-LABEL: _Z13testUiToFpExtILj1EEfDv4_j 310; CHECK-64: xxextractuw 0, 34, 4 311; CHECK-64: xscvuxdsp 1, 0 312; CHECK-32-LABEL: _Z13testUiToFpExtILj1EEfDv4_j 313; CHECK-32: lfiwzx 0, 0, 3 314; CHECK-32: xscvuxdsp 1, 0 315 %vecext = extractelement <4 x i32> %a, i32 1 316 %conv = uitofp i32 %vecext to float 317 ret float %conv 318} 319 320define float @_Z13testUiToFpExtILj2EEfDv4_j(<4 x i32> %a) { 321entry: 322; CHECK-64-LABEL: _Z13testUiToFpExtILj2EEfDv4_j 323; CHECK-64: xxextractuw 0, 34, 8 324; CHECK-64: xscvuxdsp 1, 0 325; CHECK-32-LABEL: _Z13testUiToFpExtILj2EEfDv4_j 326; CHECK-32: lfiwzx 0, 0, 3 327; CHECK-32: xscvuxdsp 1, 0 328 %vecext = extractelement <4 x i32> %a, i32 2 329 %conv = uitofp i32 %vecext to float 330 ret float %conv 331} 332 333define float @_Z13testUiToFpExtILj3EEfDv4_j(<4 x i32> %a) { 334entry: 335; CHECK-64-LABEL: _Z13testUiToFpExtILj3EEfDv4_j 336; CHECK-64: xxextractuw 0, 34, 12 337; CHECK-64: xscvuxdsp 1, 0 338; CHECK-32-LABEL: _Z13testUiToFpExtILj3EEfDv4_j 339; CHECK-32: lfiwzx 0, 0, 3 340; CHECK-32: xscvuxdsp 1, 0 341 %vecext = extractelement <4 x i32> %a, i32 3 342 %conv = uitofp i32 %vecext to float 343 ret float %conv 344} 345 346; Verify we generate optimal code for unsigned vector int elem extract followed 347; by conversion to double 348 349define double @conv2dlbTestui0(<4 x i32> %a) { 350entry: 351; CHECK-64-LABEL: conv2dlbTestui0 352; CHECK-64: xxextractuw [[CP64:[0-9]+]], 34, 0 353; CHECK-64: xscvuxddp 1, [[CP64]] 354; CHECK-32-LABEL: conv2dlbTestui0 355; CHECK-32: lfiwzx [[CP32:[0-9]+]], 0, 3 356; CHECK-32: xscvuxddp 1, [[CP32]] 357 %0 = extractelement <4 x i32> %a, i32 0 358 %1 = uitofp i32 %0 to double 359 ret double %1 360} 361 362define double @conv2dlbTestui1(<4 x i32> %a) { 363entry: 364; CHECK-64-LABEL: conv2dlbTestui1 365; CHECK-64: xxextractuw [[CP64:[0-9]+]], 34, 4 366; CHECK-64: xscvuxddp 1, [[CP64]] 367; CHECK-32-LABEL: conv2dlbTestui1 368; CHECK-32: lfiwzx [[CP32:[0-9]+]], 0, 3 369; CHECK-32: xscvuxddp 1, [[CP32]] 370 %0 = extractelement <4 x i32> %a, i32 1 371 %1 = uitofp i32 %0 to double 372 ret double %1 373} 374 375define double @conv2dlbTestui2(<4 x i32> %a) { 376entry: 377; CHECK-64-LABEL: conv2dlbTestui2 378; CHECK-64: xxextractuw [[CP64:[0-9]+]], 34, 8 379; CHECK-64: xscvuxddp 1, [[CP64]] 380; CHECK-32-LABEL: conv2dlbTestui2 381; CHECK-32: lfiwzx [[CP32:[0-9]+]], 0, 3 382; CHECK-32: xscvuxddp 1, [[CP32]] 383 %0 = extractelement <4 x i32> %a, i32 2 384 %1 = uitofp i32 %0 to double 385 ret double %1 386} 387 388define double @conv2dlbTestui3(<4 x i32> %a) { 389entry: 390; CHECK-64-LABEL: conv2dlbTestui3 391; CHECK-64: xxextractuw [[CP64:[0-9]+]], 34, 12 392; CHECK-64: xscvuxddp 1, [[CP64]] 393; CHECK-32-LABEL: conv2dlbTestui3 394; CHECK-32: lfiwzx [[CP32:[0-9]+]], 0, 3 395; CHECK-32: xscvuxddp 1, [[CP32]] 396 %0 = extractelement <4 x i32> %a, i32 3 397 %1 = uitofp i32 %0 to double 398 ret double %1 399} 400 401; verify we don't crash for variable elem extract 402define double @conv2dlbTestuiVar(<4 x i32> %a, i32 zeroext %elem) { 403entry: 404 %vecext = extractelement <4 x i32> %a, i32 %elem 405 %conv = uitofp i32 %vecext to double 406 ret double %conv 407} 408 409define <4 x float> @_Z10testInsEltILj0EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) { 410entry: 411; CHECK-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_ 412; CHECK: xscvdpspn 0, 1 413; CHECK: xxsldwi 0, 0, 0, 3 414; CHECK: xxinsertw 34, 0, 0 415 %vecins = insertelement <4 x float> %a, float %b, i32 0 416 ret <4 x float> %vecins 417} 418 419define <4 x float> @_Z10testInsEltILj1EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) { 420entry: 421; CHECK-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_ 422; CHECK: xscvdpspn 0, 1 423; CHECK: xxsldwi 0, 0, 0, 3 424; CHECK: xxinsertw 34, 0, 4 425 %vecins = insertelement <4 x float> %a, float %b, i32 1 426 ret <4 x float> %vecins 427} 428 429define <4 x float> @_Z10testInsEltILj2EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) { 430entry: 431; CHECK-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_ 432; CHECK: xscvdpspn 0, 1 433; CHECK: xxsldwi 0, 0, 0, 3 434; CHECK: xxinsertw 34, 0, 8 435 %vecins = insertelement <4 x float> %a, float %b, i32 2 436 ret <4 x float> %vecins 437} 438 439define <4 x float> @_Z10testInsEltILj3EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) { 440entry: 441; CHECK-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_ 442; CHECK: xscvdpspn 0, 1 443; CHECK: xxsldwi 0, 0, 0, 3 444; CHECK: xxinsertw 34, 0, 12 445 %vecins = insertelement <4 x float> %a, float %b, i32 3 446 ret <4 x float> %vecins 447} 448 449define <4 x i32> @_Z10testInsEltILj0EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) { 450entry: 451; CHECK-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_ 452; CHECK: mtfprwz 0, 3 453; CHECK: xxinsertw 34, 0, 0 454 %vecins = insertelement <4 x i32> %a, i32 %b, i32 0 455 ret <4 x i32> %vecins 456} 457 458define <4 x i32> @_Z10testInsEltILj1EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) { 459entry: 460; CHECK-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_ 461; CHECK: mtfprwz 0, 3 462; CHECK: xxinsertw 34, 0, 4 463 %vecins = insertelement <4 x i32> %a, i32 %b, i32 1 464 ret <4 x i32> %vecins 465} 466 467define <4 x i32> @_Z10testInsEltILj2EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) { 468entry: 469; CHECK-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_ 470; CHECK: mtfprwz 0, 3 471; CHECK: xxinsertw 34, 0, 8 472 %vecins = insertelement <4 x i32> %a, i32 %b, i32 2 473 ret <4 x i32> %vecins 474} 475 476define <4 x i32> @_Z10testInsEltILj3EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) { 477entry: 478; CHECK-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_ 479; CHECK: mtfprwz 0, 3 480; CHECK: xxinsertw 34, 0, 12 481 %vecins = insertelement <4 x i32> %a, i32 %b, i32 3 482 ret <4 x i32> %vecins 483} 484 485define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 486entry: 487; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_ 488; CHECK: xxsldwi 0, 35, 35, 3 489; CHECK: xxinsertw 34, 0, 0 490 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7> 491 ret <4 x float> %vecins 492} 493 494define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 495entry: 496; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_ 497; CHECK-NOT: xxsldwi 498; CHECK: xxinsertw 34, 35, 0 499 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7> 500 ret <4 x float> %vecins 501} 502 503define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 504entry: 505; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_ 506; CHECK: xxsldwi 0, 35, 35, 1 507; CHECK: xxinsertw 34, 0, 0 508 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7> 509 ret <4 x float> %vecins 510} 511 512define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 513entry: 514; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_ 515; CHECK: xxswapd 0, 35 516; CHECK: xxinsertw 34, 0, 0 517 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7> 518 ret <4 x float> %vecins 519} 520 521define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 522entry: 523; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_ 524; CHECK: xxsldwi 0, 35, 35, 3 525; CHECK: xxinsertw 34, 0, 4 526 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7> 527 ret <4 x float> %vecins 528} 529 530define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 531entry: 532; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_ 533; CHECK-NOT: xxsldwi 534; CHECK: xxinsertw 34, 35, 4 535 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7> 536 ret <4 x float> %vecins 537} 538 539define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 540entry: 541; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_ 542; CHECK: xxsldwi 0, 35, 35, 1 543; CHECK: xxinsertw 34, 0, 4 544 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7> 545 ret <4 x float> %vecins 546} 547 548define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 549entry: 550; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_ 551; CHECK: xxswapd 0, 35 552; CHECK: xxinsertw 34, 0, 4 553 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7> 554 ret <4 x float> %vecins 555} 556 557define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 558entry: 559; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_ 560; CHECK: xxsldwi 0, 35, 35, 3 561; CHECK: xxinsertw 34, 0, 8 562 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7> 563 ret <4 x float> %vecins 564} 565 566define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 567entry: 568; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_ 569; CHECK-NOT: xxsldwi 570; CHECK: xxinsertw 34, 35, 8 571 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7> 572 ret <4 x float> %vecins 573} 574 575define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 576entry: 577; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_ 578; CHECK: xxsldwi 0, 35, 35, 1 579; CHECK: xxinsertw 34, 0, 8 580 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7> 581 ret <4 x float> %vecins 582} 583 584define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 585entry: 586; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_ 587; CHECK: xxswapd 0, 35 588; CHECK: xxinsertw 34, 0, 8 589 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7> 590 ret <4 x float> %vecins 591} 592 593define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 594entry: 595; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_ 596; CHECK: xxsldwi 0, 35, 35, 3 597; CHECK: xxinsertw 34, 0, 12 598 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0> 599 ret <4 x float> %vecins 600} 601 602define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 603entry: 604; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_ 605; CHECK-NOT: xxsldwi 606; CHECK: xxinsertw 34, 35, 12 607 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1> 608 ret <4 x float> %vecins 609} 610 611define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 612entry: 613; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_ 614; CHECK: xxsldwi 0, 35, 35, 1 615; CHECK: xxinsertw 34, 0, 12 616 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2> 617 ret <4 x float> %vecins 618} 619 620define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 621entry: 622; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_ 623; CHECK: xxswapd 0, 35 624; CHECK: xxinsertw 34, 0, 12 625 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3> 626 ret <4 x float> %vecins 627} 628 629define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 630entry: 631; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_ 632; CHECK: xxsldwi 0, 35, 35, 3 633; CHECK: xxinsertw 34, 0, 0 634 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7> 635 ret <4 x i32> %vecins 636} 637 638define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 639entry: 640; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_ 641; CHECK-NOT: xxsldwi 642; CHECK: xxinsertw 34, 35, 0 643 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7> 644 ret <4 x i32> %vecins 645} 646 647define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 648entry: 649; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_ 650; CHECK: xxsldwi 0, 35, 35, 1 651; CHECK: xxinsertw 34, 0, 0 652 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7> 653 ret <4 x i32> %vecins 654} 655 656define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 657entry: 658; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_ 659; CHECK: xxswapd 0, 35 660; CHECK: xxinsertw 34, 0, 0 661 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7> 662 ret <4 x i32> %vecins 663} 664 665define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 666entry: 667; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_ 668; CHECK: xxsldwi 0, 35, 35, 3 669; CHECK: xxinsertw 34, 0, 4 670 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7> 671 ret <4 x i32> %vecins 672} 673 674define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 675entry: 676; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_ 677; CHECK-NOT: xxsldwi 678; CHECK: xxinsertw 34, 35, 4 679 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7> 680 ret <4 x i32> %vecins 681} 682 683define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 684entry: 685; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_ 686; CHECK: xxsldwi 0, 35, 35, 1 687; CHECK: xxinsertw 34, 0, 4 688 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7> 689 ret <4 x i32> %vecins 690} 691 692define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 693entry: 694; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_ 695; CHECK: xxswapd 0, 35 696; CHECK: xxinsertw 34, 0, 4 697 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7> 698 ret <4 x i32> %vecins 699} 700 701define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 702entry: 703; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_ 704; CHECK: xxsldwi 0, 35, 35, 3 705; CHECK: xxinsertw 34, 0, 8 706 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7> 707 ret <4 x i32> %vecins 708} 709 710define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 711entry: 712; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_ 713; CHECK-NOT: xxsldwi 714; CHECK: xxinsertw 34, 35, 8 715 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7> 716 ret <4 x i32> %vecins 717} 718 719define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 720entry: 721; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_ 722; CHECK: xxsldwi 0, 35, 35, 1 723; CHECK: xxinsertw 34, 0, 8 724 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7> 725 ret <4 x i32> %vecins 726} 727 728define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 729entry: 730; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_ 731; CHECK: xxswapd 0, 35 732; CHECK: xxinsertw 34, 0, 8 733 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7> 734 ret <4 x i32> %vecins 735} 736 737define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 738entry: 739; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_ 740; CHECK: xxsldwi 0, 35, 35, 3 741; CHECK: xxinsertw 34, 0, 12 742 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0> 743 ret <4 x i32> %vecins 744} 745 746define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 747entry: 748; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_ 749; CHECK-NOT: xxsldwi 750; CHECK: xxinsertw 34, 35, 12 751 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1> 752 ret <4 x i32> %vecins 753} 754 755define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 756entry: 757; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_ 758; CHECK: xxsldwi 0, 35, 35, 1 759; CHECK: xxinsertw 34, 0, 12 760 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2> 761 ret <4 x i32> %vecins 762} 763 764define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 765entry: 766; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_ 767; CHECK: xxswapd 0, 35 768; CHECK: xxinsertw 34, 0, 12 769 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3> 770 ret <4 x i32> %vecins 771} 772define <4 x float> @testSameVecEl0BE(<4 x float> %a) { 773entry: 774; CHECK-LABEL: testSameVecEl0BE 775; CHECK: xxinsertw 34, 34, 0 776 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 5, i32 1, i32 2, i32 3> 777 ret <4 x float> %vecins 778} 779define <4 x float> @testSameVecEl2BE(<4 x float> %a) { 780entry: 781; CHECK-LABEL: testSameVecEl2BE 782; CHECK: xxinsertw 34, 34, 8 783 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 5, i32 3> 784 ret <4 x float> %vecins 785} 786define <4 x float> @testSameVecEl3BE(<4 x float> %a) { 787entry: 788; CHECK-LABEL: testSameVecEl3BE 789; CHECK: xxinsertw 34, 34, 12 790 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 5> 791 ret <4 x float> %vecins 792} 793define <4 x float> @insertVarF(<4 x float> %a, float %f, i32 %el) { 794entry: 795; CHECK-LABEL: insertVarF 796; CHECK: stfsx 1, 797; CHECK: lxv 798 %vecins = insertelement <4 x float> %a, float %f, i32 %el 799 ret <4 x float> %vecins 800} 801define <4 x i32> @insertVarI(<4 x i32> %a, i32 %i, i32 %el) { 802entry: 803; CHECK-LABEL: insertVarI 804; CHECK: stwx 805; CHECK: lxv 806 %vecins = insertelement <4 x i32> %a, i32 %i, i32 %el 807 ret <4 x i32> %vecins 808} 809