1; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \ 2; RUN: -verify-machineinstrs < %s | FileCheck %s 3; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \ 4; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE 5 6define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 7entry: 8; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_ 9; CHECK: xxswapd 0, 35 10; CHECK: xxinsertw 34, 0, 12 11; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_ 12; CHECK-BE: xxsldwi 0, 35, 35, 3 13; CHECK-BE: xxinsertw 34, 0, 0 14 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3> 15 ret <4 x float> %vecins 16} 17 18define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 19entry: 20; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_ 21; CHECK: xxsldwi 0, 35, 35, 1 22; CHECK: xxinsertw 34, 0, 12 23; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_ 24; CHECK-BE-NOT: xxsldwi 25; CHECK-BE: xxinsertw 34, 35, 0 26 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3> 27 ret <4 x float> %vecins 28} 29 30define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 31entry: 32; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_ 33; CHECK-NOT: xxsldwi 34; CHECK: xxinsertw 34, 35, 12 35; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_ 36; CHECK-BE: xxsldwi 0, 35, 35, 1 37; CHECK-BE: xxinsertw 34, 0, 0 38 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3> 39 ret <4 x float> %vecins 40} 41 42define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 43entry: 44; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_ 45; CHECK: xxsldwi 0, 35, 35, 3 46; CHECK: xxinsertw 34, 0, 12 47; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_ 48; CHECK-BE: xxswapd 0, 35 49; CHECK-BE: xxinsertw 34, 0, 0 50 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3> 51 ret <4 x float> %vecins 52} 53 54define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 55entry: 56; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_ 57; CHECK: xxswapd 0, 35 58; CHECK: xxinsertw 34, 0, 8 59; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_ 60; CHECK-BE: xxsldwi 0, 35, 35, 3 61; CHECK-BE: xxinsertw 34, 0, 4 62 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3> 63 ret <4 x float> %vecins 64} 65 66define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 67entry: 68; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_ 69; CHECK: xxsldwi 0, 35, 35, 1 70; CHECK: xxinsertw 34, 0, 8 71; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_ 72; CHECK-BE-NOT: xxsldwi 73; CHECK-BE: xxinsertw 34, 35, 4 74 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3> 75 ret <4 x float> %vecins 76} 77 78define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 79entry: 80; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_ 81; CHECK-NOT: xxsldwi 82; CHECK: xxinsertw 34, 35, 8 83; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_ 84; CHECK-BE: xxsldwi 0, 35, 35, 1 85; CHECK-BE: xxinsertw 34, 0, 4 86 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3> 87 ret <4 x float> %vecins 88} 89 90define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 91entry: 92; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_ 93; CHECK: xxsldwi 0, 35, 35, 3 94; CHECK: xxinsertw 34, 0, 8 95; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_ 96; CHECK-BE: xxswapd 0, 35 97; CHECK-BE: xxinsertw 34, 0, 4 98 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3> 99 ret <4 x float> %vecins 100} 101 102define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 103entry: 104; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_ 105; CHECK: xxswapd 0, 35 106; CHECK: xxinsertw 34, 0, 4 107; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_ 108; CHECK-BE: xxsldwi 0, 35, 35, 3 109; CHECK-BE: xxinsertw 34, 0, 8 110 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3> 111 ret <4 x float> %vecins 112} 113 114define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 115entry: 116; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_ 117; CHECK: xxsldwi 0, 35, 35, 1 118; CHECK: xxinsertw 34, 0, 4 119; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_ 120; CHECK-BE-NOT: xxsldwi 121; CHECK-BE: xxinsertw 34, 35, 8 122 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3> 123 ret <4 x float> %vecins 124} 125 126define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 127entry: 128; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_ 129; CHECK-NOT: xxsldwi 130; CHECK: xxinsertw 34, 35, 4 131; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_ 132; CHECK-BE: xxsldwi 0, 35, 35, 1 133; CHECK-BE: xxinsertw 34, 0, 8 134 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3> 135 ret <4 x float> %vecins 136} 137 138define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 139entry: 140; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_ 141; CHECK: xxsldwi 0, 35, 35, 3 142; CHECK: xxinsertw 34, 0, 4 143; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_ 144; CHECK-BE: xxswapd 0, 35 145; CHECK-BE: xxinsertw 34, 0, 8 146 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3> 147 ret <4 x float> %vecins 148} 149 150define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 151entry: 152; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_ 153; CHECK: xxswapd 0, 35 154; CHECK: xxinsertw 34, 0, 0 155; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_ 156; CHECK-BE: xxsldwi 0, 35, 35, 3 157; CHECK-BE: xxinsertw 34, 0, 12 158 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4> 159 ret <4 x float> %vecins 160} 161 162define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 163entry: 164; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_ 165; CHECK: xxsldwi 0, 35, 35, 1 166; CHECK: xxinsertw 34, 0, 0 167; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_ 168; CHECK-BE-NOT: xxsldwi 169; CHECK-BE: xxinsertw 34, 35, 12 170 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5> 171 ret <4 x float> %vecins 172} 173 174define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 175entry: 176; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_ 177; CHECK-NOT: xxsldwi 178; CHECK: xxinsertw 34, 35, 0 179; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_ 180; CHECK-BE: xxsldwi 0, 35, 35, 1 181; CHECK-BE: xxinsertw 34, 0, 12 182 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6> 183 ret <4 x float> %vecins 184} 185 186define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 187entry: 188; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_ 189; CHECK: xxsldwi 0, 35, 35, 3 190; CHECK: xxinsertw 34, 0, 0 191; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_ 192; CHECK-BE: xxswapd 0, 35 193; CHECK-BE: xxinsertw 34, 0, 12 194 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7> 195 ret <4 x float> %vecins 196} 197 198define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 199entry: 200; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_ 201; CHECK: xxswapd 0, 35 202; CHECK: xxinsertw 34, 0, 12 203; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_ 204; CHECK-BE: xxsldwi 0, 35, 35, 3 205; CHECK-BE: xxinsertw 34, 0, 0 206 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3> 207 ret <4 x i32> %vecins 208} 209 210define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 211entry: 212; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_ 213; CHECK: xxsldwi 0, 35, 35, 1 214; CHECK: xxinsertw 34, 0, 12 215; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_ 216; CHECK-BE-NOT: xxsldwi 217; CHECK-BE: xxinsertw 34, 35, 0 218 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3> 219 ret <4 x i32> %vecins 220} 221 222define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 223entry: 224; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_ 225; CHECK-NOT: xxsldwi 226; CHECK: xxinsertw 34, 35, 12 227; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_ 228; CHECK-BE: xxsldwi 0, 35, 35, 1 229; CHECK-BE: xxinsertw 34, 0, 0 230 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3> 231 ret <4 x i32> %vecins 232} 233 234define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 235entry: 236; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_ 237; CHECK: xxsldwi 0, 35, 35, 3 238; CHECK: xxinsertw 34, 0, 12 239; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_ 240; CHECK-BE: xxswapd 0, 35 241; CHECK-BE: xxinsertw 34, 0, 0 242 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3> 243 ret <4 x i32> %vecins 244} 245 246define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 247entry: 248; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_ 249; CHECK: xxswapd 0, 35 250; CHECK: xxinsertw 34, 0, 8 251; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_ 252; CHECK-BE: xxsldwi 0, 35, 35, 3 253; CHECK-BE: xxinsertw 34, 0, 4 254 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3> 255 ret <4 x i32> %vecins 256} 257 258define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 259entry: 260; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_ 261; CHECK: xxsldwi 0, 35, 35, 1 262; CHECK: xxinsertw 34, 0, 8 263; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_ 264; CHECK-BE-NOT: xxsldwi 265; CHECK-BE: xxinsertw 34, 35, 4 266 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3> 267 ret <4 x i32> %vecins 268} 269 270define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 271entry: 272; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_ 273; CHECK-NOT: xxsldwi 274; CHECK: xxinsertw 34, 35, 8 275; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_ 276; CHECK-BE: xxsldwi 0, 35, 35, 1 277; CHECK-BE: xxinsertw 34, 0, 4 278 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3> 279 ret <4 x i32> %vecins 280} 281 282define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 283entry: 284; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_ 285; CHECK: xxsldwi 0, 35, 35, 3 286; CHECK: xxinsertw 34, 0, 8 287; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_ 288; CHECK-BE: xxswapd 0, 35 289; CHECK-BE: xxinsertw 34, 0, 4 290 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3> 291 ret <4 x i32> %vecins 292} 293 294define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 295entry: 296; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_ 297; CHECK: xxswapd 0, 35 298; CHECK: xxinsertw 34, 0, 4 299; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_ 300; CHECK-BE: xxsldwi 0, 35, 35, 3 301; CHECK-BE: xxinsertw 34, 0, 8 302 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3> 303 ret <4 x i32> %vecins 304} 305 306define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 307entry: 308; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_ 309; CHECK: xxsldwi 0, 35, 35, 1 310; CHECK: xxinsertw 34, 0, 4 311; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_ 312; CHECK-BE-NOT: xxsldwi 313; CHECK-BE: xxinsertw 34, 35, 8 314 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3> 315 ret <4 x i32> %vecins 316} 317 318define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 319entry: 320; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_ 321; CHECK-NOT: xxsldwi 322; CHECK: xxinsertw 34, 35, 4 323; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_ 324; CHECK-BE: xxsldwi 0, 35, 35, 1 325; CHECK-BE: xxinsertw 34, 0, 8 326 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3> 327 ret <4 x i32> %vecins 328} 329 330define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 331entry: 332; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_ 333; CHECK: xxsldwi 0, 35, 35, 3 334; CHECK: xxinsertw 34, 0, 4 335; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_ 336; CHECK-BE: xxswapd 0, 35 337; CHECK-BE: xxinsertw 34, 0, 8 338 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3> 339 ret <4 x i32> %vecins 340} 341 342define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 343entry: 344; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_ 345; CHECK: xxswapd 0, 35 346; CHECK: xxinsertw 34, 0, 0 347; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_ 348; CHECK-BE: xxsldwi 0, 35, 35, 3 349; CHECK-BE: xxinsertw 34, 0, 12 350 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4> 351 ret <4 x i32> %vecins 352} 353 354define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 355entry: 356; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_ 357; CHECK: xxsldwi 0, 35, 35, 1 358; CHECK: xxinsertw 34, 0, 0 359; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_ 360; CHECK-BE-NOT: xxsldwi 361; CHECK-BE: xxinsertw 34, 35, 12 362 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5> 363 ret <4 x i32> %vecins 364} 365 366define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 367entry: 368; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_ 369; CHECK-NOT: xxsldwi 370; CHECK: xxinsertw 34, 35, 0 371; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_ 372; CHECK-BE: xxsldwi 0, 35, 35, 1 373; CHECK-BE: xxinsertw 34, 0, 12 374 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6> 375 ret <4 x i32> %vecins 376} 377 378define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 379entry: 380; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_ 381; CHECK: xxsldwi 0, 35, 35, 3 382; CHECK: xxinsertw 34, 0, 0 383; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_ 384; CHECK-BE: xxswapd 0, 35 385; CHECK-BE: xxinsertw 34, 0, 12 386 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7> 387 ret <4 x i32> %vecins 388} 389 390define float @_Z13testUiToFpExtILj0EEfDv4_j(<4 x i32> %a) { 391entry: 392; CHECK-LABEL: _Z13testUiToFpExtILj0EEfDv4_j 393; CHECK: xxextractuw 0, 34, 12 394; CHECK: xscvuxdsp 1, 0 395; CHECK-BE-LABEL: _Z13testUiToFpExtILj0EEfDv4_j 396; CHECK-BE: xxextractuw 0, 34, 0 397; CHECK-BE: xscvuxdsp 1, 0 398 %vecext = extractelement <4 x i32> %a, i32 0 399 %conv = uitofp i32 %vecext to float 400 ret float %conv 401} 402 403define float @_Z13testUiToFpExtILj1EEfDv4_j(<4 x i32> %a) { 404entry: 405; CHECK-LABEL: _Z13testUiToFpExtILj1EEfDv4_j 406; CHECK: xxextractuw 0, 34, 8 407; CHECK: xscvuxdsp 1, 0 408; CHECK-BE-LABEL: _Z13testUiToFpExtILj1EEfDv4_j 409; CHECK-BE: xxextractuw 0, 34, 4 410; CHECK-BE: xscvuxdsp 1, 0 411 %vecext = extractelement <4 x i32> %a, i32 1 412 %conv = uitofp i32 %vecext to float 413 ret float %conv 414} 415 416define float @_Z13testUiToFpExtILj2EEfDv4_j(<4 x i32> %a) { 417entry: 418; CHECK-LABEL: _Z13testUiToFpExtILj2EEfDv4_j 419; CHECK: xxextractuw 0, 34, 4 420; CHECK: xscvuxdsp 1, 0 421; CHECK-BE-LABEL: _Z13testUiToFpExtILj2EEfDv4_j 422; CHECK-BE: xxextractuw 0, 34, 8 423; CHECK-BE: xscvuxdsp 1, 0 424 %vecext = extractelement <4 x i32> %a, i32 2 425 %conv = uitofp i32 %vecext to float 426 ret float %conv 427} 428 429define float @_Z13testUiToFpExtILj3EEfDv4_j(<4 x i32> %a) { 430entry: 431; CHECK-LABEL: _Z13testUiToFpExtILj3EEfDv4_j 432; CHECK: xxextractuw 0, 34, 0 433; CHECK: xscvuxdsp 1, 0 434; CHECK-BE-LABEL: _Z13testUiToFpExtILj3EEfDv4_j 435; CHECK-BE: xxextractuw 0, 34, 12 436; CHECK-BE: xscvuxdsp 1, 0 437 %vecext = extractelement <4 x i32> %a, i32 3 438 %conv = uitofp i32 %vecext to float 439 ret float %conv 440} 441 442; Verify we generate optimal code for unsigned vector int elem extract followed 443; by conversion to double 444 445define double @conv2dlbTestui0(<4 x i32> %a) { 446entry: 447; CHECK-LABEL: conv2dlbTestui0 448; CHECK: xxextractuw [[SW:[0-9]+]], 34, 12 449; CHECK: xscvuxddp 1, [[SW]] 450; CHECK-BE-LABEL: conv2dlbTestui0 451; CHECK-BE: xxextractuw [[CP:[0-9]+]], 34, 0 452; CHECK-BE: xscvuxddp 1, [[CP]] 453 %0 = extractelement <4 x i32> %a, i32 0 454 %1 = uitofp i32 %0 to double 455 ret double %1 456} 457 458define double @conv2dlbTestui1(<4 x i32> %a) { 459entry: 460; CHECK-LABEL: conv2dlbTestui1 461; CHECK: xxextractuw [[SW:[0-9]+]], 34, 8 462; CHECK: xscvuxddp 1, [[SW]] 463; CHECK-BE-LABEL: conv2dlbTestui1 464; CHECK-BE: xxextractuw [[CP:[0-9]+]], 34, 4 465; CHECK-BE: xscvuxddp 1, [[CP]] 466 %0 = extractelement <4 x i32> %a, i32 1 467 %1 = uitofp i32 %0 to double 468 ret double %1 469} 470 471define double @conv2dlbTestui2(<4 x i32> %a) { 472entry: 473; CHECK-LABEL: conv2dlbTestui2 474; CHECK: xxextractuw [[SW:[0-9]+]], 34, 4 475; CHECK: xscvuxddp 1, [[SW]] 476; CHECK-BE-LABEL: conv2dlbTestui2 477; CHECK-BE: xxextractuw [[CP:[0-9]+]], 34, 8 478; CHECK-BE: xscvuxddp 1, [[CP]] 479 %0 = extractelement <4 x i32> %a, i32 2 480 %1 = uitofp i32 %0 to double 481 ret double %1 482} 483 484define double @conv2dlbTestui3(<4 x i32> %a) { 485entry: 486; CHECK-LABEL: conv2dlbTestui3 487; CHECK: xxextractuw [[SW:[0-9]+]], 34, 0 488; CHECK: xscvuxddp 1, [[SW]] 489; CHECK-BE-LABEL: conv2dlbTestui3 490; CHECK-BE: xxextractuw [[CP:[0-9]+]], 34, 12 491; CHECK-BE: xscvuxddp 1, [[CP]] 492 %0 = extractelement <4 x i32> %a, i32 3 493 %1 = uitofp i32 %0 to double 494 ret double %1 495} 496 497; verify we don't crash for variable elem extract 498define double @conv2dlbTestuiVar(<4 x i32> %a, i32 zeroext %elem) { 499entry: 500 %vecext = extractelement <4 x i32> %a, i32 %elem 501 %conv = uitofp i32 %vecext to double 502 ret double %conv 503} 504 505define <4 x float> @_Z10testInsEltILj0EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) { 506entry: 507; CHECK-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_ 508; CHECK: xscvdpspn 0, 1 509; CHECK: xxinsertw 34, 0, 12 510; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_ 511; CHECK-BE: xscvdpspn 0, 1 512; CHECK-BE: xxinsertw 34, 0, 0 513 %vecins = insertelement <4 x float> %a, float %b, i32 0 514 ret <4 x float> %vecins 515} 516 517define <4 x float> @_Z10testInsEltILj1EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) { 518entry: 519; CHECK-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_ 520; CHECK: xscvdpspn 0, 1 521; CHECK: xxinsertw 34, 0, 8 522; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_ 523; CHECK-BE: xscvdpspn 0, 1 524; CHECK-BE: xxinsertw 34, 0, 4 525 %vecins = insertelement <4 x float> %a, float %b, i32 1 526 ret <4 x float> %vecins 527} 528 529define <4 x float> @_Z10testInsEltILj2EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) { 530entry: 531; CHECK-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_ 532; CHECK: xscvdpspn 0, 1 533; CHECK: xxinsertw 34, 0, 4 534; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_ 535; CHECK-BE: xscvdpspn 0, 1 536; CHECK-BE: xxinsertw 34, 0, 8 537 %vecins = insertelement <4 x float> %a, float %b, i32 2 538 ret <4 x float> %vecins 539} 540 541define <4 x float> @_Z10testInsEltILj3EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) { 542entry: 543; CHECK-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_ 544; CHECK: xscvdpspn 0, 1 545; CHECK: xxinsertw 34, 0, 0 546; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_ 547; CHECK-BE: xscvdpspn 0, 1 548; CHECK-BE: xxinsertw 34, 0, 12 549 %vecins = insertelement <4 x float> %a, float %b, i32 3 550 ret <4 x float> %vecins 551} 552 553define <4 x i32> @_Z10testInsEltILj0EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) { 554entry: 555; CHECK-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_ 556; CHECK: mtfprwz 0, 5 557; CHECK: xxinsertw 34, 0, 12 558; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_ 559; CHECK-BE: mtfprwz 0, 5 560; CHECK-BE: xxinsertw 34, 0, 0 561 %vecins = insertelement <4 x i32> %a, i32 %b, i32 0 562 ret <4 x i32> %vecins 563} 564 565define <4 x i32> @_Z10testInsEltILj1EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) { 566entry: 567; CHECK-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_ 568; CHECK: mtfprwz 0, 5 569; CHECK: xxinsertw 34, 0, 8 570; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_ 571; CHECK-BE: mtfprwz 0, 5 572; CHECK-BE: xxinsertw 34, 0, 4 573 %vecins = insertelement <4 x i32> %a, i32 %b, i32 1 574 ret <4 x i32> %vecins 575} 576 577define <4 x i32> @_Z10testInsEltILj2EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) { 578entry: 579; CHECK-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_ 580; CHECK: mtfprwz 0, 5 581; CHECK: xxinsertw 34, 0, 4 582; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_ 583; CHECK-BE: mtfprwz 0, 5 584; CHECK-BE: xxinsertw 34, 0, 8 585 %vecins = insertelement <4 x i32> %a, i32 %b, i32 2 586 ret <4 x i32> %vecins 587} 588 589define <4 x i32> @_Z10testInsEltILj3EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) { 590entry: 591; CHECK-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_ 592; CHECK: mtfprwz 0, 5 593; CHECK: xxinsertw 34, 0, 0 594; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_ 595; CHECK-BE: mtfprwz 0, 5 596; CHECK-BE: xxinsertw 34, 0, 12 597 %vecins = insertelement <4 x i32> %a, i32 %b, i32 3 598 ret <4 x i32> %vecins 599} 600 601define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 602entry: 603; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_ 604; CHECK: xxswapd 0, 35 605; CHECK: xxinsertw 34, 0, 12 606; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_ 607; CHECK-BE: xxsldwi 0, 35, 35, 3 608; CHECK-BE: xxinsertw 34, 0, 0 609 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7> 610 ret <4 x float> %vecins 611} 612 613define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 614entry: 615; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_ 616; CHECK: xxsldwi 0, 35, 35, 1 617; CHECK: xxinsertw 34, 0, 12 618; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_ 619; CHECK-BE-NOT: xxsldwi 620; CHECK-BE: xxinsertw 34, 35, 0 621 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7> 622 ret <4 x float> %vecins 623} 624 625define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 626entry: 627; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_ 628; CHECK-NOT: xxsldwi 629; CHECK: xxinsertw 34, 35, 12 630; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_ 631; CHECK-BE: xxsldwi 0, 35, 35, 1 632; CHECK-BE: xxinsertw 34, 0, 0 633 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7> 634 ret <4 x float> %vecins 635} 636 637define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 638entry: 639; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_ 640; CHECK: xxsldwi 0, 35, 35, 3 641; CHECK: xxinsertw 34, 0, 12 642; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_ 643; CHECK-BE: xxswapd 0, 35 644; CHECK-BE: xxinsertw 34, 0, 0 645 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7> 646 ret <4 x float> %vecins 647} 648 649define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 650entry: 651; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_ 652; CHECK: xxswapd 0, 35 653; CHECK: xxinsertw 34, 0, 8 654; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_ 655; CHECK-BE: xxsldwi 0, 35, 35, 3 656; CHECK-BE: xxinsertw 34, 0, 4 657 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7> 658 ret <4 x float> %vecins 659} 660 661define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 662entry: 663; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_ 664; CHECK: xxsldwi 0, 35, 35, 1 665; CHECK: xxinsertw 34, 0, 8 666; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_ 667; CHECK-BE-NOT: xxsldwi 668; CHECK-BE: xxinsertw 34, 35, 4 669 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7> 670 ret <4 x float> %vecins 671} 672 673define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 674entry: 675; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_ 676; CHECK-NOT: xxsldwi 677; CHECK: xxinsertw 34, 35, 8 678; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_ 679; CHECK-BE: xxsldwi 0, 35, 35, 1 680; CHECK-BE: xxinsertw 34, 0, 4 681 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7> 682 ret <4 x float> %vecins 683} 684 685define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 686entry: 687; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_ 688; CHECK: xxsldwi 0, 35, 35, 3 689; CHECK: xxinsertw 34, 0, 8 690; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_ 691; CHECK-BE: xxswapd 0, 35 692; CHECK-BE: xxinsertw 34, 0, 4 693 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7> 694 ret <4 x float> %vecins 695} 696 697define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 698entry: 699; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_ 700; CHECK: xxswapd 0, 35 701; CHECK: xxinsertw 34, 0, 4 702; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_ 703; CHECK-BE: xxsldwi 0, 35, 35, 3 704; CHECK-BE: xxinsertw 34, 0, 8 705 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7> 706 ret <4 x float> %vecins 707} 708 709define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 710entry: 711; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_ 712; CHECK: xxsldwi 0, 35, 35, 1 713; CHECK: xxinsertw 34, 0, 4 714; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_ 715; CHECK-BE-NOT: xxsldwi 716; CHECK-BE: xxinsertw 34, 35, 8 717 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7> 718 ret <4 x float> %vecins 719} 720 721define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 722entry: 723; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_ 724; CHECK-NOT: xxsldwi 725; CHECK: xxinsertw 34, 35, 4 726; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_ 727; CHECK-BE: xxsldwi 0, 35, 35, 1 728; CHECK-BE: xxinsertw 34, 0, 8 729 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7> 730 ret <4 x float> %vecins 731} 732 733define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 734entry: 735; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_ 736; CHECK: xxsldwi 0, 35, 35, 3 737; CHECK: xxinsertw 34, 0, 4 738; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_ 739; CHECK-BE: xxswapd 0, 35 740; CHECK-BE: xxinsertw 34, 0, 8 741 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7> 742 ret <4 x float> %vecins 743} 744 745define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 746entry: 747; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_ 748; CHECK: xxswapd 0, 35 749; CHECK: xxinsertw 34, 0, 0 750; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_ 751; CHECK-BE: xxsldwi 0, 35, 35, 3 752; CHECK-BE: xxinsertw 34, 0, 12 753 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0> 754 ret <4 x float> %vecins 755} 756 757define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 758entry: 759; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_ 760; CHECK: xxsldwi 0, 35, 35, 1 761; CHECK: xxinsertw 34, 0, 0 762; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_ 763; CHECK-BE-NOT: xxsldwi 764; CHECK-BE: xxinsertw 34, 35, 12 765 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1> 766 ret <4 x float> %vecins 767} 768 769define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 770entry: 771; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_ 772; CHECK-NOT: xxsldwi 773; CHECK: xxinsertw 34, 35, 0 774; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_ 775; CHECK-BE: xxsldwi 0, 35, 35, 1 776; CHECK-BE: xxinsertw 34, 0, 12 777 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2> 778 ret <4 x float> %vecins 779} 780 781define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 782entry: 783; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_ 784; CHECK: xxsldwi 0, 35, 35, 3 785; CHECK: xxinsertw 34, 0, 0 786; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_ 787; CHECK-BE: xxswapd 0, 35 788; CHECK-BE: xxinsertw 34, 0, 12 789 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3> 790 ret <4 x float> %vecins 791} 792 793define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 794entry: 795; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_ 796; CHECK: xxswapd 0, 35 797; CHECK: xxinsertw 34, 0, 12 798; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_ 799; CHECK-BE: xxsldwi 0, 35, 35, 3 800; CHECK-BE: xxinsertw 34, 0, 0 801 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7> 802 ret <4 x i32> %vecins 803} 804 805define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 806entry: 807; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_ 808; CHECK: xxsldwi 0, 35, 35, 1 809; CHECK: xxinsertw 34, 0, 12 810; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_ 811; CHECK-BE-NOT: xxsldwi 812; CHECK-BE: xxinsertw 34, 35, 0 813 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7> 814 ret <4 x i32> %vecins 815} 816 817define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 818entry: 819; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_ 820; CHECK-NOT: xxsldwi 821; CHECK: xxinsertw 34, 35, 12 822; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_ 823; CHECK-BE: xxsldwi 0, 35, 35, 1 824; CHECK-BE: xxinsertw 34, 0, 0 825 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7> 826 ret <4 x i32> %vecins 827} 828 829define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 830entry: 831; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_ 832; CHECK: xxsldwi 0, 35, 35, 3 833; CHECK: xxinsertw 34, 0, 12 834; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_ 835; CHECK-BE: xxswapd 0, 35 836; CHECK-BE: xxinsertw 34, 0, 0 837 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7> 838 ret <4 x i32> %vecins 839} 840 841define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 842entry: 843; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_ 844; CHECK: xxswapd 0, 35 845; CHECK: xxinsertw 34, 0, 8 846; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_ 847; CHECK-BE: xxsldwi 0, 35, 35, 3 848; CHECK-BE: xxinsertw 34, 0, 4 849 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7> 850 ret <4 x i32> %vecins 851} 852 853define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 854entry: 855; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_ 856; CHECK: xxsldwi 0, 35, 35, 1 857; CHECK: xxinsertw 34, 0, 8 858; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_ 859; CHECK-BE-NOT: xxsldwi 860; CHECK-BE: xxinsertw 34, 35, 4 861 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7> 862 ret <4 x i32> %vecins 863} 864 865define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 866entry: 867; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_ 868; CHECK-NOT: xxsldwi 869; CHECK: xxinsertw 34, 35, 8 870; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_ 871; CHECK-BE: xxsldwi 0, 35, 35, 1 872; CHECK-BE: xxinsertw 34, 0, 4 873 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7> 874 ret <4 x i32> %vecins 875} 876 877define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 878entry: 879; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_ 880; CHECK: xxsldwi 0, 35, 35, 3 881; CHECK: xxinsertw 34, 0, 8 882; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_ 883; CHECK-BE: xxswapd 0, 35 884; CHECK-BE: xxinsertw 34, 0, 4 885 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7> 886 ret <4 x i32> %vecins 887} 888 889define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 890entry: 891; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_ 892; CHECK: xxswapd 0, 35 893; CHECK: xxinsertw 34, 0, 4 894; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_ 895; CHECK-BE: xxsldwi 0, 35, 35, 3 896; CHECK-BE: xxinsertw 34, 0, 8 897 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7> 898 ret <4 x i32> %vecins 899} 900 901define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 902entry: 903; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_ 904; CHECK: xxsldwi 0, 35, 35, 1 905; CHECK: xxinsertw 34, 0, 4 906; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_ 907; CHECK-BE-NOT: xxsldwi 908; CHECK-BE: xxinsertw 34, 35, 8 909 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7> 910 ret <4 x i32> %vecins 911} 912 913define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 914entry: 915; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_ 916; CHECK-NOT: xxsldwi 917; CHECK: xxinsertw 34, 35, 4 918; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_ 919; CHECK-BE: xxsldwi 0, 35, 35, 1 920; CHECK-BE: xxinsertw 34, 0, 8 921 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7> 922 ret <4 x i32> %vecins 923} 924 925define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 926entry: 927; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_ 928; CHECK: xxsldwi 0, 35, 35, 3 929; CHECK: xxinsertw 34, 0, 4 930; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_ 931; CHECK-BE: xxswapd 0, 35 932; CHECK-BE: xxinsertw 34, 0, 8 933 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7> 934 ret <4 x i32> %vecins 935} 936 937define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 938entry: 939; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_ 940; CHECK: xxswapd 0, 35 941; CHECK: xxinsertw 34, 0, 0 942; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_ 943; CHECK-BE: xxsldwi 0, 35, 35, 3 944; CHECK-BE: xxinsertw 34, 0, 12 945 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0> 946 ret <4 x i32> %vecins 947} 948 949define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 950entry: 951; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_ 952; CHECK: xxsldwi 0, 35, 35, 1 953; CHECK: xxinsertw 34, 0, 0 954; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_ 955; CHECK-BE-NOT: xxsldwi 956; CHECK-BE: xxinsertw 34, 35, 12 957 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1> 958 ret <4 x i32> %vecins 959} 960 961define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 962entry: 963; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_ 964; CHECK-NOT: xxsldwi 965; CHECK: xxinsertw 34, 35, 0 966; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_ 967; CHECK-BE: xxsldwi 0, 35, 35, 1 968; CHECK-BE: xxinsertw 34, 0, 12 969 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2> 970 ret <4 x i32> %vecins 971} 972 973define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 974entry: 975; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_ 976; CHECK: xxsldwi 0, 35, 35, 3 977; CHECK: xxinsertw 34, 0, 0 978; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_ 979; CHECK-BE: xxswapd 0, 35 980; CHECK-BE: xxinsertw 34, 0, 12 981 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3> 982 ret <4 x i32> %vecins 983} 984define <4 x float> @testSameVecEl0BE(<4 x float> %a) { 985entry: 986; CHECK-BE-LABEL: testSameVecEl0BE 987; CHECK-BE: xxinsertw 34, 34, 0 988 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 5, i32 1, i32 2, i32 3> 989 ret <4 x float> %vecins 990} 991define <4 x float> @testSameVecEl2BE(<4 x float> %a) { 992entry: 993; CHECK-BE-LABEL: testSameVecEl2BE 994; CHECK-BE: xxinsertw 34, 34, 8 995 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 5, i32 3> 996 ret <4 x float> %vecins 997} 998define <4 x float> @testSameVecEl3BE(<4 x float> %a) { 999entry: 1000; CHECK-BE-LABEL: testSameVecEl3BE 1001; CHECK-BE: xxinsertw 34, 34, 12 1002 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 5> 1003 ret <4 x float> %vecins 1004} 1005define <4 x float> @testSameVecEl0LE(<4 x float> %a) { 1006entry: 1007; CHECK-LABEL: testSameVecEl0LE 1008; CHECK: xxinsertw 34, 34, 12 1009 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 6, i32 1, i32 2, i32 3> 1010 ret <4 x float> %vecins 1011} 1012define <4 x float> @testSameVecEl1LE(<4 x float> %a) { 1013entry: 1014; CHECK-LABEL: testSameVecEl1LE 1015; CHECK: xxinsertw 34, 34, 8 1016 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3> 1017 ret <4 x float> %vecins 1018} 1019define <4 x float> @testSameVecEl3LE(<4 x float> %a) { 1020entry: 1021; CHECK-LABEL: testSameVecEl3LE 1022; CHECK: xxinsertw 34, 34, 0 1023 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6> 1024 ret <4 x float> %vecins 1025} 1026define <4 x float> @insertVarF(<4 x float> %a, float %f, i32 %el) { 1027entry: 1028; CHECK-LABEL: insertVarF 1029; CHECK: stfsx 1, 1030; CHECK: lxv 1031; CHECK-BE-LABEL: insertVarF 1032; CHECK-BE: stfsx 1, 1033; CHECK-BE: lxv 1034 %vecins = insertelement <4 x float> %a, float %f, i32 %el 1035 ret <4 x float> %vecins 1036} 1037define <4 x i32> @insertVarI(<4 x i32> %a, i32 %i, i32 %el) { 1038entry: 1039; CHECK-LABEL: insertVarI 1040; CHECK: stwx 1041; CHECK: lxv 1042; CHECK-BE-LABEL: insertVarI 1043; CHECK-BE: stwx 1044; CHECK-BE: lxv 1045 %vecins = insertelement <4 x i32> %a, i32 %i, i32 %el 1046 ret <4 x i32> %vecins 1047} 1048define <4 x i32> @intrinsicInsertTest(<4 x i32> %a, <2 x i64> %b) { 1049entry: 1050; CHECK-LABEL:intrinsicInsertTest 1051; CHECK: xxinsertw 34, 35, 3 1052; CHECK: blr 1053 %ans = tail call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> %a, <2 x i64> %b, i32 3) 1054 ret <4 x i32> %ans 1055} 1056declare <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32>, <2 x i64>, i32) 1057define <2 x i64> @intrinsicExtractTest(<2 x i64> %a) { 1058entry: 1059; CHECK-LABEL: intrinsicExtractTest 1060; CHECK: xxextractuw 34, 34, 5 1061; CHECK: blr 1062 %ans = tail call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> %a, i32 5) 1063 ret <2 x i64> %ans 1064} 1065declare <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64>, i32) 1066