xref: /llvm-project/llvm/test/CodeGen/AArch64/neon-sm4-sm3.ll (revision 61cca0f2e5bbb6045bb27b822e34cd39c9c1acb1) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc %s -mtriple=aarch64 -mattr=+v8.3a,+sm4 -o - | FileCheck %s
3
4define <4 x i32> @test_vsm3partw1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
5; CHECK-LABEL: test_vsm3partw1:
6; CHECK:       // %bb.0: // %entry
7; CHECK-NEXT:    sm3partw1 v0.4s, v1.4s, v2.4s
8; CHECK-NEXT:    ret
9entry:
10  %vsm3partw1.i = tail call <4 x i32> @llvm.aarch64.crypto.sm3partw1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
11  ret <4 x i32> %vsm3partw1.i
12}
13
14define <4 x i32> @test_vsm3partw2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
15; CHECK-LABEL: test_vsm3partw2:
16; CHECK:       // %bb.0: // %entry
17; CHECK-NEXT:    sm3partw2 v0.4s, v1.4s, v2.4s
18; CHECK-NEXT:    ret
19entry:
20  %vsm3partw2.i = tail call <4 x i32> @llvm.aarch64.crypto.sm3partw2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
21  ret <4 x i32> %vsm3partw2.i
22}
23
24define <4 x i32> @test_vsm3ss1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
25; CHECK-LABEL: test_vsm3ss1:
26; CHECK:       // %bb.0: // %entry
27; CHECK-NEXT:    sm3ss1 v0.4s, v0.4s, v1.4s, v2.4s
28; CHECK-NEXT:    ret
29entry:
30  %vsm3ss1.i = tail call <4 x i32> @llvm.aarch64.crypto.sm3ss1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
31  ret <4 x i32> %vsm3ss1.i
32}
33
34define <4 x i32> @test_vsm3tt1a(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
35; CHECK-LABEL: test_vsm3tt1a:
36; CHECK:       // %bb.0: // %entry
37; CHECK-NEXT:    sm3tt1a v0.4s, v1.4s, v2.s[2]
38; CHECK-NEXT:    ret
39entry:
40  %vsm3tt1a.i = tail call <4 x i32> @llvm.aarch64.crypto.sm3tt1a(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, i64 2)
41  ret <4 x i32> %vsm3tt1a.i
42}
43
44define <4 x i32> @test_vsm3tt1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
45; CHECK-LABEL: test_vsm3tt1b:
46; CHECK:       // %bb.0: // %entry
47; CHECK-NEXT:    sm3tt1b v0.4s, v1.4s, v2.s[2]
48; CHECK-NEXT:    ret
49entry:
50  %vsm3tt1b.i = tail call <4 x i32> @llvm.aarch64.crypto.sm3tt1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, i64 2)
51  ret <4 x i32> %vsm3tt1b.i
52}
53
54define <4 x i32> @test_vsm3tt2a(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
55; CHECK-LABEL: test_vsm3tt2a:
56; CHECK:       // %bb.0: // %entry
57; CHECK-NEXT:    sm3tt2a v0.4s, v1.4s, v2.s[2]
58; CHECK-NEXT:    ret
59entry:
60  %vsm3tt2a.i = tail call <4 x i32> @llvm.aarch64.crypto.sm3tt2a(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, i64 2)
61  ret <4 x i32> %vsm3tt2a.i
62}
63
64define <4 x i32> @test_vsm3tt2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
65; CHECK-LABEL: test_vsm3tt2b:
66; CHECK:       // %bb.0: // %entry
67; CHECK-NEXT:    sm3tt2b v0.4s, v1.4s, v2.s[2]
68; CHECK-NEXT:    ret
69entry:
70  %vsm3tt2b.i = tail call <4 x i32> @llvm.aarch64.crypto.sm3tt2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, i64 2)
71  ret <4 x i32> %vsm3tt2b.i
72}
73
74define <4 x i32> @test_vsm4e(<4 x i32> %a, <4 x i32> %b) {
75; CHECK-LABEL: test_vsm4e:
76; CHECK:       // %bb.0: // %entry
77; CHECK-NEXT:    sm4e v0.4s, v1.4s
78; CHECK-NEXT:    ret
79entry:
80  %vsm4e.i = tail call <4 x i32> @llvm.aarch64.crypto.sm4e(<4 x i32> %a, <4 x i32> %b)
81  ret <4 x i32> %vsm4e.i
82}
83
84define <4 x i32> @test_vsm4ekey(<4 x i32> %a, <4 x i32> %b) {
85; CHECK-LABEL: test_vsm4ekey:
86; CHECK:       // %bb.0: // %entry
87; CHECK-NEXT:    sm4ekey v0.4s, v0.4s, v1.4s
88; CHECK-NEXT:    ret
89entry:
90  %vsm4ekey.i = tail call <4 x i32> @llvm.aarch64.crypto.sm4ekey(<4 x i32> %a, <4 x i32> %b)
91  ret <4 x i32> %vsm4ekey.i
92}
93
94declare <4 x i32> @llvm.aarch64.crypto.sm3partw1(<4 x i32>, <4 x i32>, <4 x i32>)
95declare <4 x i32> @llvm.aarch64.crypto.sm3partw2(<4 x i32>, <4 x i32>, <4 x i32>)
96declare <4 x i32> @llvm.aarch64.crypto.sm3ss1(<4 x i32>, <4 x i32>, <4 x i32>)
97declare <4 x i32> @llvm.aarch64.crypto.sm3tt1a(<4 x i32>, <4 x i32>, <4 x i32>, i64 immarg)
98declare <4 x i32> @llvm.aarch64.crypto.sm3tt2b(<4 x i32>, <4 x i32>, <4 x i32>, i64 immarg)
99declare <4 x i32> @llvm.aarch64.crypto.sm3tt2a(<4 x i32>, <4 x i32>, <4 x i32>, i64 immarg)
100declare <4 x i32> @llvm.aarch64.crypto.sm3tt1b(<4 x i32>, <4 x i32>, <4 x i32>, i64 immarg)
101declare <4 x i32> @llvm.aarch64.crypto.sm4e(<4 x i32>, <4 x i32>)
102declare <4 x i32> @llvm.aarch64.crypto.sm4ekey(<4 x i32>, <4 x i32>)
103