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/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
9 // This file contains the X86 implementation of the TargetInstrInfo class.
14 #include "X86.h"
52 #define DEBUG_TYPE "x86-instr-info"
64 " fuse, but the X86 backend currently can't"),
86 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
87 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
88 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
89 : X86 in X86InstrInfo()
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H A DX86FixupVectorConstants.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
18 #include "X86.h"
27 #define DEBUG_TYPE "x86-fixup-vector-constants"
39 return "X86 Fixup Vector Constants"; in getPassName()
59 char X86FixupVectorConstantsPass::ID = 0;
100 assert((NumBits % Bits->getBitWidth()) == 0 && "Illegal splat"); in extractConstantBits()
106 for (unsigned I = 0, E = CV->getNumOperands(); I != E; ++I) { in extractConstantBits()
127 for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) { in getSplatableConstant()
153 assert((Ty->getPrimitiveSizeInBits() % SplatBitWidth) == 0 && in getSplatableConstant()
166 if ((SplatBitWidth % NumEltsBits) == 0) { in rebuildConstant()
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H A DX86FloatingPoint.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
25 #include "X86.h"
51 #define DEBUG_TYPE "x86-codegen"
64 memset(Stack, 0, sizeof(Stack)); in FPS()
65 memset(RegMap, 0, sizeof(RegMap)); in FPS()
83 StringRef getPassName() const override { return "X86 FP Stackifier"; } in getPassName()
100 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
101 unsigned Mask = 0;
103 // Number of pre-assigned live registers in FixStack. This is 0 when the
105 unsigned FixCount = 0;
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H A DX86MCInstLower.cpp1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
9 // This file contains code to lower X86 MachineInstrs to their corresponding
335 return Subtarget.is64Bit() ? X86::RET64 : X86::RET32; in LowerMachineOperand()
374 case X86::TAILJMPr: in convertTailJumpOpcode()
375 Opcode = X86::JMP32r; in convertTailJumpOpcode()
377 case X86::TAILJMPm: in convertTailJumpOpcode()
378 Opcode = X86::JMP32m; in convertTailJumpOpcode()
380 case X86 in convertTailJumpOpcode()
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H A DX86AvoidStoreForwardingBlocks.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
36 #include "X86.h"
55 #define DEBUG_TYPE "x86-avoid-SFB"
58 "x86-disable-avoid-SFB", cl::Hidden,
59 cl::desc("X86: Disable Store Forwarding Blocks fixup."), cl::init(false));
62 "x86-sfb-inspection-limit",
63 cl::desc("X86: Number of instructions backward to "
77 return "X86 Avoid Store Forwarding Blocks"; in getPassName()
121 char X86AvoidSFBPass::ID = 0;
134 return Opcode == X86 in isXMMLoadOpcode()
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H A DX86ExpandPseudo.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
15 #include "X86.h"
30 #define DEBUG_TYPE "x86-pseudo"
31 #define X86_EXPAND_PSEUDO_NAME "X86 pseudo instruction expansion pass"
60 return "X86 pseudo instruction expansion pass"; in getPassName()
76 /// Expand X86::VASTART_SAVE_XMM_REGS into set of xmm copying instructions,
83 char X86ExpandPseudo::ID = 0;
101 MachineOperand Selector = JTInst->getOperand(0); in INITIALIZE_PASS()
107 BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86 in INITIALIZE_PASS()
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H A DX86FixupInstTuning.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
24 #include "X86.h"
34 #define DEBUG_TYPE "x86-fixup-inst-tuning"
45 StringRef getPassName() const override { return "X86 Fixup Inst Tuning"; } in getPassName()
64 char X86FixupInstTuningPass::ID = 0;
172 // `vunpcklpd/vmovlhps r, r` -> `vunpcklqdq r, r`/`vshufpd r, r, 0x00` in processInstruction()
173 // `vunpckhpd/vmovlhps r, r` -> `vunpckhqdq r, r`/`vshufpd r, r, 0xff` in processInstruction()
174 // `vunpcklpd r, r, k` -> `vunpcklqdq r, r, k`/`vshufpd r, r, k, 0x00` in processInstruction()
175 // `vunpckhpd r, r, k` -> `vunpckhqdq r, r, k`/`vshufpd r, r, k, 0xff` in processInstruction()
210 return ProcessUNPCK(NewOpc, 0x00); in processInstruction()
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H A DX86FastISel.cpp1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
9 // This file defines the X86-specific support for the FastISel class. Much
15 #include "X86.h"
161 bool foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
180 // 0 - EQ in getX86SSEConditionCode()
190 case CmpInst::FCMP_OEQ: CC = 0; break; in getX86SSEConditionCode()
219 X86::AddrIndexReg); in addFullAddress()
225 bool X86FastISel::foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I, in foldX86XALUIntrinsic()
238 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(0 in foldX86XALUIntrinsic()
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H A DX86DomainReassignment.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
15 #include "X86.h"
33 #define DEBUG_TYPE "x86-domain-reassignment"
38 "disable-x86-domain-reassignment", cl::Hidden,
39 cl::desc("X86: Disable Virtual Register Reassignment."), cl::init(false));
45 return X86::GR64RegClass.hasSubClassEq(RC) || in isGPR()
46 X86::GR32RegClass.hasSubClassEq(RC) || in isGPR()
47 X86::GR16RegClass.hasSubClassEq(RC) || in isGPR()
48 X86::GR8RegClass.hasSubClassEq(RC); in isGPR()
53 return X86 in isMask()
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H A DX86CompressEVEX.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
23 // crc32w %si, %eax ## encoding: [0x66,0xf2,0x0f,0x38,0xf1,0xc6]
25 // crc32w %si, %eax ## encoding: [0x62,0xf4,0x7
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H A DX86InstrFoldTables.cpp1 //===-- X86InstrFoldTables.cpp - X86 Instruction Folding Tables -----------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
9 // This file contains the X86 memory folding tables.
30 { X86::VANDNPDZ128rr, X86::VANDNPSZ128rmb, TB_BCAST_SS },
31 { X86::VANDNPDZ256rr, X86::VANDNPSZ256rmb, TB_BCAST_SS },
32 { X86::VANDNPDZrr, X86::VANDNPSZrmb, TB_BCAST_SS },
33 { X86
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H A DX86RegisterInfo.cpp1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
9 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // on X86.
45 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
49 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP), in X86RegisterInfo()
52 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { in X86RegisterInfo()
68 StackPtr = Use64BitReg ? X86 in X86RegisterInfo()
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H A DX86FrameLowering.cpp1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
9 // This file contains the X86 implementation of TargetFrameLowering class.
40 #define DEBUG_TYPE "x86-fl"
86 // So, this is required for x86 functions that have push sequences even
110 return IsLP64 ? X86::SUB64ri32 : X86::SUB32ri; in getSUBriOpcode()
114 return IsLP64 ? X86::ADD64ri32 : X86::ADD32ri; in getADDriOpcode()
118 return IsLP64 ? X86 in getSUBrrOpcode()
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H A DX86DynAllocaExpander.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
17 #include "X86.h"
62 unsigned StackPtr = 0;
63 unsigned SlotSize = 0;
64 int64_t StackProbeSize = 0;
67 StringRef getPassName() const override { return "X86 DynAlloca Expander"; } in getPassName()
71 char X86DynAllocaExpander::ID = 0;
81 assert(MI->getOpcode() == X86::DYN_ALLOCA_32 || in getDynAllocaAmount()
82 MI->getOpcode() == X86::DYN_ALLOCA_64); in getDynAllocaAmount()
83 assert(MI->getOperand(0).isReg()); in getDynAllocaAmount()
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H A DX86FlagsCopyLowering.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
18 /// SAHF don't work on all x86 processors and are often quite slow compared to
23 #include "X86.h"
62 #define PASS_KEY "x86-flags-copy-lowering"
74 using CondRegArray = std::array<unsigned, X86::LAST_VALID_COND + 1>;
80 StringRef getPassName() const override { return "X86 EFLAGS copy lowering"; }
100 const DebugLoc &TestLoc, X86::CondCode Cond);
103 const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs);
120 "X86 EFLAGS copy lowering", false, false)
122 "X86 EFLAG
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H A DX86FixupLEAs.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
15 #include "X86.h"
30 #define FIXUPLEA_DESC "X86 LEA Fixup"
31 #define FIXUPLEA_NAME "x86-fixup-LEAs"
154 char FixupLEAPass::ID = 0;
163 case X86::MOV32rr: in INITIALIZE_PASS()
164 case X86::MOV64rr: { in INITIALIZE_PASS()
166 const MachineOperand &Dest = MI.getOperand(0); in INITIALIZE_PASS()
169 TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r in INITIALIZE_PASS()
170 : X86::LEA64r)) in INITIALIZE_PASS()
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstPrinterCommon.cpp1 //===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
33 bool IsCMPCCXADD = X86::isCMPCCXADD(Opc); in printCondCode()
34 bool IsCCMPOrCTEST = X86::isCCMPCC(Opc) || X86::isCTESTCC(Opc); in printCondCode()
39 case 0: O << "o"; break; in printCondCode()
49 case 0xa: O << (IsCCMPOrCTEST ? "t" : "p"); break; in printCondCode()
50 case 0xb: O << (IsCCMPOrCTEST ? "f" : "np"); break; in printCondCode()
51 case 0xc: O << "l"; break; in printCondCode()
52 case 0x in printCondCode()
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H A DX86ATTInstPrinter.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
57 if (MI->getOpcode() == X86::CALLpcrel32 && in printInst()
58 (STI.hasFeature(X86::Is64Bit))) { in printInst()
60 printPCRelImm(MI, Address, 0, OS); in printInst()
62 // data16 and data32 both have the same encoding of 0x66. While data32 is in printInst()
65 // 0x66 to be interpreted as "data16" by the asm printer. in printInst()
67 else if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
68 STI.hasFeature(X86::Is16Bit)) { in printInst()
81 if (MI->getNumOperands() == 0 || in printVecCompareInstr()
92 case X86 in printVecCompareInstr()
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H A DX86IntelInstPrinter.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
46 if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
47 STI.hasFeature(X86::Is16Bit)) { in printInst()
61 if (MI->getNumOperands() == 0 || in printVecCompareInstr()
72 case X86::CMPPDrmi: case X86::CMPPDrri: in printVecCompareInstr()
73 case X86::CMPPSrmi: case X86::CMPPSrri: in printVecCompareInstr()
74 case X86::CMPSDrmi: case X86 in printVecCompareInstr()
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H A DX86BaseInfo.h1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
10 // the X86 target useful for the compiler back-end and the MC libraries.
25 namespace X86 {
29 AddrBaseReg = 0,
42 TO_NEAREST_INT = 0,
52 IP_NO_PREFIX = 0,
53 IP_HAS_OP_SIZE = 1U << 0,
70 // AVX512 embedded rounding control. This should only have values 0-3.
75 // X86 specifi
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H A DX86MCTargetDesc.cpp1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
9 // This file provides X86 specific target descriptions.
74 return MI.getFlags() & X86::IP_HAS_LOCK; in hasLockPrefix()
78 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in isMemOperand()
79 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in isMemOperand()
82 return (Base.isReg() && Base.getReg() != 0 && RC.contains(Base.getReg())) || in isMemOperand()
83 (Index.isReg() && Index.getReg() != 0 && RC.contains(Index.getReg())); in isMemOperand()
88 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is16BitMemOperand()
89 const MCOperand &Index = MI.getOperand(Op + X86 in is16BitMemOperand()
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/freebsd-src/sys/contrib/x86emu/
H A Dx86emu.c6 * Realmode X86 Emulator Library
182 push_word(emu, (uint16_t) emu->x86.R_FLG); in x86emu_intr_dispatch()
185 push_word(emu, emu->x86.R_CS); in x86emu_intr_dispatch()
186 emu->x86.R_CS = fetch_word(emu, 0, intno * 4 + 2); in x86emu_intr_dispatch()
187 push_word(emu, emu->x86.R_IP); in x86emu_intr_dispatch()
188 emu->x86.R_IP = fetch_word(emu, 0, intno * 4); in x86emu_intr_dispatch()
197 if (emu->x86.intr & INTR_SYNCH) { in x86emu_intr_handle()
198 intno = emu->x86.intno; in x86emu_intr_handle()
199 emu->x86.intr = 0; in x86emu_intr_handle()
215 emu->x86.intno = intrnum; in x86emu_intr_raise()
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
10 /// X86.
15 #include "X86.h"
51 #define DEBUG_TYPE "X86-isel"
173 if (RB.getID() == X86::GPRRegBankID) {
175 return &X86::GR8RegClass; in getRegClass()
177 return &X86::GR16RegClass; in getRegClass()
179 return &X86::GR32RegClass; in getRegClass()
181 return &X86::GR64RegClass; in getRegClass()
183 if (RB.getID() == X86 in getRegClass()
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/freebsd-src/crypto/openssl/providers/common/include/prov/
H A Dder_rsa.h21 #define DER_OID_V_hashAlgs DER_P_OBJECT, 8, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02
28 #define DER_OID_V_rsaEncryption DER_P_OBJECT, 9, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x…
35 #define DER_OID_V_id_RSAES_OAEP DER_P_OBJECT, 9, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x…
42 #define DER_OID_V_id_pSpecified DER_P_OBJECT, 9, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x…
49 #define DER_OID_V_id_RSASSA_PSS DER_P_OBJECT, 9, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x…
56 …ine DER_OID_V_md2WithRSAEncryption DER_P_OBJECT, 9, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01…
63 …ine DER_OID_V_md5WithRSAEncryption DER_P_OBJECT, 9, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01…
70 …ne DER_OID_V_sha1WithRSAEncryption DER_P_OBJECT, 9, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01…
77 … DER_OID_V_sha224WithRSAEncryption DER_P_OBJECT, 9, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01…
84 … DER_OID_V_sha256WithRSAEncryption DER_P_OBJECT, 9, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01…
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H A Dder_ec.h21 #define DER_OID_V_ecdsa_with_SHA1 DER_P_OBJECT, 7, 0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x04, 0x01
28 #define DER_OID_V_id_ecPublicKey DER_P_OBJECT, 7, 0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x02, 0x01
35 #define DER_OID_V_c2pnb163v1 DER_P_OBJECT, 8, 0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x03, 0x00, 0x01
42 #define DER_OID_V_c2pnb163v2 DER_P_OBJECT, 8, 0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x03, 0x00, 0x02
49 #define DER_OID_V_c2pnb163v3 DER_P_OBJECT, 8, 0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x03, 0x00, 0x03
56 #define DER_OID_V_c2pnb176w1 DER_P_OBJECT, 8, 0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x03, 0x00, 0x04
63 #define DER_OID_V_c2tnb191v1 DER_P_OBJECT, 8, 0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x03, 0x00, 0x05
70 #define DER_OID_V_c2tnb191v2 DER_P_OBJECT, 8, 0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x03, 0x00, 0x06
77 #define DER_OID_V_c2tnb191v3 DER_P_OBJECT, 8, 0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x03, 0x00, 0x07
84 #define DER_OID_V_c2onb191v4 DER_P_OBJECT, 8, 0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x03, 0x00, 0x08
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