Lines Matching +full:0 +full:x86
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
25 #include "X86.h"
51 #define DEBUG_TYPE "x86-codegen"
64 memset(Stack, 0, sizeof(Stack));
65 memset(RegMap, 0, sizeof(RegMap));
83 StringRef getPassName() const override { return "X86 FP Stackifier"; }
100 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
101 unsigned Mask = 0;
103 // Number of pre-assigned live registers in FixStack. This is 0 when the
105 unsigned FixCount = 0;
117 // Numbered LiveBundle structs. LiveBundles[0] is used for all CFG edges
126 unsigned Mask = 0;
130 static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums");
131 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
132 Mask |= 1 << (Reg - X86::FP0);
153 unsigned StackTop = 0; // The current top of the FP stack.
174 for (unsigned i = 0; i != StackTop; ++i) {
194 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
201 /// getSTReg - Return the X86::ST(i) register which contains the specified
204 return StackTop - 1 - getSlot(RegNo) + X86::ST0;
218 if (StackTop == 0)
220 RegMap[Stack[--StackTop]] = ~0; // Update state
229 unsigned RegOnTop = getStackEntry(0);
240 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
250 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
272 /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] is
273 /// st(0), FP reg FixStack[1] is st(1) etc.
291 Register DstReg = MI.getOperand(0).getReg();
294 return X86::RFP80RegClass.contains(DstReg) ||
295 X86::RFP80RegClass.contains(SrcReg);
302 char FPS::ID = 0;
304 INITIALIZE_PASS_BEGIN(FPS, DEBUG_TYPE, "X86 FP Stackifier",
307 INITIALIZE_PASS_END(FPS, DEBUG_TYPE, "X86 FP Stackifier",
312 /// getFPReg - Return the X86::FPx register number for the specified operand.
313 /// For example, this returns 3 for X86::FP3.
317 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
318 return Reg - X86::FP0;
329 static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
331 for (unsigned i = 0; i <= 6; ++i)
332 if (!MRI.reg_nodbg_empty(X86::FP0 + i)) {
346 StackTop = 0;
366 assert((Bundle.Mask & 0xFE) == 0 &&
369 Bundle.FixStack[0] = 0;
429 X86::RFP80RegClass.contains(MI.getOperand(0).getReg()))
454 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
455 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
468 static_assert(X86::FP7 - X86::FP0 == 7, "sequential FP regnumbers");
469 if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) {
470 LLVM_DEBUG(dbgs() << "Register FP#" << Reg - X86::FP0 << " is dead!\n");
471 freeStackSlotAfter(I, Reg-X86::FP0);
507 StackTop = 0;
521 for (unsigned i = Bundle.FixCount; i > 0; --i) {
570 for (unsigned i = 0; i < StackTop; ++i)
622 // concrete X86 instruction which uses the register stack.
625 { X86::ABS_Fp32 , X86::ABS_F },
626 { X86::ABS_Fp64 , X86::ABS_F },
627 { X86::ABS_Fp80 , X86::ABS_F },
628 { X86::ADD_Fp32m , X86::ADD_F32m },
629 { X86::ADD_Fp64m , X86::ADD_F64m },
630 { X86::ADD_Fp64m32 , X86::ADD_F32m },
631 { X86::ADD_Fp80m32 , X86::ADD_F32m },
632 { X86::ADD_Fp80m64 , X86::ADD_F64m },
633 { X86::ADD_FpI16m32 , X86::ADD_FI16m },
634 { X86::ADD_FpI16m64 , X86::ADD_FI16m },
635 { X86::ADD_FpI16m80 , X86::ADD_FI16m },
636 { X86::ADD_FpI32m32 , X86::ADD_FI32m },
637 { X86::ADD_FpI32m64 , X86::ADD_FI32m },
638 { X86::ADD_FpI32m80 , X86::ADD_FI32m },
639 { X86::CHS_Fp32 , X86::CHS_F },
640 { X86::CHS_Fp64 , X86::CHS_F },
641 { X86::CHS_Fp80 , X86::CHS_F },
642 { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
643 { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
644 { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
645 { X86::CMOVB_Fp32 , X86::CMOVB_F },
646 { X86::CMOVB_Fp64 , X86::CMOVB_F },
647 { X86::CMOVB_Fp80 , X86::CMOVB_F },
648 { X86::CMOVE_Fp32 , X86::CMOVE_F },
649 { X86::CMOVE_Fp64 , X86::CMOVE_F },
650 { X86::CMOVE_Fp80 , X86::CMOVE_F },
651 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
652 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
653 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
654 { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
655 { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
656 { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
657 { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
658 { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
659 { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
660 { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
661 { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
662 { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
663 { X86::CMOVP_Fp32 , X86::CMOVP_F },
664 { X86::CMOVP_Fp64 , X86::CMOVP_F },
665 { X86::CMOVP_Fp80 , X86::CMOVP_F },
666 { X86::COM_FpIr32 , X86::COM_FIr },
667 { X86::COM_FpIr64 , X86::COM_FIr },
668 { X86::COM_FpIr80 , X86::COM_FIr },
669 { X86::COM_Fpr32 , X86::COM_FST0r },
670 { X86::COM_Fpr64 , X86::COM_FST0r },
671 { X86::COM_Fpr80 , X86::COM_FST0r },
672 { X86::DIVR_Fp32m , X86::DIVR_F32m },
673 { X86::DIVR_Fp64m , X86::DIVR_F64m },
674 { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
675 { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
676 { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
677 { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
678 { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
679 { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
680 { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
681 { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
682 { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
683 { X86::DIV_Fp32m , X86::DIV_F32m },
684 { X86::DIV_Fp64m , X86::DIV_F64m },
685 { X86::DIV_Fp64m32 , X86::DIV_F32m },
686 { X86::DIV_Fp80m32 , X86::DIV_F32m },
687 { X86::DIV_Fp80m64 , X86::DIV_F64m },
688 { X86::DIV_FpI16m32 , X86::DIV_FI16m },
689 { X86::DIV_FpI16m64 , X86::DIV_FI16m },
690 { X86::DIV_FpI16m80 , X86::DIV_FI16m },
691 { X86::DIV_FpI32m32 , X86::DIV_FI32m },
692 { X86::DIV_FpI32m64 , X86::DIV_FI32m },
693 { X86::DIV_FpI32m80 , X86::DIV_FI32m },
694 { X86::ILD_Fp16m32 , X86::ILD_F16m },
695 { X86::ILD_Fp16m64 , X86::ILD_F16m },
696 { X86::ILD_Fp16m80 , X86::ILD_F16m },
697 { X86::ILD_Fp32m32 , X86::ILD_F32m },
698 { X86::ILD_Fp32m64 , X86::ILD_F32m },
699 { X86::ILD_Fp32m80 , X86::ILD_F32m },
700 { X86::ILD_Fp64m32 , X86::ILD_F64m },
701 { X86::ILD_Fp64m64 , X86::ILD_F64m },
702 { X86::ILD_Fp64m80 , X86::ILD_F64m },
703 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
704 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
705 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
706 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
707 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
708 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
709 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
710 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
711 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
712 { X86::IST_Fp16m32 , X86::IST_F16m },
713 { X86::IST_Fp16m64 , X86::IST_F16m },
714 { X86::IST_Fp16m80 , X86::IST_F16m },
715 { X86::IST_Fp32m32 , X86::IST_F32m },
716 { X86::IST_Fp32m64 , X86::IST_F32m },
717 { X86::IST_Fp32m80 , X86::IST_F32m },
718 { X86::IST_Fp64m32 , X86::IST_FP64m },
719 { X86::IST_Fp64m64 , X86::IST_FP64m },
720 { X86::IST_Fp64m80 , X86::IST_FP64m },
721 { X86::LD_Fp032 , X86::LD_F0 },
722 { X86::LD_Fp064 , X86::LD_F0 },
723 { X86::LD_Fp080 , X86::LD_F0 },
724 { X86::LD_Fp132 , X86::LD_F1 },
725 { X86::LD_Fp164 , X86::LD_F1 },
726 { X86::LD_Fp180 , X86::LD_F1 },
727 { X86::LD_Fp32m , X86::LD_F32m },
728 { X86::LD_Fp32m64 , X86::LD_F32m },
729 { X86::LD_Fp32m80 , X86::LD_F32m },
730 { X86::LD_Fp64m , X86::LD_F64m },
731 { X86::LD_Fp64m80 , X86::LD_F64m },
732 { X86::LD_Fp80m , X86::LD_F80m },
733 { X86::MUL_Fp32m , X86::MUL_F32m },
734 { X86::MUL_Fp64m , X86::MUL_F64m },
735 { X86::MUL_Fp64m32 , X86::MUL_F32m },
736 { X86::MUL_Fp80m32 , X86::MUL_F32m },
737 { X86::MUL_Fp80m64 , X86::MUL_F64m },
738 { X86::MUL_FpI16m32 , X86::MUL_FI16m },
739 { X86::MUL_FpI16m64 , X86::MUL_FI16m },
740 { X86::MUL_FpI16m80 , X86::MUL_FI16m },
741 { X86::MUL_FpI32m32 , X86::MUL_FI32m },
742 { X86::MUL_FpI32m64 , X86::MUL_FI32m },
743 { X86::MUL_FpI32m80 , X86::MUL_FI32m },
744 { X86::SQRT_Fp32 , X86::SQRT_F },
745 { X86::SQRT_Fp64 , X86::SQRT_F },
746 { X86::SQRT_Fp80 , X86::SQRT_F },
747 { X86::ST_Fp32m , X86::ST_F32m },
748 { X86::ST_Fp64m , X86::ST_F64m },
749 { X86::ST_Fp64m32 , X86::ST_F32m },
750 { X86::ST_Fp80m32 , X86::ST_F32m },
751 { X86::ST_Fp80m64 , X86::ST_F64m },
752 { X86::ST_FpP80m , X86::ST_FP80m },
753 { X86::SUBR_Fp32m , X86::SUBR_F32m },
754 { X86::SUBR_Fp64m , X86::SUBR_F64m },
755 { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
756 { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
757 { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
758 { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
759 { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
760 { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
761 { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
762 { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
763 { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
764 { X86::SUB_Fp32m , X86::SUB_F32m },
765 { X86::SUB_Fp64m , X86::SUB_F64m },
766 { X86::SUB_Fp64m32 , X86::SUB_F32m },
767 { X86::SUB_Fp80m32 , X86::SUB_F32m },
768 { X86::SUB_Fp80m64 , X86::SUB_F64m },
769 { X86::SUB_FpI16m32 , X86::SUB_FI16m },
770 { X86::SUB_FpI16m64 , X86::SUB_FI16m },
771 { X86::SUB_FpI16m80 , X86::SUB_FI16m },
772 { X86::SUB_FpI32m32 , X86::SUB_FI32m },
773 { X86::SUB_FpI32m64 , X86::SUB_FI32m },
774 { X86::SUB_FpI32m80 , X86::SUB_FI32m },
775 { X86::TST_Fp32 , X86::TST_F },
776 { X86::TST_Fp64 , X86::TST_F },
777 { X86::TST_Fp80 , X86::TST_F },
778 { X86::UCOM_FpIr32 , X86::UCOM_FIr },
779 { X86::UCOM_FpIr64 , X86::UCOM_FIr },
780 { X86::UCOM_FpIr80 , X86::UCOM_FIr },
781 { X86::UCOM_Fpr32 , X86::UCOM_Fr },
782 { X86::UCOM_Fpr64 , X86::UCOM_Fr },
783 { X86::UCOM_Fpr80 , X86::UCOM_Fr },
784 { X86::XAM_Fp32 , X86::XAM_F },
785 { X86::XAM_Fp64 , X86::XAM_F },
786 { X86::XAM_Fp80 , X86::XAM_F },
804 { X86::ADD_FrST0 , X86::ADD_FPrST0 },
806 { X86::COMP_FST0r, X86::FCOMPP },
807 { X86::COM_FIr , X86::COM_FIPr },
808 { X86::COM_FST0r , X86::COMP_FST0r },
810 { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
811 { X86::DIV_FrST0 , X86::DIV_FPrST0 },
813 { X86::IST_F16m , X86::IST_FP16m },
814 { X86::IST_F32m , X86::IST_FP32m },
816 { X86::MUL_FrST0 , X86::MUL_FPrST0 },
818 { X86::ST_F32m , X86::ST_FP32m },
819 { X86::ST_F64m , X86::ST_FP64m },
820 { X86::ST_Frr , X86::ST_FPrr },
822 { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
823 { X86::SUB_FrST0 , X86::SUB_FPrST0 },
825 { X86::UCOM_FIr , X86::UCOM_FIPr },
827 { X86::UCOM_FPr , X86::UCOM_FPPr },
828 { X86::UCOM_Fr , X86::UCOM_FPr },
833 MI.findRegisterDefOperand(X86::FPSW, /*TRI=*/nullptr))
844 if (X86::isX87Instruction(MI))
867 if (Opcode == X86::FCOMPP || Opcode == X86::UCOM_FPPr)
868 I->removeOperand(0);
876 if (Next != MBB.end() && Next->readsRegister(X86::FPSW, /*TRI=*/nullptr))
879 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
888 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
908 RegMap[FPRegNo] = ~0;
909 Stack[--StackTop] = ~0;
910 return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr))
919 unsigned Kills = 0;
920 for (unsigned i = 0; i < StackTop; ++i) {
929 assert((Kills & Defs) == 0 && "Register needs killing and def'ing?");
947 unsigned KReg = getStackEntry(0);
967 LLVM_DEBUG(dbgs() << "Defining %fp" << DReg << " as 0\n");
968 BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
994 if (FixCount > 0)
1007 unsigned STReturns = 0;
1010 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1015 bool ClobbersFP0 = Op.clobbersPhysReg(X86::FP0);
1017 static_assert(X86::FP7 - X86::FP0 == 7, "sequential FP regnumbers");
1019 assert(Op.clobbersPhysReg(X86::FP0 + i) == ClobbersFP0 &&
1027 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1044 assert((ClobbersFPStack || STReturns == 0) &&
1053 assert(STReturns == 0 || (isMask_32(STReturns) && N <= 2));
1058 while (StackTop > 0)
1061 for (unsigned I = 0; I < N; ++I)
1070 /// If RET has an FP register use operand, pass the first one in ST(0) and
1076 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1077 unsigned LiveMask = 0;
1079 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1081 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1092 if (FirstFPRegOp == ~0U)
1095 assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1113 // ST(0) already, so just declare success by removing the value from the
1115 if (SecondFPRegOp == ~0U) {
1117 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1123 StackTop = 0;
1131 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1144 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1146 if (getStackEntry(0) == SecondFPRegOp) {
1151 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1153 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1155 StackTop = 0;
1158 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
1162 unsigned DestReg = getFPReg(MI.getOperand(0));
1165 MI.removeOperand(0); // Remove the explicit ST(0) operand
1168 MachineOperand::CreateReg(X86::ST0, /*isDef*/ true, /*isImp*/ true));
1176 /// handleOneArgFP - fst <mem>, ST(0)
1181 assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) &&
1186 bool KillsSrc = MI.killsRegister(X86::FP0 + Reg, /*TRI=*/nullptr);
1194 if (!KillsSrc && (MI.getOpcode() == X86::IST_Fp64m32 ||
1195 MI.getOpcode() == X86::ISTT_Fp16m32 ||
1196 MI.getOpcode() == X86::ISTT_Fp32m32 ||
1197 MI.getOpcode() == X86::ISTT_Fp64m32 ||
1198 MI.getOpcode() == X86::IST_Fp64m64 ||
1199 MI.getOpcode() == X86::ISTT_Fp16m64 ||
1200 MI.getOpcode() == X86::ISTT_Fp32m64 ||
1201 MI.getOpcode() == X86::ISTT_Fp64m64 ||
1202 MI.getOpcode() == X86::IST_Fp64m80 ||
1203 MI.getOpcode() == X86::ISTT_Fp16m80 ||
1204 MI.getOpcode() == X86::ISTT_Fp32m80 ||
1205 MI.getOpcode() == X86::ISTT_Fp64m80 ||
1206 MI.getOpcode() == X86::ST_FpP80m)) {
1213 MI.removeOperand(NumOps - 1); // Remove explicit ST(0) operand
1216 MachineOperand::CreateReg(X86::ST0, /*isDef*/ false, /*isImp*/ true));
1218 if (MI.getOpcode() == X86::IST_FP64m || MI.getOpcode() == X86::ISTT_FP16m ||
1219 MI.getOpcode() == X86::ISTT_FP32m || MI.getOpcode() == X86::ISTT_FP64m ||
1220 MI.getOpcode() == X86::ST_FP80m) {
1221 if (StackTop == 0)
1249 bool KillsSrc = MI.killsRegister(X86::FP0 + Reg, /*TRI=*/nullptr);
1255 if (StackTop == 0)
1258 pushReg(getFPReg(MI.getOperand(0)));
1262 duplicateToTop(Reg, getFPReg(MI.getOperand(0)), I);
1267 MI.removeOperand(0); // Drop the destination operand.
1277 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
1279 { X86::ADD_Fp32 , X86::ADD_FST0r },
1280 { X86::ADD_Fp64 , X86::ADD_FST0r },
1281 { X86::ADD_Fp80 , X86::ADD_FST0r },
1282 { X86::DIV_Fp32 , X86::DIV_FST0r },
1283 { X86::DIV_Fp64 , X86::DIV_FST0r },
1284 { X86::DIV_Fp80 , X86::DIV_FST0r },
1285 { X86::MUL_Fp32 , X86::MUL_FST0r },
1286 { X86::MUL_Fp64 , X86::MUL_FST0r },
1287 { X86::MUL_Fp80 , X86::MUL_FST0r },
1288 { X86::SUB_Fp32 , X86::SUB_FST0r },
1289 { X86::SUB_Fp64 , X86::SUB_FST0r },
1290 { X86::SUB_Fp80 , X86::SUB_FST0r },
1293 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
1295 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
1296 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
1297 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
1298 { X86::DIV_Fp32 , X86::DIVR_FST0r },
1299 { X86::DIV_Fp64 , X86::DIVR_FST0r },
1300 { X86::DIV_Fp80 , X86::DIVR_FST0r },
1301 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
1302 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
1303 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
1304 { X86::SUB_Fp32 , X86::SUBR_FST0r },
1305 { X86::SUB_Fp64 , X86::SUBR_FST0r },
1306 { X86::SUB_Fp80 , X86::SUBR_FST0r },
1309 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
1311 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
1312 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
1313 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
1314 { X86::DIV_Fp32 , X86::DIVR_FrST0 },
1315 { X86::DIV_Fp64 , X86::DIVR_FrST0 },
1316 { X86::DIV_Fp80 , X86::DIVR_FrST0 },
1317 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
1318 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
1319 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
1320 { X86::SUB_Fp32 , X86::SUBR_FrST0 },
1321 { X86::SUB_Fp64 , X86::SUBR_FrST0 },
1322 { X86::SUB_Fp80 , X86::SUBR_FrST0 },
1325 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
1327 { X86::ADD_Fp32 , X86::ADD_FrST0 },
1328 { X86::ADD_Fp64 , X86::ADD_FrST0 },
1329 { X86::ADD_Fp80 , X86::ADD_FrST0 },
1330 { X86::DIV_Fp32 , X86::DIV_FrST0 },
1331 { X86::DIV_Fp64 , X86::DIV_FrST0 },
1332 { X86::DIV_Fp80 , X86::DIV_FrST0 },
1333 { X86::MUL_Fp32 , X86::MUL_FrST0 },
1334 { X86::MUL_Fp64 , X86::MUL_FrST0 },
1335 { X86::MUL_Fp80 , X86::MUL_FrST0 },
1336 { X86::SUB_Fp32 , X86::SUB_FrST0 },
1337 { X86::SUB_Fp64 , X86::SUB_FrST0 },
1338 { X86::SUB_Fp80 , X86::SUB_FrST0 },
1345 /// Result: ST(0) = fsub ST(0), ST(i)
1346 /// ST(i) = fsub ST(0), ST(i)
1347 /// ST(0) = fsubr ST(0), ST(i)
1348 /// ST(i) = fsubr ST(0), ST(i)
1357 unsigned Dest = getFPReg(MI.getOperand(0));
1360 bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0, /*TRI=*/nullptr);
1361 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1, /*TRI=*/nullptr);
1364 unsigned TOS = getStackEntry(0);
1458 bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0, /*TRI=*/nullptr);
1459 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1, /*TRI=*/nullptr);
1466 MI.getOperand(0).setReg(getSTReg(Op1));
1477 /// instructions move a st(i) register to st(0) iff a condition is true. These
1483 unsigned Op0 = getFPReg(MI.getOperand(0));
1485 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1, /*TRI=*/nullptr);
1492 MI.removeOperand(0);
1494 MI.getOperand(0).setReg(getSTReg(Op1));
1528 const MachineOperand &MO0 = MI.getOperand(0);
1550 // All FP registers must be explicitly defined, so load a 0 instead.
1551 unsigned Reg = MI.getOperand(0).getReg() - X86::FP0;
1553 BuildMI(*MBB, Inst, MI.getDebugLoc(), TII->get(X86::LD_F0));
1593 unsigned STUses = 0, STDefs = 0, STClobbers = 0;
1594 unsigned NumOps = 0;
1609 unsigned STReg = MO.getReg() - X86::FP0;
1664 for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I)
1666 assert((1 << getFPReg(MI.getOperand(I)) & STDefs) == 0 &&
1673 unsigned FPKills = ((1u << NumFPRegs) - 1) & ~0xff;
1675 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1692 for (unsigned I = 0; I < NumSTUses; ++I)
1702 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1704 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1714 Op.setReg(X86::ST0 + FPReg);
1720 for (unsigned i = 0; i < NumSTDefs; ++i)
1771 unsigned Reg = MO.getReg() - X86::FP0;