Lines Matching +full:0 +full:x86
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
23 // crc32w %si, %eax ## encoding: [0x66,0xf2,0x0f,0x38,0xf1,0xc6]
25 // crc32w %si, %eax ## encoding: [0x62,0xf4,0x7d,0x08,0xf1,0xc6]
41 #include "X86.h"
58 #define COMP_EVEX_NAME "x86-compress-evex"
84 char CompressEVEXPass::ID = 0;
89 if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
92 if (Reg >= X86::YMM16 && Reg <= X86::YMM31)
121 case X86::VALIGNDZ128rri:
122 case X86::VALIGNDZ128rmi:
123 case X86::VALIGNQZ128rri:
124 case X86::VALIGNQZ128rmi: {
125 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) &&
128 (Opc == X86::VALIGNQZ128rri || Opc == X86::VALIGNQZ128rmi) ? 8 : 4;
133 case X86::VSHUFF32X4Z256rmi:
134 case X86::VSHUFF32X4Z256rri:
135 case X86::VSHUFF64X2Z256rmi:
136 case X86::VSHUFF64X2Z256rri:
137 case X86::VSHUFI32X4Z256rmi:
138 case X86::VSHUFI32X4Z256rri:
139 case X86::VSHUFI64X2Z256rmi:
140 case X86::VSHUFI64X2Z256rri: {
141 assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr ||
142 NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) &&
146 // Set bit 5, move bit 1 to bit 4, copy bit 0.
147 Imm.setImm(0x20 | ((ImmVal & 2) << 3) | (ImmVal & 1));
150 case X86::VRNDSCALEPDZ128rri:
151 case X86::VRNDSCALEPDZ128rmi:
152 case X86::VRNDSCALEPSZ128rri:
153 case X86::VRNDSCALEPSZ128rmi:
154 case X86::VRNDSCALEPDZ256rri:
155 case X86::VRNDSCALEPDZ256rmi:
156 case X86::VRNDSCALEPSZ256rri:
157 case X86::VRNDSCALEPSZ256rmi:
158 case X86::VRNDSCALESDZr:
159 case X86::VRNDSCALESDZm:
160 case X86::VRNDSCALESSZr:
161 case X86::VRNDSCALESSZm:
162 case X86::VRNDSCALESDZr_Int:
163 case X86::VRNDSCALESDZm_Int:
164 case X86::VRNDSCALESSZr_Int:
165 case X86::VRNDSCALESSZm_Int:
168 // Ensure that only bits 3:0 of the immediate are used.
169 if ((ImmVal & 0xf) != ImmVal)
193 Register Reg0 = MI.getOperand(0).getReg();
195 if (!Op1.isReg() || X86::getFirstAddrOperandIdx(MI) == 1 ||
196 X86::isCFCMOVCC(MI.getOpcode()))
227 bool IsNDLike = IsND || Opc == X86::MOVBE32rr || Opc == X86::MOVBE64rr;
234 return 0;
238 return 0;
244 ? X86::getNonNDVariant(Opc)
246 MI.registerDefIsDead(X86::EFLAGS, /*TRI=*/nullptr))
247 ? X86::getNFVariant(Opc)
258 AsmComment = X86::AC_EVEX_2_LEGACY;
261 AsmComment = X86::AC_EVEX_2_VEX;
264 AsmComment = X86::AC_EVEX_2_EVEX;
273 MI.tieOperands(0, 1);