Lines Matching +full:0 +full:x86
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
10 /// X86.
15 #include "X86.h"
51 #define DEBUG_TYPE "X86-isel"
173 if (RB.getID() == X86::GPRRegBankID) {
175 return &X86::GR8RegClass;
177 return &X86::GR16RegClass;
179 return &X86::GR32RegClass;
181 return &X86::GR64RegClass;
183 if (RB.getID() == X86::VECRRegBankID) {
185 return STI.hasAVX512() ? &X86::FR16XRegClass : &X86::FR16RegClass;
187 return STI.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
189 return STI.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
191 return STI.hasAVX512() ? &X86::VR128XRegClass : &X86::VR128RegClass;
193 return STI.hasAVX512() ? &X86::VR256XRegClass : &X86::VR256RegClass;
195 return &X86::VR512RegClass;
198 if (RB.getID() == X86::PSRRegBankID) {
200 return &X86::RFP80RegClass;
202 return &X86::RFP64RegClass;
204 return &X86::RFP32RegClass;
218 unsigned SubIdx = X86::NoSubRegister;
219 if (RC == &X86::GR32RegClass) {
220 SubIdx = X86::sub_32bit;
221 } else if (RC == &X86::GR16RegClass) {
222 SubIdx = X86::sub_16bit;
223 } else if (RC == &X86::GR8RegClass) {
224 SubIdx = X86::sub_8bit;
232 if (X86::GR64RegClass.contains(Reg))
233 return &X86::GR64RegClass;
234 if (X86::GR32RegClass.contains(Reg))
235 return &X86::GR32RegClass;
236 if (X86::GR16RegClass.contains(Reg))
237 return &X86::GR16RegClass;
238 if (X86::GR8RegClass.contains(Reg))
239 return &X86::GR8RegClass;
276 // Set X86 Opcode and constrain DestReg.
279 Register DstReg = I.getOperand(0).getReg();
290 if (DstSize > SrcSize && SrcRegBank.getID() == X86::GPRRegBankID &&
291 DstRegBank.getID() == X86::GPRRegBankID) {
303 .addImm(0)
326 if (SrcRegBank.getID() == X86::GPRRegBankID &&
327 DstRegBank.getID() == X86::GPRRegBankID && SrcSize > DstSize &&
350 I.setDesc(TII.get(X86::COPY));
459 if (X86::GPRRegBankID == RB.getID())
460 return Isload ? X86::MOV8rm : X86::MOV8mr;
462 if (X86::GPRRegBankID == RB.getID())
463 return Isload ? X86::MOV16rm : X86::MOV16mr;
464 } else if (Ty == LLT::scalar(32) || Ty == LLT::pointer(0, 32)) {
465 if (X86::GPRRegBankID == RB.getID())
466 return Isload ? X86::MOV32rm : X86::MOV32mr;
467 if (X86::VECRRegBankID == RB.getID())
468 return Isload ? (HasAVX512 ? X86::VMOVSSZrm_alt :
469 HasAVX ? X86::VMOVSSrm_alt :
470 X86::MOVSSrm_alt)
471 : (HasAVX512 ? X86::VMOVSSZmr :
472 HasAVX ? X86::VMOVSSmr :
473 X86::MOVSSmr);
474 if (X86::PSRRegBankID == RB.getID())
475 return Isload ? X86::LD_Fp32m : X86::ST_Fp32m;
476 } else if (Ty == LLT::scalar(64) || Ty == LLT::pointer(0, 64)) {
477 if (X86::GPRRegBankID == RB.getID())
478 return Isload ? X86::MOV64rm : X86::MOV64mr;
479 if (X86::VECRRegBankID == RB.getID())
480 return Isload ? (HasAVX512 ? X86::VMOVSDZrm_alt :
481 HasAVX ? X86::VMOVSDrm_alt :
482 X86::MOVSDrm_alt)
483 : (HasAVX512 ? X86::VMOVSDZmr :
484 HasAVX ? X86::VMOVSDmr :
485 X86::MOVSDmr);
486 if (X86::PSRRegBankID == RB.getID())
487 return Isload ? X86::LD_Fp64m : X86::ST_Fp64m;
489 return Isload ? X86::LD_Fp80m : X86::ST_FpP80m;
492 return Isload ? (HasVLX ? X86::VMOVAPSZ128rm
494 ? X86::VMOVAPSZ128rm_NOVLX
495 : HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm)
496 : (HasVLX ? X86::VMOVAPSZ128mr
498 ? X86::VMOVAPSZ128mr_NOVLX
499 : HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
501 return Isload ? (HasVLX ? X86::VMOVUPSZ128rm
503 ? X86::VMOVUPSZ128rm_NOVLX
504 : HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm)
505 : (HasVLX ? X86::VMOVUPSZ128mr
507 ? X86::VMOVUPSZ128mr_NOVLX
508 : HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
511 return Isload ? (HasVLX ? X86::VMOVAPSZ256rm
512 : HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX
513 : X86::VMOVAPSYrm)
514 : (HasVLX ? X86::VMOVAPSZ256mr
515 : HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX
516 : X86::VMOVAPSYmr);
518 return Isload ? (HasVLX ? X86::VMOVUPSZ256rm
519 : HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX
520 : X86::VMOVUPSYrm)
521 : (HasVLX ? X86::VMOVUPSZ256mr
522 : HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX
523 : X86::VMOVUPSYmr);
526 return Isload ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
528 return Isload ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
537 assert(I.getOperand(0).isReg() && "unsupported opperand.");
538 assert(MRI.getType(I.getOperand(0).getReg()).isPointer() &&
557 AM.Base.Reg = I.getOperand(0).getReg();
568 const Register DefReg = I.getOperand(0).getReg();
606 unsigned PICBase = 0;
610 PICBase = X86::RIP;
626 I.removeOperand(0);
635 if (Ty == LLT::pointer(0, 64))
636 return X86::LEA64r;
637 else if (Ty == LLT::pointer(0, 32))
638 return STI.isTarget64BitILP32() ? X86::LEA64_32r : X86::LEA32r;
651 const Register DefReg = I.getOperand(0).getReg();
660 addOffset(MIB, 0);
665 MIB.addImm(0).addReg(0);
700 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
701 AM.Base.Reg = X86::RIP;
704 const Register DefReg = I.getOperand(0).getReg();
723 const Register DefReg = I.getOperand(0).getReg();
726 if (RBI.getRegBank(DefReg, MRI, TRI)->getID() != X86::GPRRegBankID)
729 uint64_t Val = 0;
741 NewOpc = X86::MOV8ri;
744 NewOpc = X86::MOV16ri;
747 NewOpc = X86::MOV32ri;
750 // TODO: in case isUInt<32>(Val), X86::MOV32ri can be used
752 NewOpc = X86::MOV64ri32;
754 NewOpc = X86::MOV64ri;
769 return (DstRC == &X86::FR32RegClass || DstRC == &X86::FR32XRegClass ||
770 DstRC == &X86::FR64RegClass || DstRC == &X86::FR64XRegClass) &&
771 (SrcRC == &X86::VR128RegClass || SrcRC == &X86::VR128XRegClass);
785 I.setDesc(TII.get(X86::COPY));
796 const Register DstReg = I.getOperand(0).getReg();
823 if (DstRB.getID() != X86::GPRRegBankID)
829 SubIdx = X86::NoSubRegister;
830 } else if (DstRC == &X86::GR32RegClass) {
831 SubIdx = X86::sub_32bit;
832 } else if (DstRC == &X86::GR16RegClass) {
833 SubIdx = X86::sub_16bit;
834 } else if (DstRC == &X86::GR8RegClass) {
835 SubIdx = X86::sub_8bit;
851 I.setDesc(TII.get(X86::COPY));
860 const Register DstReg = I.getOperand(0).getReg();
884 AndOpc = X86::AND8ri;
886 AndOpc = X86::AND16ri;
888 AndOpc = X86::AND32ri;
890 AndOpc = X86::AND64ri32;
906 .addImm(X86::sub_8bit);
925 const Register DstReg = I.getOperand(0).getReg();
949 if (DstRB.getID() != X86::GPRRegBankID)
960 I.setDesc(TII.get(X86::COPY));
967 .addImm(0)
980 X86::CondCode CC;
982 std::tie(CC, SwapArgs) = X86::getX86ConditionCode(
998 OpCmp = X86::CMP8rr;
1001 OpCmp = X86::CMP16rr;
1004 OpCmp = X86::CMP32rr;
1007 OpCmp = X86::CMP64rr;
1017 TII.get(X86::SETCCr), I.getOperand(0).getReg()).addImm(CC);
1038 {X86::COND_E, X86::COND_NP, X86::AND8rr},
1039 {X86::COND_NE, X86::COND_P, X86::OR8rr}};
1045 SETFOpc = &SETFOpcTable[0][0];
1048 SETFOpc = &SETFOpcTable[1][0];
1059 OpCmp = X86::UCOMISSrr;
1062 OpCmp = X86::UCOMISDrr;
1066 Register ResultReg = I.getOperand(0).getReg();
1076 Register FlagReg1 = MRI.createVirtualRegister(&X86::GR8RegClass);
1077 Register FlagReg2 = MRI.createVirtualRegister(&X86::GR8RegClass);
1079 TII.get(X86::SETCCr), FlagReg1).addImm(SETFOpc[0]);
1081 TII.get(X86::SETCCr), FlagReg2).addImm(SETFOpc[1]);
1095 X86::CondCode CC;
1097 std::tie(CC, SwapArgs) = X86::getX86ConditionCode(Predicate);
1098 assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.");
1110 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC);
1126 const Register DstReg = I.getOperand(0).getReg();
1142 OpADC = X86::ADC8rr;
1143 OpADD = X86::ADD8rr;
1144 OpSBB = X86::SBB8rr;
1145 OpSUB = X86::SUB8rr;
1148 OpADC = X86::ADC16rr;
1149 OpADD = X86::ADD16rr;
1150 OpSBB = X86::SBB16rr;
1151 OpSUB = X86::SUB16rr;
1154 OpADC = X86::ADC32rr;
1155 OpADD = X86::ADD32rr;
1156 OpSBB = X86::SBB32rr;
1157 OpSUB = X86::SUB32rr;
1160 OpADC = X86::ADC64rr;
1161 OpADD = X86::ADD64rr;
1162 OpSBB = X86::SBB64rr;
1163 OpSUB = X86::SUB64rr;
1189 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY),
1190 X86::EFLAGS)
1198 // carry is constant, support only 0.
1199 if (*val != 0)
1212 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), CarryOutReg)
1213 .addReg(X86::EFLAGS);
1229 const Register DstReg = I.getOperand(0).getReg();
1240 if (Index % DstTy.getSizeInBits() != 0)
1243 if (Index == 0) {
1258 I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rr));
1260 I.setDesc(TII.get(X86::VEXTRACTF128rr));
1265 I.setDesc(TII.get(X86::VEXTRACTF32x4Zrr));
1267 I.setDesc(TII.get(X86::VEXTRACTF64x4Zrr));
1273 // Convert to X86 VEXTRACT immediate.
1286 unsigned SubIdx = X86::NoSubRegister;
1295 SubIdx = X86::sub_xmm;
1297 SubIdx = X86::sub_ymm;
1312 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), DstReg)
1313 .addReg(SrcReg, 0, SubIdx);
1324 unsigned SubIdx = X86::NoSubRegister;
1334 SubIdx = X86::sub_xmm;
1336 SubIdx = X86::sub_ymm;
1349 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY))
1361 const Register DstReg = I.getOperand(0).getReg();
1373 if (Index % InsertRegTy.getSizeInBits() != 0)
1376 if (Index == 0 && MRI.getVRegDef(SrcReg)->isImplicitDef()) {
1391 I.setDesc(TII.get(X86::VINSERTF32x4Z256rr));
1393 I.setDesc(TII.get(X86::VINSERTF128rr));
1398 I.setDesc(TII.get(X86::VINSERTF32x4Zrr));
1400 I.setDesc(TII.get(X86::VINSERTF64x4Zrr));
1406 // Convert to X86 VINSERT immediate.
1422 unsigned DefSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
1424 for (unsigned Idx = 0; Idx < NumDefs; ++Idx) {
1446 Register DstReg = I.getOperand(0).getReg();
1493 const Register CondReg = I.getOperand(0).getReg();
1497 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TEST8ri))
1500 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::JCC_1))
1501 .addMBB(DestMBB).addImm(X86::COND_NE);
1520 const Register DstReg = I.getOperand(0).getReg();
1537 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
1540 Register AddrReg = MRI.createVirtualRegister(&X86::GR64RegClass);
1541 BuildMI(*I.getParent(), I, DbgLoc, TII.get(X86::MOV64ri), AddrReg)
1542 .addConstantPoolIndex(CPI, 0, OpFlag);
1546 LLT::pointer(0, DL.getPointerSizeInBits()), Alignment);
1555 // This is true for X86-32 always and X86-64 when in -mcmodel=small mode.
1557 // x86-32 PIC requires a PIC base register for constant pools.
1558 unsigned PICBase = 0;
1564 PICBase = X86::RIP;
1583 Register DstReg = I.getOperand(0).getReg();
1597 I.setDesc(TII.get(X86::IMPLICIT_DEF));
1599 I.setDesc(TII.get(X86::PHI));
1617 const Register DstReg = I.getOperand(0).getReg();
1626 if (!RegRB || RegRB->getID() != X86::GPRRegBankID)
1635 // For the X86 IDIV instruction, in most cases the dividend
1660 X86::AX,
1661 0,
1663 {X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AL, S}, // SDiv
1664 {X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AH, S}, // SRem
1665 {X86::DIV8r, 0, X86::MOVZX16rr8, X86::AL, U}, // UDiv
1666 {X86::DIV8r, 0, X86::MOVZX16rr8, X86::AH, U}, // URem
1667 {X86::IMUL8r, 0, X86::MOVSX16rr8, X86::AL, S}, // Mul
1668 {X86::IMUL8r, 0, X86::MOVSX16rr8, X86::AH, S}, // SMulH
1669 {X86::MUL8r, 0, X86::MOVZX16rr8, X86::AH, U}, // UMulH
1672 X86::AX,
1673 X86::DX,
1675 {X86::IDIV16r, X86::CWD, Copy, X86::AX, S}, // SDiv
1676 {X86::IDIV16r, X86::CWD, Copy, X86::DX, S}, // SRem
1677 {X86::DIV16r, X86::MOV32r0, Copy, X86::AX, U}, // UDiv
1678 {X86::DIV16r, X86::MOV32r0, Copy, X86::DX, U}, // URem
1679 {X86::IMUL16r, X86::MOV32r0, Copy, X86::AX, S}, // Mul
1680 {X86::IMUL16r, X86::MOV32r0, Copy, X86::DX, S}, // SMulH
1681 {X86::MUL16r, X86::MOV32r0, Copy, X86::DX, U}, // UMulH
1684 X86::EAX,
1685 X86::EDX,
1687 {X86::IDIV32r, X86::CDQ, Copy, X86::EAX, S}, // SDiv
1688 {X86::IDIV32r, X86::CDQ, Copy, X86::EDX, S}, // SRem
1689 {X86::DIV32r, X86::MOV32r0, Copy, X86::EAX, U}, // UDiv
1690 {X86::DIV32r, X86::MOV32r0, Copy, X86::EDX, U}, // URem
1691 {X86::IMUL32r, X86::MOV32r0, Copy, X86::EAX, S}, // Mul
1692 {X86::IMUL32r, X86::MOV32r0, Copy, X86::EDX, S}, // SMulH
1693 {X86::MUL32r, X86::MOV32r0, Copy, X86::EDX, U}, // UMulH
1696 X86::RAX,
1697 X86::RDX,
1699 {X86::IDIV64r, X86::CQO, Copy, X86::RAX, S}, // SDiv
1700 {X86::IDIV64r, X86::CQO, Copy, X86::RDX, S}, // SRem
1701 {X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U}, // UDiv
1702 {X86::DIV64r, X86::MOV32r0, Copy, X86::RDX, U}, // URem
1703 {X86::IMUL64r, X86::MOV32r0, Copy, X86::RAX, S}, // Mul
1704 {X86::IMUL64r, X86::MOV32r0, Copy, X86::RDX, S}, // SMulH
1705 {X86::MUL64r, X86::MOV32r0, Copy, X86::RDX, U}, // UMulH
1720 OpIndex = 0;
1766 Register Zero32 = MRI.createVirtualRegister(&X86::GR32RegClass);
1767 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::MOV32r0),
1776 .addReg(Zero32, 0, X86::sub_16bit);
1784 .addImm(0)
1786 .addImm(X86::sub_32bit);
1803 if (OpEntry.ResultReg == X86::AH && STI.is64Bit()) {
1804 Register SourceSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);
1805 Register ResultSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);
1807 .addReg(X86::AX);
1810 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SHR16ri),
1818 .addReg(ResultSuperReg, 0, X86::sub_8bit);
1833 unsigned DstReg = Sel.getReg(0);
1834 BuildMI(*Sel.getParent(), Sel, Sel.getDebugLoc(), TII.get(X86::TEST32rr))
1844 OpCmp = X86::CMOV_GR8;
1847 OpCmp = STI.canUseCMOV() ? X86::CMOV16rr : X86::CMOV_GR16;
1850 OpCmp = STI.canUseCMOV() ? X86::CMOV32rr : X86::CMOV_GR32;
1854 OpCmp = X86::CMOV64rr;
1860 .addImm(X86::COND_E);