Lines Matching +full:0 +full:x86
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
15 #include "X86.h"
30 #define FIXUPLEA_DESC "X86 LEA Fixup"
31 #define FIXUPLEA_NAME "x86-fixup-LEAs"
154 char FixupLEAPass::ID = 0;
163 case X86::MOV32rr: in INITIALIZE_PASS()
164 case X86::MOV64rr: { in INITIALIZE_PASS()
166 const MachineOperand &Dest = MI.getOperand(0); in INITIALIZE_PASS()
169 TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r in INITIALIZE_PASS()
170 : X86::LEA64r)) in INITIALIZE_PASS()
174 .addReg(0) in INITIALIZE_PASS()
175 .addImm(0) in INITIALIZE_PASS()
176 .addReg(0); in INITIALIZE_PASS()
188 case X86::ADD64ri32: in INITIALIZE_PASS()
189 case X86::ADD64ri32_DB: in INITIALIZE_PASS()
190 case X86::ADD32ri: in INITIALIZE_PASS()
191 case X86::ADD32ri_DB: in INITIALIZE_PASS()
198 case X86::SHL64ri: in INITIALIZE_PASS()
199 case X86::SHL32ri: in INITIALIZE_PASS()
200 case X86::INC64r: in INITIALIZE_PASS()
201 case X86::INC32r: in INITIALIZE_PASS()
202 case X86::DEC64r: in INITIALIZE_PASS()
203 case X86::DEC32r: in INITIALIZE_PASS()
204 case X86::ADD64rr: in INITIALIZE_PASS()
205 case X86::ADD64rr_DB: in INITIALIZE_PASS()
206 case X86::ADD32rr: in INITIALIZE_PASS()
207 case X86::ADD32rr_DB: in INITIALIZE_PASS()
217 return Opcode == X86::LEA32r || Opcode == X86::LEA64r || in isLEA()
218 Opcode == X86::LEA64_32r; in isLEA()
329 return Reg == X86::EBP || Reg == X86::RBP || in isInefficientLEAReg()
330 Reg == X86::R13D || Reg == X86::R13; in isInefficientLEAReg()
340 Index.getReg() != X86::NoRegister; in hasInefficientLEABaseReg()
344 return (Offset.isImm() && Offset.getImm() != 0) || Offset.isGlobal() || in hasLEAOffset()
352 case X86::LEA32r: in getADDrrFromLEA()
353 case X86::LEA64_32r: in getADDrrFromLEA()
354 return X86::ADD32rr; in getADDrrFromLEA()
355 case X86::LEA64r: in getADDrrFromLEA()
356 return X86::ADD64rr; in getADDrrFromLEA()
364 case X86::LEA32r: in getSUBrrFromLEA()
365 case X86::LEA64_32r: in getSUBrrFromLEA()
366 return X86::SUB32rr; in getSUBrrFromLEA()
367 case X86::LEA64r: in getSUBrrFromLEA()
368 return X86::SUB64rr; in getSUBrrFromLEA()
377 case X86::LEA32r: in getADDriFromLEA()
378 case X86::LEA64_32r: in getADDriFromLEA()
379 return X86::ADD32ri; in getADDriFromLEA()
380 case X86::LEA64r: in getADDriFromLEA()
381 return X86::ADD64ri32; in getADDriFromLEA()
389 case X86::LEA32r: in getINCDECFromLEA()
390 case X86::LEA64_32r: in getINCDECFromLEA()
391 return IsINC ? X86::INC32r : X86::DEC32r; in getINCDECFromLEA()
392 case X86::LEA64r: in getINCDECFromLEA()
393 return IsINC ? X86::INC64r : X86::DEC64r; in getINCDECFromLEA()
407 Register DestReg = I->getOperand(0).getReg(); in searchALUInst()
416 for (unsigned I = 0, E = CurInst->getNumOperands(); I != E; ++I) { in searchALUInst()
428 MachineOperand AluDest = CurInst->getOperand(0); in searchALUInst()
435 if (!CurInst->registerDefIsDead(X86::EFLAGS, TRI)) in searchALUInst()
458 Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg(); in checkRegUsage()
459 Register IndexReg = LeaI->getOperand(1 + X86::AddrIndexReg).getReg(); in checkRegUsage()
460 Register AluDestReg = AluI->getOperand(0).getReg(); in checkRegUsage()
506 Register AluDestReg = AluI->getOperand(0).getReg(); in optLEAALU()
507 Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg(); in optLEAALU()
508 Register IndexReg = I->getOperand(1 + X86::AddrIndexReg).getReg(); in optLEAALU()
509 if (I->getOpcode() == X86::LEA64_32r) { in optLEAALU()
510 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit); in optLEAALU()
511 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in optLEAALU()
528 .addReg(BaseReg, KilledBase ? RegState::Kill : 0); in optLEAALU()
529 NewMI1->addRegisterDead(X86::EFLAGS, TRI); in optLEAALU()
533 .addReg(IndexReg, KilledIndex ? RegState::Kill : 0); in optLEAALU()
534 NewMI2->addRegisterDead(X86::EFLAGS, TRI); in optLEAALU()
554 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in optTwoAddrLEA()
555 const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt); in optTwoAddrLEA()
556 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in optTwoAddrLEA()
557 const MachineOperand &Disp = MI.getOperand(1 + X86::AddrDisp); in optTwoAddrLEA()
558 const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg); in optTwoAddrLEA()
560 if (Segment.getReg() != 0 || !Disp.isImm() || Scale.getImm() > 1 || in optTwoAddrLEA()
561 MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I) != in optTwoAddrLEA()
565 Register DestReg = MI.getOperand(0).getReg(); in optTwoAddrLEA()
570 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP)) in optTwoAddrLEA()
574 if (MI.getOpcode() == X86::LEA64_32r) { in optTwoAddrLEA()
575 if (BaseReg != 0) in optTwoAddrLEA()
576 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit); in optTwoAddrLEA()
577 if (IndexReg != 0) in optTwoAddrLEA()
578 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in optTwoAddrLEA()
586 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 && in optTwoAddrLEA()
592 if (MI.getOpcode() == X86::LEA64_32r) { in optTwoAddrLEA()
602 } else if (DestReg == BaseReg && IndexReg == 0) { in optTwoAddrLEA()
614 if (MI.getOpcode() == X86::LEA64_32r) { in optTwoAddrLEA()
624 if (MI.getOpcode() == X86::LEA64_32r) { in optTwoAddrLEA()
634 } else if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0) { in optTwoAddrLEA()
655 if (AddrOffset >= 0) { in processInstruction()
657 MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg); in processInstruction()
658 if (p.isReg() && p.getReg() != X86::ESP) { in processInstruction()
661 MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg); in processInstruction()
662 if (q.isReg() && q.getReg() != X86::ESP) { in processInstruction()
693 const MachineOperand &Dst = MI.getOperand(0); in processInstructionForSlowLEA()
694 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in processInstructionForSlowLEA()
695 const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt); in processInstructionForSlowLEA()
696 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in processInstructionForSlowLEA()
697 const MachineOperand &Offset = MI.getOperand(1 + X86::AddrDisp); in processInstructionForSlowLEA()
698 const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg); in processInstructionForSlowLEA()
700 if (Segment.getReg() != 0 || !Offset.isImm() || in processInstructionForSlowLEA()
701 MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I, 4) != in processInstructionForSlowLEA()
707 if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR)) in processInstructionForSlowLEA()
715 if (SrcR1 != 0 && SrcR2 != 0) { in processInstructionForSlowLEA()
723 if (Offset.getImm() != 0) { in processInstructionForSlowLEA()
745 const MachineOperand &Dest = MI.getOperand(0); in processInstrForSlow3OpLEA()
746 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in processInstrForSlow3OpLEA()
747 const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt); in processInstrForSlow3OpLEA()
748 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in processInstrForSlow3OpLEA()
749 const MachineOperand &Offset = MI.getOperand(1 + X86::AddrDisp); in processInstrForSlow3OpLEA()
750 const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg); in processInstrForSlow3OpLEA()
753 MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I, 4) != in processInstrForSlow3OpLEA()
755 Segment.getReg() != X86::NoRegister) in processInstrForSlow3OpLEA()
762 if (MI.getOpcode() == X86::LEA64_32r) { in processInstrForSlow3OpLEA()
763 if (BaseReg != 0) in processInstrForSlow3OpLEA()
764 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit); in processInstrForSlow3OpLEA()
765 if (IndexReg != 0) in processInstrForSlow3OpLEA()
766 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in processInstrForSlow3OpLEA()
793 .addReg(0) in processInstrForSlow3OpLEA()
814 if (MI.getOpcode() == X86::LEA64_32r) { in processInstrForSlow3OpLEA()
836 .addImm(0) in processInstrForSlow3OpLEA()
873 if (LEAOpcode == X86::LEA64_32r) in processInstrForSlow3OpLEA()
898 .addReg(0) in processInstrForSlow3OpLEA()