Lines Matching +full:0 +full:x86
1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
9 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // on X86.
45 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
49 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
52 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
68 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
69 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
70 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
73 StackPtr = X86::ESP;
74 FramePtr = X86::EBP;
75 BasePtr = X86::ESI;
89 if (!Is64Bit && Idx == X86::sub_8bit)
90 Idx = X86::sub_8bit_hi;
101 if (!Is64Bit && SubIdx == X86::sub_8bit) {
102 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
120 if (RC == &X86::GR8_NOREXRegClass)
129 case X86::FR32RegClassID:
130 case X86::FR64RegClassID:
136 case X86::VR128RegClassID:
137 case X86::VR256RegClassID:
143 case X86::VR128XRegClassID:
144 case X86::VR256XRegClassID:
150 case X86::FR32XRegClassID:
151 case X86::FR64XRegClassID:
157 case X86::GR8RegClassID:
158 case X86::GR16RegClassID:
159 case X86::GR32RegClassID:
160 case X86::GR64RegClassID:
161 case X86::GR8_NOREX2RegClassID:
162 case X86::GR16_NOREX2RegClassID:
163 case X86::GR32_NOREX2RegClassID:
164 case X86::GR64_NOREX2RegClassID:
165 case X86::RFP32RegClassID:
166 case X86::RFP64RegClassID:
167 case X86::RFP80RegClassID:
168 case X86::VR512_0_15RegClassID:
169 case X86::VR512RegClassID:
186 case 0: // Normal GPRs.
188 return &X86::GR64RegClass;
198 ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
199 : &X86::LOW32_ADDR_ACCESSRegClass;
201 return &X86::GR32RegClass;
204 return &X86::GR64_NOSPRegClass;
206 return &X86::GR32_NOSPRegClass;
209 return &X86::GR64_NOREXRegClass;
210 return &X86::GR32_NOREXRegClass;
213 return &X86::GR64_NOREX_NOSPRegClass;
215 return &X86::GR32_NOREX_NOSPRegClass;
228 if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 &&
229 SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit)
240 return &X86::GR64_TCW64RegClass;
242 return &X86::GR64_TCRegClass;
246 return &X86::GR32RegClass;
247 return &X86::GR32_TCRegClass;
252 if (RC == &X86::CCRRegClass) {
254 return &X86::GR64RegClass;
256 return &X86::GR32RegClass;
266 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
269 return 0;
270 case X86::GR32RegClassID:
272 case X86::GR64RegClassID:
274 case X86::VR128RegClassID:
276 case X86::VR64RegClassID:
353 assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86");
475 assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86");
541 Reserved.set(X86::FPCW);
544 Reserved.set(X86::FPSW);
547 Reserved.set(X86::MXCSR);
550 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP))
554 Reserved.set(X86::SSP);
557 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP))
562 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RBP))
581 Reserved.set(X86::CS);
582 Reserved.set(X86::SS);
583 Reserved.set(X86::DS);
584 Reserved.set(X86::ES);
585 Reserved.set(X86::FS);
586 Reserved.set(X86::GS);
589 for (unsigned n = 0; n != 8; ++n)
590 Reserved.set(X86::ST0 + n);
594 // These 8-bit registers are part of the x86-64 extension even though their
596 Reserved.set(X86::SIL);
597 Reserved.set(X86::DIL);
598 Reserved.set(X86::BPL);
599 Reserved.set(X86::SPL);
600 Reserved.set(X86::SIH);
601 Reserved.set(X86::DIH);
602 Reserved.set(X86::BPH);
603 Reserved.set(X86::SPH);
605 for (unsigned n = 0; n != 8; ++n) {
607 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
611 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
616 for (unsigned n = 0; n != 16; ++n) {
617 for (MCRegAliasIterator AI(X86::XMM16 + n, this, true); AI.isValid();
625 Reserved.set(X86::R16, X86::R31WH + 1);
628 for (MCRegAliasIterator AI(X86::R14, this, true); AI.isValid(); ++AI)
630 for (MCRegAliasIterator AI(X86::R15, this, true); AI.isValid(); ++AI)
635 {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
636 X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
652 static_assert((X86::R15WH + 1 == X86::YMM0) && (X86::YMM15 + 1 == X86::K0) &&
653 (X86::K6_K7 + 1 == X86::TMMCFG) &&
654 (X86::TMM7 + 1 == X86::R16) &&
655 (X86::R31WH + 1 == X86::NUM_TARGET_REGS),
660 return X86::NUM_TARGET_REGS;
662 return X86::TMM7 + 1;
664 return X86::K6_K7 + 1;
666 return X86::YMM15 + 1;
667 return X86::R15WH + 1;
680 SmallVector<MCRegister>{X86::EAX, X86::ECX, X86::EDX},
682 (ST.hasMMX() && X86::VR64RegClass.contains(Reg));
686 if (CC == CallingConv::X86_64_SysV && IsSubReg(X86::RAX, Reg))
690 SmallVector<MCRegister>{X86::RDX, X86::RCX, X86::R8, X86::R9},
695 llvm::any_of(SmallVector<MCRegister>{X86::RDI, X86::RSI},
700 llvm::any_of(SmallVector<MCRegister>{X86::XMM0, X86::XMM1, X86::XMM2,
701 X86::XMM3, X86::XMM4, X86::XMM5,
702 X86::XMM6, X86::XMM7},
715 if (TRI.isSuperOrSubRegisterEq(X86::RSP, PhysReg))
720 if (TFI.hasFP(MF) && TRI.isSuperOrSubRegisterEq(X86::RBP, PhysReg))
727 return RC->getID() == X86::TILERegClassID;
738 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
742 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
812 if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
814 MI.getOperand(3).getReg() != X86::NoRegister ||
815 MI.getOperand(4).getImm() != 0 ||
816 MI.getOperand(5).getReg() != X86::NoRegister)
822 if (Opc == X86::LEA64_32r)
824 Register NewDestReg = MI.getOperand(0).getReg();
835 case X86::CATCHRET:
836 case X86::CLEANUPRET:
859 // X86 format. It only has a FI and an offset.
873 if (Offset != 0)
904 TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0).getFixed();
925 // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
928 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
939 // X86 format. It only has a FI and an offset.
953 if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
968 return 0;
973 return 0;
977 return 0;
979 case X86::RET:
980 case X86::RET32:
981 case X86::RET64:
982 case X86::RETI32:
983 case X86::RETI64:
984 case X86::TCRETURNdi:
985 case X86::TCRETURNri:
986 case X86::TCRETURNmi:
987 case X86::TCRETURNdi64:
988 case X86::TCRETURNri64:
989 case X86::TCRETURNmi64:
990 case X86::EH_RETURN:
991 case X86::EH_RETURN64: {
1004 if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS != X86::ESP)
1009 return 0;
1047 case X86::COPY: {
1054 case X86::PTILELOADDV:
1055 case X86::PTILELOADDT1V:
1056 case X86::PTDPBSSDV:
1057 case X86::PTDPBSUDV:
1058 case X86::PTDPBUSDV:
1059 case X86::PTDPBUUDV:
1060 case X86::PTILEZEROV:
1061 case X86::PTDPBF16PSV:
1062 case X86::PTDPFP16PSV:
1063 case X86::PTCMMIMFP16PSV:
1064 case X86::PTCMMRLFP16PSV:
1085 if (ID != X86::TILERegClassID)