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Searched defs:Src0 (Results 1 – 25 of 44) sorted by relevance

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/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h1784 MachineInstrBuilder buildAbds(const DstOp &Dst, const SrcOp &Src0, in buildXor() argument
1762 buildAnd(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildAnd() argument
1792 buildNot(const DstOp & Dst,const SrcOp & Src0) buildNot() argument
1800 buildNeg(const DstOp & Dst,const SrcOp & Src0) buildNeg() argument
1806 buildCTPOP(const DstOp & Dst,const SrcOp & Src0) buildCTPOP() argument
1811 buildCTLZ(const DstOp & Dst,const SrcOp & Src0) buildCTLZ() argument
1816 buildCTLZ_ZERO_UNDEF(const DstOp & Dst,const SrcOp & Src0) buildCTLZ_ZERO_UNDEF() argument
1821 buildCTTZ(const DstOp & Dst,const SrcOp & Src0) buildCTTZ() argument
1826 buildCTTZ_ZERO_UNDEF(const DstOp & Dst,const SrcOp & Src0) buildCTTZ_ZERO_UNDEF() argument
1831 buildBSwap(const DstOp & Dst,const SrcOp & Src0) buildBSwap() argument
1950 buildFCopysign(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildFCopysign() argument
1956 buildUITOFP(const DstOp & Dst,const SrcOp & Src0) buildUITOFP() argument
1961 buildSITOFP(const DstOp & Dst,const SrcOp & Src0) buildSITOFP() argument
1966 buildFPTOUI(const DstOp & Dst,const SrcOp & Src0) buildFPTOUI() argument
1971 buildFPTOSI(const DstOp & Dst,const SrcOp & Src0) buildFPTOSI() argument
1984 buildSMin(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildSMin() argument
1990 buildSMax(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildSMax() argument
1996 buildUMin(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildUMin() argument
2002 buildUMax(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildUMax() argument
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/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp146 Register Src0 = in runOnMachineFunction() local
198 Register Src0 = in runOnMachineFunction() local
H A DSIShrinkInstructions.cpp96 MachineOperand &Src0 = MI.getOperand(Src0Idx); foldImmediates() local
243 const MachineOperand &Src0 = MI.getOperand(0); shrinkScalarCompare() local
418 MachineOperand &Src0 = *TII->getNamedOperand(MI, AMDGPU::OpName::src0); shrinkMadFma() local
512 MachineOperand *Src0 = &MI.getOperand(1); shrinkScalarLogicOp() local
847 MachineOperand *Src0 = &MI.getOperand(1); runOnMachineFunction() local
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H A DSIPeepholeSDWA.cpp582 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); matchSDWAOperand() local
623 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); matchSDWAOperand() local
692 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); matchSDWAOperand() local
709 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); matchSDWAOperand() local
1008 if (MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0)) { isConvertibleToSDWA() local
1061 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); convertToSDWA() local
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H A DAMDGPUCombinerHelper.cpp419 matchExpandPromotedF16FMed3(MachineInstr & MI,Register Src0,Register Src1,Register Src2) matchExpandPromotedF16FMed3() argument
432 applyExpandPromotedF16FMed3(MachineInstr & MI,Register Src0,Register Src1,Register Src2) applyExpandPromotedF16FMed3() argument
H A DAMDGPUInstCombineIntrinsic.cpp45 static APFloat fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1, in fmed3AMDGCN() argument
601 Value *Src0 = II.getArgOperand(0); instCombineIntrinsic() local
631 Value *Src0 = II.getArgOperand(0); instCombineIntrinsic() local
660 Value *Src0 = II.getArgOperand(0); instCombineIntrinsic() local
763 Value *Src0 = II.getArgOperand(0); instCombineIntrinsic() local
852 Value *Src0 = II.getArgOperand(0); instCombineIntrinsic() local
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H A DSIOptimizeExecMasking.cpp536 MachineOperand &Src0 = SaveExecInst->getOperand(1); optimizeExecSequence() local
583 MachineOperand *Src0 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src0); optimizeVCMPSaveExecSequence() local
681 MachineOperand *Src0 = TII->getNamedOperand(*VCmp, AMDGPU::OpName::src0); tryRecordVCmpxAndSaveexecSequence() local
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H A DSIModeRegister.cpp182 MachineOperand Src0 = MI.getOperand(1); getInstructionMode() local
199 MachineOperand Src0 = MI.getOperand(1); getInstructionMode() local
H A DSIFoldOperands.cpp1218 MachineOperand *Src0 = getImmOrMaterializedImm(MI->getOperand(Src0Idx)); tryConstantFoldOp() local
1316 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); tryFoldCndMask() local
1354 MachineOperand *Src0 = getImmOrMaterializedImm(MI.getOperand(1)); tryFoldZeroHighBits() local
1529 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); isClamp() local
1666 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); isOMod() local
1703 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); isOMod() local
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H A DGCNVOPDUtils.cpp83 const MachineOperand &Src0 = MI.getOperand(VOPD::Component::SRC0); in checkVOPDRegConstraints() local
H A DGCNDPPCombine.cpp290 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); createDPPInst() local
684 auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0); combineDPPMov() local
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H A DAMDGPUPostLegalizerCombiner.cpp324 Register Src0; in matchCvtF32UByteN() local
419 Register Src0 = MI.getOperand(1).getReg(); in matchCombine_s_mul_u64() local
H A DSIInstrInfo.cpp2720 swapSourceModifiers(MachineInstr & MI,MachineOperand & Src0,unsigned Src0OpName,MachineOperand & Src1,unsigned Src1OpName) const swapSourceModifiers() argument
2788 MachineOperand &Src0 = MI.getOperand(Src0Idx); commuteInstructionImpl() local
3512 MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0); foldImmediate() local
3917 const MachineOperand *Src0 = &MI.getOperand(Src0Idx); convertToThreeAddress() local
3930 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0); convertToThreeAddress() local
5004 const MachineOperand &Src0 = MI.getOperand(Src0Idx); verifyInstruction() local
5026 const MachineOperand &Src0 = MI.getOperand(Src0Idx); verifyInstruction() local
5095 const MachineOperand &Src0 = MI.getOperand(Src0Idx); verifyInstruction() local
5849 MachineOperand &Src0 = MI.getOperand(Src0Idx); legalizeOperandsVOP2() local
6666 Register Src0 = MI.getOperand(1).getReg(); legalizeOperands() local
6752 MachineOperand &Src0 = MI.getOperand(Src0Idx); legalizeOperands() local
7219 MachineOperand &Src0 = Inst.getOperand(2); moveToVALUImpl() local
7544 MachineOperand &Src0 = Inst.getOperand(1); lowerSelect() local
7653 MachineOperand &Src0 = Inst.getOperand(1); lowerScalarXnor() local
7719 MachineOperand &Src0 = Inst.getOperand(1); splitScalarNotBinop() local
7748 MachineOperand &Src0 = Inst.getOperand(1); splitScalarBinOpN2() local
7775 MachineOperand &Src0 = Inst.getOperand(1); splitScalar64BitUnaryOp() local
7840 MachineOperand &Src0 = Inst.getOperand(1); splitScalarSMulU64() local
7949 MachineOperand &Src0 = Inst.getOperand(1); splitScalarSMulPseudo() local
8008 MachineOperand &Src0 = Inst.getOperand(1); splitScalar64BitBinaryOp() local
8075 MachineOperand &Src0 = Inst.getOperand(1); splitScalar64BitXnor() local
8305 MachineOperand &Src0 = Inst.getOperand(1); movePackToVALU() local
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H A DAMDGPURegBankCombiner.cpp316 MachineInstr *Src0 = getDefIgnoringCopies(MI.getOperand(1).getReg(), MRI); matchFPMed3ToClamp() local
H A DSIISelLowering.cpp4962 MachineOperand &Src0 = MI.getOperand(2); EmitInstrWithCustomInserter() local
4985 MachineOperand &Src0 = MI.getOperand(1); EmitInstrWithCustomInserter() local
5037 MachineOperand &Src0 = MI.getOperand(1); EmitInstrWithCustomInserter() local
5119 MachineOperand &Src0 = MI.getOperand(2); EmitInstrWithCustomInserter() local
5276 const MachineOperand &Src0 = MI.getOperand(1); EmitInstrWithCustomInserter() local
6055 SDValue Src0 = N->getOperand(1); lowerFCMPIntrinsic() local
6124 __anon7a836d960102(SDValue Src0, SDValue Src1, SDValue Src2, MVT ValT) lowerLaneOp() argument
6160 SDValue Src0 = N->getOperand(1); lowerLaneOp() local
6312 SDValue Src0 = N->getOperand(1); ReplaceNodeResults() local
6324 SDValue Src0 = N->getOperand(1); ReplaceNodeResults() local
8616 SDValue Src0 = Param->isAllOnes() ? Numerator : Denominator; LowerINTRINSIC_WO_CHAIN() local
9495 SDValue Src0 = Op.getOperand(4); LowerINTRINSIC_VOID() local
10571 SDValue Src0 = Op.getOperand(0); LowerFDIV16() local
13271 SDValue Src0 = N->getOperand(0); performFMed3Combine() local
13308 SDValue Src0 = N->getOperand(0); performCvtPkRTZCombine() local
13812 placeSources(ByteProvider<SDValue> & Src0,ByteProvider<SDValue> & Src1,SmallVectorImpl<DotSrc> & Src0s,SmallVectorImpl<DotSrc> & Src1s,int Step) placeSources() argument
13974 checkDot4MulSignedness(const SDValue & N,ByteProvider<SDValue> & Src0,ByteProvider<SDValue> & Src1,const SDValue & S0Op,const SDValue & S1Op,const SelectionDAG & DAG) checkDot4MulSignedness() argument
14069 auto Src0 = handleMulOperand(TempNode->getOperand(MulIdx)->getOperand(0)); performAddCombine() local
14092 auto Src0 = performAddCombine() local
14135 SDValue Src0, Src1; performAddCombine() local
15060 SDValue Src0 = Node->getOperand(1); PostISelFolding() local
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H A DSILoadStoreOptimizer.cpp1241 const auto *Src0 = TII->getNamedOperand(*CI.I, OpName); copyFromSrcRegs() local
2019 const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0); processBaseWithConstOffset() local
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H A DSIFixSGPRCopies.cpp709 MachineOperand &Src0 = MI.getOperand(Src0Idx); runOnMachineFunction() local
/llvm-project/llvm/unittests/CodeGen/GlobalISel/
H A DPatternMatchTest.cpp48 std::optional<ValueAndVReg> Src0; in TEST_F() local
122 Register Src0, Src1, Src2; in TEST_F() local
464 Register Src0; TEST_F() local
527 Register Src0; TEST_F() local
544 Register Src0, Src1; TEST_F() local
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/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp112 computeKnownBitsMin(Register Src0,Register Src1,KnownBits & Known,const APInt & DemandedElts,unsigned Depth) computeKnownBitsMin() argument
619 computeNumSignBitsMin(Register Src0,Register Src1,const APInt & DemandedElts,unsigned Depth) computeNumSignBitsMin() argument
H A DCSEMIRBuilder.cpp261 const SrcOp &Src0 = SrcOps[0]; buildInstr() local
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp298 unsigned Src0 = 0, SubReg0; in transformInstruction() local
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp53 PairedCopy(const PPCInstrInfo * TII,MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,const DebugLoc & DL,Register Dest0,Register Dest1,Register Src0,Register Src1) PairedCopy() argument
/llvm-project/llvm/lib/Transforms/Scalar/
H A DScalarizeMaskedMemIntrin.cpp148 Value *Src0 = CI->getArgOperand(3); scalarizeMaskedLoad() local
410 Value *Src0 = CI->getArgOperand(3); scalarizeMaskedGather() local
H A DInferAddressSpaces.cpp929 Value *Src0 = Op.getOperand(1); updateAddressSpace() local
/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp497 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); emitUnaryMaybeConstrainedFPBuiltin() local
514 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); emitBinaryMaybeConstrainedFPBuiltin() local
531 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); emitBinaryExpMaybeConstrainedFPBuiltin() local
551 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); emitTernaryMaybeConstrainedFPBuiltin() local
603 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); emitFPIntBuiltin() local
616 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); emitMaybeConstrainedFPToIntRoundBuiltin() local
632 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); emitFrexpBuiltin() local
3535 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitBuiltinExpr() local
18472 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
18567 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
18576 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
18589 Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
18595 Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
18625 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
18636 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
18657 Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
19076 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
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