Lines Matching defs:Src0
5081 MachineOperand &Src0 = MI.getOperand(2);
5089 .add(Src0)
5108 MachineOperand &Src0 = MI.getOperand(1);
5115 .add(Src0)
5126 MI, MRI, Src0, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
5128 MI, MRI, Src0, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
5162 MachineOperand &Src0 = MI.getOperand(1);
5168 .add(Src0)
5184 const TargetRegisterClass *Src0RC = Src0.isReg()
5185 ? MRI.getRegClass(Src0.getReg())
5197 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
5202 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
5245 MachineOperand &Src0 = MI.getOperand(2);
5251 if (Src0.isReg() && TRI->isVectorRegister(MRI, Src0.getReg())) {
5254 .addReg(Src0.getReg());
5255 Src0.setReg(RegOp0);
5304 .add(Src0)
5406 const MachineOperand &Src0 = MI.getOperand(1);
5416 const TargetRegisterClass *Src0RC = Src0.isReg()
5417 ? MRI.getRegClass(Src0.getReg())
5429 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
5434 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
6185 SDValue Src0 = N->getOperand(1);
6187 EVT CmpVT = Src0.getValueType();
6191 Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
6199 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, Src1,
6261 auto createLaneOp = [&DAG, &SL, N, IID](SDValue Src0, SDValue Src1,
6283 Operands.push_back(Src0);
6302 SDValue Src0 = N->getOperand(1);
6320 Src0 = DAG.getAnyExtOrTrunc(IsFloat ? DAG.getBitcast(IntVT, Src0) : Src0,
6333 SDValue LaneOp = createLaneOp(Src0, Src1, Src2, MVT::i32);
6387 SDValue LaneOp = createLaneOp(Src0, Src1, Src2, VT.getSimpleVT());
6400 Src0SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src0,
6428 Src0 = DAG.getBitcast(VecVT, Src0);
6436 SDValue LaneOp = createLaneOp(Src0, Src1, Src2, VecVT);
6462 SDValue Src0 = N->getOperand(1);
6466 DAG.getNode(AMDGPUISD::CVT_PKRTZ_F16_F32, SL, MVT::i32, Src0, Src1);
6474 SDValue Src0 = N->getOperand(1);
6490 Results.push_back(DAG.getNode(Opcode, SL, VT, Src0, Src1));
6492 SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1);
8860 SDValue Src0 = Param->isAllOnes() ? Numerator : Denominator;
8862 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
9746 SDValue Src0 = Op.getOperand(4);
9749 if (isTypeLegal(Src0.getValueType()))
9756 DAG.getNode(ISD::BITCAST, DL, MVT::f32, Src0), // src0
13587 SDValue Src0 = N->getOperand(0);
13591 if (isClampZeroToOne(Src0, Src1)) {
13606 if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1))
13607 std::swap(Src0, Src1);
13612 if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1))
13613 std::swap(Src0, Src1);
13616 return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Src0);
13624 SDValue Src0 = N->getOperand(0);
13626 if (Src0.isUndef() && Src1.isUndef())
14200 static void placeSources(ByteProvider<SDValue> &Src0,
14205 assert(Src0.Src.has_value() && Src1.Src.has_value());
14208 Src0s.push_back({*Src0.Src, ((Src0.SrcOffset % 4) << 24) + 0x0c0c0c,
14209 Src0.SrcOffset / 4});
14216 std::pair<ByteProvider<SDValue>, ByteProvider<SDValue>> BPP = {Src0, Src1};
14218 BPP = {Src1, Src0};
14261 // for either Src0 or Src1, so just place them arbitrarily.
14267 {*Src0.Src,
14268 ((Src0.SrcOffset % 4) << (8 * (3 - Step)) | (ZeroMask & ~FMask)),
14269 Src0.SrcOffset / 4});
14360 checkDot4MulSignedness(const SDValue &N, ByteProvider<SDValue> &Src0,
14460 auto Src0 = handleMulOperand(TempNode->getOperand(MulIdx)->getOperand(0));
14461 if (!Src0)
14468 TempNode->getOperand(MulIdx), *Src0, *Src1,
14477 placeSources(*Src0, *Src1, Src0s, Src1s, I);
14483 auto Src0 =
14485 if (!Src0)
14492 TempNode->getOperand(AddIdx), *Src0, *Src1,
14500 placeSources(*Src0, *Src1, Src0s, Src1s, I + 1);
14526 SDValue Src0, Src1;
14561 Src0 = DAG.getBitcastedAnyExtOrTrunc(FirstEltOp, SL,
14569 Src0 = resolveSources(DAG, SL, Src0s, false, true);
14582 auto Dot = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SL, MVT::i32, IID, Src0,
15560 SDValue Src0 = Node->getOperand(1);
15564 if ((Src0.isMachineOpcode() &&
15565 Src0.getMachineOpcode() != AMDGPU::IMPLICIT_DEF) &&
15566 (Src0 == Src1 || Src0 == Src2))
15569 MVT VT = Src0.getValueType().getSimpleVT();
15571 getRegClassFor(VT, Src0.getNode()->isDivergent());
15577 Src0, SDValue());
15581 if (Src0.isMachineOpcode() &&
15582 Src0.getMachineOpcode() == AMDGPU::IMPLICIT_DEF) {
15585 Src0 = Src1;
15588 Src0 = Src2;
15591 Src0 = UndefReg;
15598 Ops[1] = Src0;
16356 auto [Dst, Src0, Src1, Src2] = MI->getFirst4Regs();
16369 KB.computeKnownBitsImpl(Src0, Known0, DemandedElts, Depth + 1);